summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu/sparc (follow)
Commit message (Collapse)AuthorAgeFilesLines
* sparc: Disable FPU in interrupt contextAlexander Krutwig2015-05-302-1/+32
| | | | Update #2270.
* sparc: Remove superfluous FP enableSebastian Huber2015-05-302-22/+7
| | | | | | | The FP context save/restore makes only sense in the context of FP threads. Update #2270.
* sparc: Avoid new window for FP save/restoreSebastian Huber2015-05-301-54/+48
| | | | Update #2270.
* sparc: Improve _CPU_Context_validate()Alexander Krutwig2015-05-291-46/+49
| | | | | | | Write the pattern only once to the entry register window and the floating point registers. Update #2270.
* sparc: Add static assertionSebastian Huber2015-05-261-0/+5
|
* sparc: Delete unused CONTEXT_CONTROL_SIZESebastian Huber2015-05-261-3/+0
|
* sparc: Delete unused ISF_STACK_FRAME_OFFSETSebastian Huber2015-05-261-2/+0
|
* sparc: Add static offset assertionsSebastian Huber2015-05-261-0/+32
|
* sparc: Add support for sptests/spcontext01Alexander Krutwig2015-05-214-10/+528
| | | | | | Implement _CPU_Context_validate() and _CPU_Context_volatile_clobber(). Update #2270.
* sparc: Ensure interrupt service after ISR enableSebastian Huber2015-03-251-1/+8
|
* cpukit: add and use CPU_Uint32ptr typeGedare Bloom2015-03-161-0/+3
|
* score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITYSebastian Huber2015-03-051-16/+0
|
* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-171-6/+2
| | | | Update #2268.
* SPARC: optimize IRQ enable & disableDaniel Hellstrom2014-12-041-2/+16
| | | | | | | | | | | | | | | | * Coding style cleanups. * Use OS reserved trap 0x89 for IRQ Disable * Use OS reserved trap 0x8A for IRQ Enable * Add to SPARC CPU supplement documentation This will result in faster Disable/Enable code since the system trap handler does not need to decode which function the user wants. Besides the IRQ disable/enabled can now be inline which avoids the caller to take into account that o0-o7+g1-g4 registers are destroyed by trap handler. It was also possible to reduce the interrupt trap handler by five instructions due to this.
* SPARC: Fatal_halt use source and exit codesDaniel Hellstrom2014-10-061-8/+2
| | | | | | | | | | | | | | | The Fatal_halt handler now have two options, either halt as before or enter system error state to return to debugger or simulator. The exit-code is now also propagated to the debugger which is very useful for testing. The CPU_Fatal_halt handler was split up into two, since the only the LEON3 support the CPU power down. The LEON3 halt now uses the power-down instruction to save CPU power. This doesn't stop a potential watch-dog timer from expiring.
* sparc: Add commentSebastian Huber2014-09-181-0/+5
|
* score: Rename _BSP_Exception_frame_print()Sebastian Huber2014-09-111-8/+1
| | | | | Rename _BSP_Exception_frame_print() to _CPU_Exception_frame_print() to be in line with other CPU port functions.
* Let CPU/BSP Fatal handler have access to sourceDaniel Hellstrom2014-09-101-1/+1
| | | | | | | | | Without the source the error code does not say that much. Let it be up to the CPU/BSP to determine the error code reported on fatal shutdown. This patch does not change the current behaviour, just adds the option to handle the source of the fatal halt.
* score: Define _CPU_Start_multitasking only for LEON SPARC, not SPARC in generalDaniel Cederman2014-09-011-2/+4
| | | | | Rename _BSP_Start_multitasking to _LEON3_Start_multitasking to show that it is LEON specific
* score/sparc: Add comment on icache flush after trap table updateDaniel Cederman2014-08-221-3/+14
| | | | | | | | | | | Changes to the trap table might be missed by other cores. If the system state is up, the other cores can be notified using SMP messages that they need to flush their icache. If the up state has not been reached there is no need to notify other cores. They will do an automatic flush of the icache just after entering the up state, but before enabling interrupts. Cache invalidation is required for both single and multiprocessor systems.
* bsp/sparc: Flush icache before first time enabling interruptsDaniel Cederman2014-08-221-0/+4
| | | | | | | A secondary processor might miss changes done to the trap table if the instruction cache is not flushed. Once interrupts are enabled any other required cache flushes can be ordered via the cache manager.
* score: PR2183: Fix context switch on SMPSebastian Huber2014-07-041-1/+1
| | | | | | | | Fix context switch on SMP for ARM, PowerPC and SPARC. Atomically test and set the is executing indicator of the heir context to ensure that at most one processor uses the heir context. Break the busy wait loop also due to heir updates.
* score/sparc: Add support for paravirtualizationChristian Mauderer2014-06-033-18/+45
| | | | | | | Guest systems in paravirtualization environments run usually in user mode. Thus it is not possible to directly access the PSR and TBR registers. Use functions instead of inline assembler to access these registers if RTEMS_PARAVIRT is defined.
* SPARC: add syscall 1 (exit) function entry pointDaniel Hellstrom2014-05-231-0/+25
| | | | | | The exit SPARC system call doesn't have a function entry point like the others do. This is probably why people use TA 0x0 instruction directly for shutting down the system.
* sparc: Change asm to __asm__ to compile with -std=c99.Daniel Cederman2014-05-141-1/+1
|
* score: Fix CPU context usage on SMPSebastian Huber2014-05-082-6/+14
| | | | | | | | | | We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
* score: Implement forced thread migrationSebastian Huber2014-05-072-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* sparc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2014-04-282-33/+36
| | | | | | | | | | | | | | | | Use register g6 for the per-CPU control of the current processor. The register g6 is reserved for the operating system by the SPARC ABI. On Linux register g6 is used for a similar purpose with the same method since 1996. The register g6 must be initialized during system startup and then must remain unchanged. Since the per-CPU control is used in all critical sections of the operating system, this is a performance optimization for the operating system core procedures. An additional benefit is that the low-level context switch and interrupt processing code is now identical on non-SMP and SMP configurations.
* sparc: Optimize context switchSebastian Huber2014-04-282-51/+48
| | | | | | The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well.
* score: Clarify TLS supportSebastian Huber2014-04-171-1/+1
|
* score: SMP initialization changesSebastian Huber2014-04-141-1/+5
| | | | | | | | | | | | | | | | | Add and use _CPU_SMP_Start_processor(). Add and use _CPU_SMP_Finalize_initialization(). This makes most _CPU_SMP_Initialize() functions a bit simpler since we can calculate the minimum value of the count of processors requested by the application configuration and the count of physically or virtually available processors in the high-level code. The CPU port has now the ability to signal a processor start failure. With the support for clustered/partitioned scheduling the presence of particular processors can be configured to be optional or mandatory. There will be a fatal error only in case mandatory processors are not present. The CPU port may use a timeout to monitor the start of a processor.
* sparc: Use __leon__ multilib defineSebastian Huber2014-04-141-1/+8
|
* score: Rename Priority_bit_map_ControlSebastian Huber2014-04-031-1/+1
| | | | Rename Priority_bit_map_Control in Priority_bit_map_Word.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-218-8/+8
|
* sparc: Fix CPU counter supportSebastian Huber2014-02-243-2/+84
| | | | | | | | The SPARC processors supported by RTEMS have no built-in CPU counter support. We have to use some hardware counter module for this purpose. The BSP must provide a 32-bit register which contains the current CPU counter value and a function for the difference calculation. It can use for example the GPTIMER instance used for the clock driver.
* score: _CPU_SMP_Get_current_processor()Sebastian Huber2014-02-212-2/+2
| | | | | | | Remove RTEMS_COMPILER_PURE_ATTRIBUTE from _SMP_Get_current_processor() and all _CPU_SMP_Get_current_processor(). Make inline ASM statements volatile again. Test smptests/smpmigration01 showed that GCC optimizes too much otherwise.
* score: Rename bsp_smp_initialize()Sebastian Huber2014-02-191-0/+2
| | | | | Rename bsp_smp_initialize() into _CPU_SMP_Initialize() since every CPU port must supply this function.
* score: Use atomic API for SMP lockSebastian Huber2014-02-173-110/+0
| | | | | Use a ticket lock implementation based on atomic operations. Delete CPU port specific SMP lock implementations.
* sparc: Add atomic support for SPARC V8Sebastian Huber2014-02-172-0/+203
| | | | Use SWAP instruction with one lock for the system in the SMP case.
* sparc: Add LEON3_ASR17_PROCESSOR_INDEX_SHIFTSebastian Huber2014-02-141-0/+14
| | | | Add _LEON3_Get_current_processor().
* score: Add CPU counter supportSebastian Huber2014-02-141-0/+12
| | | | | | | | | Add a CPU counter interface to allow access to a free-running counter. It is useful to measure short time intervals. This can be used for example to enable profiling of critical low-level functions. Add two busy wait functions rtems_counter_delay_ticks() and rtems_counter_delay_nanoseconds() implemented via the CPU counter.
* sparc: Increase CPU_STRUCTURE_ALIGNMENT to 32Sebastian Huber2014-02-131-1/+1
| | | | Recent LEON4 systems use a cache line size of 32 bytes.
* sparc: Save/restore only non-volatile contextSebastian Huber2014-02-122-64/+74
| | | | | | | | | | The _CPU_Context_switch() is a normal function call. The following registers are volatile (the caller must assume that the register contents are destroyed by the callee) according to "SYSTEM V APPLICATION BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0, o1, o2, o3, o4, o5. Drop these registers from the context. Ensure that offset defines match the structure offsets.
* score: _CPU_Context_switch_to_first_task_smp()Sebastian Huber2014-02-051-14/+0
| | | | | Delete _CPU_Context_switch_to_first_task_smp() and use _CPU_Context_restore() instead.
* Add thread-local storage (TLS) supportSebastian Huber2014-02-042-2/+12
| | | | | Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
* score: Simplify <rtems/score/cpuatomic.h>WeiY2013-08-281-30/+6
| | | | Add proper license and copyright.
* sparc: Make _CPU_ISR_Dispatch_disable per-CPUSebastian Huber2013-08-092-17/+21
| | | | This variable must be available for each processor in the system.
* sparc: Move _CPU_Context_switch(), etc.Sebastian Huber2013-08-091-224/+0
| | | | | | Move the _CPU_Context_switch(), _CPU_Context_restore() and _CPU_Context_switch_to_first_task_smp() code since the method to obtain the processor index is BSP specific.
* score/cpu: Add CPU_Per_CPU_controlSebastian Huber2013-08-091-0/+7
| | | | Add CPU port specific per-CPU control.
* score/cpu: Fix _CPU_SMP_lock_Acquire()Sebastian Huber2013-07-301-1/+1
| | | | Avoid infinite loops due to compiler optimization.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-04 03:04:19 +0000