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* score/sparc: Add support for paravirtualizationChristian Mauderer2014-06-031-1/+1
| | | | | | | Guest systems in paravirtualization environments run usually in user mode. Thus it is not possible to directly access the PSR and TBR registers. Use functions instead of inline assembler to access these registers if RTEMS_PARAVIRT is defined.
* sparc: Change asm to __asm__ to compile with -std=c99.Daniel Cederman2014-05-141-1/+1
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* score: Fix CPU context usage on SMPSebastian Huber2014-05-081-2/+14
| | | | | | | | | | We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
* score: Implement forced thread migrationSebastian Huber2014-05-071-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* sparc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2014-04-281-32/+36
| | | | | | | | | | | | | | | | Use register g6 for the per-CPU control of the current processor. The register g6 is reserved for the operating system by the SPARC ABI. On Linux register g6 is used for a similar purpose with the same method since 1996. The register g6 must be initialized during system startup and then must remain unchanged. Since the per-CPU control is used in all critical sections of the operating system, this is a performance optimization for the operating system core procedures. An additional benefit is that the low-level context switch and interrupt processing code is now identical on non-SMP and SMP configurations.
* sparc: Optimize context switchSebastian Huber2014-04-281-41/+37
| | | | | | The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well.
* score: SMP initialization changesSebastian Huber2014-04-141-1/+5
| | | | | | | | | | | | | | | | | Add and use _CPU_SMP_Start_processor(). Add and use _CPU_SMP_Finalize_initialization(). This makes most _CPU_SMP_Initialize() functions a bit simpler since we can calculate the minimum value of the count of processors requested by the application configuration and the count of physically or virtually available processors in the high-level code. The CPU port has now the ability to signal a processor start failure. With the support for clustered/partitioned scheduling the presence of particular processors can be configured to be optional or mandatory. There will be a fatal error only in case mandatory processors are not present. The CPU port may use a timeout to monitor the start of a processor.
* sparc: Use __leon__ multilib defineSebastian Huber2014-04-141-1/+8
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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* sparc: Fix CPU counter supportSebastian Huber2014-02-241-2/+49
| | | | | | | | The SPARC processors supported by RTEMS have no built-in CPU counter support. We have to use some hardware counter module for this purpose. The BSP must provide a 32-bit register which contains the current CPU counter value and a function for the difference calculation. It can use for example the GPTIMER instance used for the clock driver.
* score: _CPU_SMP_Get_current_processor()Sebastian Huber2014-02-211-1/+1
| | | | | | | Remove RTEMS_COMPILER_PURE_ATTRIBUTE from _SMP_Get_current_processor() and all _CPU_SMP_Get_current_processor(). Make inline ASM statements volatile again. Test smptests/smpmigration01 showed that GCC optimizes too much otherwise.
* score: Rename bsp_smp_initialize()Sebastian Huber2014-02-191-0/+2
| | | | | Rename bsp_smp_initialize() into _CPU_SMP_Initialize() since every CPU port must supply this function.
* score: Add CPU counter supportSebastian Huber2014-02-141-0/+12
| | | | | | | | | Add a CPU counter interface to allow access to a free-running counter. It is useful to measure short time intervals. This can be used for example to enable profiling of critical low-level functions. Add two busy wait functions rtems_counter_delay_ticks() and rtems_counter_delay_nanoseconds() implemented via the CPU counter.
* sparc: Increase CPU_STRUCTURE_ALIGNMENT to 32Sebastian Huber2014-02-131-1/+1
| | | | Recent LEON4 systems use a cache line size of 32 bytes.
* sparc: Save/restore only non-volatile contextSebastian Huber2014-02-121-64/+36
| | | | | | | | | | The _CPU_Context_switch() is a normal function call. The following registers are volatile (the caller must assume that the register contents are destroyed by the callee) according to "SYSTEM V APPLICATION BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0, o1, o2, o3, o4, o5. Drop these registers from the context. Ensure that offset defines match the structure offsets.
* score: _CPU_Context_switch_to_first_task_smp()Sebastian Huber2014-02-051-14/+0
| | | | | Delete _CPU_Context_switch_to_first_task_smp() and use _CPU_Context_restore() instead.
* Add thread-local storage (TLS) supportSebastian Huber2014-02-041-1/+3
| | | | | Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
* sparc: Make _CPU_ISR_Dispatch_disable per-CPUSebastian Huber2013-08-091-10/+14
| | | | This variable must be available for each processor in the system.
* score/cpu: Add CPU_Per_CPU_controlSebastian Huber2013-08-091-0/+7
| | | | Add CPU port specific per-CPU control.
* score: PR1782: CPU_USE_DEFERRED_FP_SWITCHSebastian Huber2013-07-231-1/+5
| | | | Do not redefine CPU_USE_DEFERRED_FP_SWITCH.
* smp: Rename _CPU_Processor_event_receive()Sebastian Huber2013-07-171-1/+1
| | | | Rename to _CPU_SMP_Processor_event_receive().
* smp: Rename _CPU_Processor_event_broadcast()Sebastian Huber2013-07-171-1/+1
| | | | Rename to _CPU_SMP_Processor_event_broadcast().
* smp: Add and use _CPU_SMP_Send_interrupt()Sebastian Huber2013-07-171-0/+2
| | | | Delete bsp_smp_interrupt_cpu().
* smp: Add and use _CPU_SMP_Get_current_processor()Sebastian Huber2013-07-171-0/+2
| | | | | | | | | | Add and use _SMP_Get_current_processor() and rtems_smp_get_current_processor(). Delete bsp_smp_interrupt_cpu(). Change type of current processor index from int to uint32_t to match _SMP_Processor_count type.
* smp: New SMP lock APISebastian Huber2013-05-311-18/+0
| | | | | | | | | | | | | | Move the SMP lock implementation to the CPU port. An optimal SMP lock implementation is highly architecture dependent. For example the memory models may be fundamentally different. The new SMP lock API has a flaw. It does not provide the ability to use a local context for acquire and release pairs. Such a context is necessary to implement for example the Mellor-Crummey and Scott (MCS) locks. The SMP lock is currently used in _Thread_Disable_dispatch() and _Thread_Enable_dispatch() and makes them to a giant lock acquire and release. Since these functions do not pass state information via a local context there is currently no use case for such a feature.
* smp: Simplify SMP initialization sequenceSebastian Huber2013-05-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delete bsp_smp_wait_for(). Other parts of the system work without timeout, e.g. the spinlocks. Using a timeout here does not make the system more robust. Delete bsp_smp_cpu_state and replace it with Per_CPU_State. The Per_CPU_State follows the Score naming conventions. Add _Per_CPU_Change_state() and _Per_CPU_Wait_for_state() functions to change and observe states. Use Per_CPU_State in Per_CPU_Control instead of the anonymous integer. Add _CPU_Processor_event_broadcast() and _CPU_Processor_event_receive() functions provided by the CPU port. Use these functions in _Per_CPU_Change_state() and _Per_CPU_Wait_for_state(). Add prototype for _SMP_Send_message(). Delete RTEMS_BSP_SMP_FIRST_TASK message. The first context switch is now performed in rtems_smp_secondary_cpu_initialize(). Issuing the first context switch in the context of the inter-processor interrupt is not possible on systems with a modern interrupt controller. Such an interrupt controler usually requires a handshake protocol with interrupt acknowledge and end of interrupt signals. A direct context switch in an interrupt handler circumvents the interrupt processing epilogue and may leave the system in an inconsistent state. Release lock in rtems_smp_process_interrupt() even if no message was delivered. This prevents deadlock of the system. Simplify and format _SMP_Send_message(), _SMP_Request_other_cores_to_perform_first_context_switch(), _SMP_Request_other_cores_to_dispatch() and _SMP_Request_other_cores_to_shutdown().
* score: Add CPU context validationSebastian Huber2013-05-101-0/+12
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* sparc/cpu.h: Add commentsJoel Sherrill2013-03-181-0/+3
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* cpukit: Use Consistent Beginning of Doxygen Group NotationJoel Sherrill2013-01-101-2/+1
| | | | | This is the result of a sed script which converts all uses of @{ into a consistent form.
* score: Doxygen Clean Up Task #4Alex Ivanov2013-01-081-326/+328
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* Miscellaneous Doxygen clean-upJoel Sherrill2012-12-281-0/+2
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* sparc cpu.h: Correct spacingJoel Sherrill2012-11-301-1/+1
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* score: Add CPU_Exception_frameSebastian Huber2012-11-271-0/+14
| | | | | | | | | | | | | | | | | | | | | Add CPU port type CPU_Exception_frame and function _CPU_Exception_frame_print(). The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh, sparc64, and v850 use an empty default implementation of _CPU_Exception_frame_print(). Add rtems_exception_frame and rtems_exception_frame_print(). Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal() with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc, and sparc for unexpected exceptions. Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the BSP_PRINT_EXCEPTION_CONTEXT define used in the default bsp_fatal_extension(). Add test sptests/spfatal26.
* score: PR1607: Add and use CPU_SIZEOF_POINTERSebastian Huber2012-11-221-0/+2
| | | | | | | | | | | | | | | | | Add and use new CPU port define CPU_SIZEOF_POINTER. It must be an integer literal that can be used by the assembler. This value will be used to calculate offsets of structure members. These offsets will be used in assembler code. The size of a pointer is part of the application binary interface (ABI) and thus independent of the actual programming language. The compiler will provide defines to determine the current ABI. We use these defines to select the appropriate CPU_SIZEOF_POINTER value. Static assertions in the new file "cpukit/score/src/percpuasm.c" will ensure that the value of CPU_SIZEOF_POINTER is consistent with the current compiler settings. Also the offset values used by assembler code are verfied.
* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2011-09-27 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-271-0/+2
| | | | | PR 1914/cpukit * rtems/score/cpu.h: Select timestamp implementation.
* 2011-06-21 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2011-06-211-272/+522
| | | | | * rtems/score/cpu.h, rtems/score/sparc.h, rtems/score/types.h: Convert comments to Doxygen style and improve.
* 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>Joel Sherrill2011-03-161-1/+30
| | | | | | | | | | | | | | | | | | | | | | PR 1729/cpukit * configure.ac, sapi/include/confdefs.h, sapi/src/exinit.c, score/Makefile.am, score/preinstall.am, score/cpu/i386/rtems/score/cpu.h, score/cpu/sparc/cpu_asm.S, score/cpu/sparc/rtems/score/cpu.h, score/include/rtems/score/basedefs.h, score/include/rtems/score/context.h, score/include/rtems/score/percpu.h, score/src/percpu.c, score/src/thread.c, score/src/threadcreateidle.c: Add next step in SMP support. This adds an allocated array of the Per_CPU structures to support multiple cpus vs a single instance of the structure which is still used if SMP support is disabled. Configuration support is also added to explicitly enable or disable SMP. But SMP can only be enabled for the CPUs which will support it initially -- SPARC and i386. With the stub BSP support, a BSP can be run as a single core SMP system from an RTEMS data structure standpoint. * aclocal/check-smp.m4, aclocal/enable-smp.m4, score/include/rtems/bspsmp.h, score/include/rtems/score/smplock.h, score/src/smp.c, score/src/smplock.c: New files.
* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-111-2/+2
| | | | | * rtems/score/cpu.h, rtems/score/sparc.h: Use "__asm__" instead of "asm" for improved c99-compliance.
* 2010-10-21 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-10-211-1/+1
| | | | | | * rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to _CPU_Context_restore() because it does not return. Telling GCC this avoids generation of dead code.
* 2010-07-16 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2010-07-161-3/+1
| | | | | * rtems/score/cpu.h: Include <rtems/score/types.h> first. * rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
* 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-06-291-16/+1
| | | | | | | | PR 1573/cpukit * cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
* Whitespace removal.Ralf Corsepius2009-12-021-26/+26
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* 2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2009-02-121-2/+2
| | | | | * rtems/score/cpu.h: Change prototype of IDLE thread to consistently return void * and take a uintptr_t argument.
* 2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2009-02-111-3/+1
| | | | | | * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch to _CPU_Initialize. Clean up comments.
* Convert to "bool".Ralf Corsepius2008-09-051-1/+1
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* 2008-08-04 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-08-041-3/+0
| | | | | | PR 1294/bsps * rtems/score/cpu.h, rtems/score/sparc.h: Correct prototype and usage of sparc_disable_interrupts.
* 2008-08-04 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-08-041-0/+1
| | | | * rtems/score/cpu.h: Spacing.
* 2008-07-31 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-07-311-1/+1
| | | | * rtems/score/cpu.h: Correct prototype of Idle threads.
* 2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-06-051-0/+13
| | | | | | | | * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting parameter to indicate that the port uses the Simple Vectored Interrupt model or the Programmable Interrupt Controller Model. The PIC model is implemented primarily in the BSP and it is responsible for all memory allocation.
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