Whitespace removal.

1 files changed, 26 insertions, 26 deletions

diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index b88de1ca8f..3e30e9a7f8 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -3,7 +3,7 @@
  */
 
 /*
- *  This include file contains information pertaining to the port of 
+ *  This include file contains information pertaining to the port of
  *  the executive to the SPARC processor.
  *
  *  COPYRIGHT (c) 1989-2006.
@@ -103,7 +103,7 @@ extern "C" {
 
 /*
  *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector 
+ *  a pointer to the saved interrupt frame (1) or just the vector
  *  number (0)?
  */
 
@@ -191,7 +191,7 @@ extern "C" {
  *  the minimum requirements of the compiler in order to have as
  *  much of the critical data area as possible in a cache line.
  *
- *  The SPARC does not appear to have particularly strict alignment 
+ *  The SPARC does not appear to have particularly strict alignment
  *  requirements.  This value was chosen to take advantages of caches.
  */
 
@@ -216,7 +216,7 @@ extern "C" {
 #define CPU_MODES_INTERRUPT_MASK   0x0000000F
 
 /*
- *  This structure represents the organization of the minimum stack frame 
+ *  This structure represents the organization of the minimum stack frame
  *  for the SPARC.  More framing information is required in certain situaions
  *  such as when there are a large number of out parameters or when the callee
  *  must save floating point registers.
@@ -306,7 +306,7 @@ typedef struct {
 
 typedef struct {
     /*
-     *  Using a double g0_g1 will put everything in this structure on a 
+     *  Using a double g0_g1 will put everything in this structure on a
      *  double word boundary which allows us to use double word loads
      *  and stores safely in the context switch.
      */
@@ -512,11 +512,11 @@ typedef struct {
 #define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
 #define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
 
-#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 
+#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
 #ifndef ASM
 /*
  *  This variable is contains the initialize context for the FP unit.
- *  It is filled in by _CPU_Initialize and copied into the task's FP 
+ *  It is filled in by _CPU_Initialize and copied into the task's FP
  *  context area during _CPU_Context_Initialize.
  */
 
@@ -555,14 +555,14 @@ SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
  *        long jump.  The other instructions load one register with the
  *        trap type (a.k.a. vector) and another with the psr.
  */
- 
+
 typedef struct {
   uint32_t     mov_psr_l0;                     /* mov   %psr, %l0           */
   uint32_t     sethi_of_handler_to_l4;         /* sethi %hi(_handler), %l4  */
   uint32_t     jmp_to_low_of_handler_plus_l4;  /* jmp   %l4 + %lo(_handler) */
   uint32_t     mov_vector_l3;                  /* mov   _vector, %l3        */
 } CPU_Trap_table_entry;
- 
+
 /*
  *  This is the set of opcodes for the instructions loaded into a trap
  *  table entry.  The routine which installs a handler is responsible
@@ -572,11 +572,11 @@ typedef struct {
  *  The constants following this structure are masks for the fields which
  *  must be filled in when the handler is installed.
  */
- 
+
 extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
 
 /*
- *  The size of the floating point context area.  
+ *  The size of the floating point context area.
  */
 
 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
@@ -714,7 +714,7 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
 
 #define _CPU_ISR_Disable( _level ) \
   (_level) = sparc_disable_interrupts()
- 
+
 /*
  *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
  *  This indicates the end of a critical section.  The parameter
@@ -733,18 +733,18 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
 
 #define _CPU_ISR_Flash( _level ) \
   sparc_flash_interrupts( _level )
- 
+
 /*
  *  Map interrupt level in task mode onto the hardware that the CPU
  *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a straight fashion are undefined.  
+ *  map onto the CPU in a straight fashion are undefined.
  */
 
 #define _CPU_ISR_Set_level( _newlevel ) \
    sparc_enable_interrupts( _newlevel << 8)
- 
+
 uint32_t   _CPU_ISR_Get_level( void );
- 
+
 /* end of ISR handler macros */
 
 /* Context handler macros */
@@ -780,7 +780,7 @@ void _CPU_Context_Initialize(
  *  On the SPARC, this is setting the frame pointer so GDB is happy.
  *  Make GDB stop unwinding at _Thread_Handler, previous register window
  *  Frame pointer is 0 and calling address must be a function with starting
- *  with a SAVE instruction. If return address is leaf-function (no SAVE) 
+ *  with a SAVE instruction. If return address is leaf-function (no SAVE)
  *  GDB will not look at prev reg window fp.
  *
  *  _Thread_Handler is known to start with SAVE.
@@ -793,7 +793,7 @@ void _CPU_Context_Initialize(
 
 /*
  *  This routine is responsible for somehow restarting the currently
- *  executing task.  
+ *  executing task.
  *
  *  On the SPARC, this is is relatively painless but requires a small
  *  amount of wrapper code before using the regular restore code in
@@ -815,7 +815,7 @@ void _CPU_Context_Initialize(
  *  This routine initializes the FP context area passed to it to.
  *
  *  The SPARC allows us to use the simple initialization model
- *  in which an "initial" FP context was saved into _CPU_Null_fp_context 
+ *  in which an "initial" FP context was saved into _CPU_Null_fp_context
  *  at CPU initialization and it is simply copied into the destination
  *  context.
  */
@@ -891,7 +891,7 @@ void _CPU_Initialize(void);
  *  This routine installs new_handler to be directly called from the trap
  *  table.
  */
- 
+
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
   proc_ptr    new_handler,
@@ -911,14 +911,14 @@ void _CPU_ISR_install_vector(
 );
 
 #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
- 
+
 /*
  *  _CPU_Thread_Idle_body
  *
  *  Some SPARC implementations have low power, sleep, or idle modes.  This
  *  tries to take advantage of those models.
  */
- 
+
 void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
 #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
@@ -972,7 +972,7 @@ void _CPU_Context_restore_fp(
  *  It must be static because it is referenced indirectly.
  *
  *  This version will work on any processor, but if you come across a better
- *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit 
+ *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
  *  entity as shown below is not any more efficient on the SPARC.
  *
  *     swap least significant two bytes with 16-bit rotate
@@ -983,18 +983,18 @@ void _CPU_Context_restore_fp(
  *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
  *  following code at optimization level four (i.e. -O4).
  */
- 
+
 static inline uint32_t CPU_swap_u32(
   uint32_t value
 )
 {
   uint32_t   byte1, byte2, byte3, byte4, swapped;
- 
+
   byte4 = (value >> 24) & 0xff;
   byte3 = (value >> 16) & 0xff;
   byte2 = (value >> 8)  & 0xff;
   byte1 =  value        & 0xff;
- 
+
   swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
   return( swapped );
 }