diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2011-03-16 20:05:06 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2011-03-16 20:05:06 +0000 |
| commit | 06dcaf09e6c0eae0b3a3c8d84adb663d03a53a4b (patch) | |
| tree | 931cf314d5a87d1d3dcd6e5c366b5ce58270a6aa /cpukit/score/cpu/sparc/rtems/score/cpu.h | |
| parent | 2011-03-16 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
| download | rtems-06dcaf09e6c0eae0b3a3c8d84adb663d03a53a4b.tar.bz2 | |
2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>
PR 1729/cpukit
* configure.ac, sapi/include/confdefs.h, sapi/src/exinit.c,
score/Makefile.am, score/preinstall.am,
score/cpu/i386/rtems/score/cpu.h, score/cpu/sparc/cpu_asm.S,
score/cpu/sparc/rtems/score/cpu.h,
score/include/rtems/score/basedefs.h,
score/include/rtems/score/context.h,
score/include/rtems/score/percpu.h, score/src/percpu.c,
score/src/thread.c, score/src/threadcreateidle.c: Add next step in
SMP support. This adds an allocated array of the Per_CPU structures
to support multiple cpus vs a single instance of the structure which
is still used if SMP support is disabled. Configuration support is
also added to explicitly enable or disable SMP. But SMP can only be
enabled for the CPUs which will support it initially -- SPARC and
i386. With the stub BSP support, a BSP can be run as a single core
SMP system from an RTEMS data structure standpoint.
* aclocal/check-smp.m4, aclocal/enable-smp.m4,
score/include/rtems/bspsmp.h, score/include/rtems/score/smplock.h,
score/src/smp.c, score/src/smplock.c: New files.
Diffstat (limited to 'cpukit/score/cpu/sparc/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/sparc/rtems/score/cpu.h | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index ddc5badfe5..330f56c6a3 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -6,7 +6,7 @@ * This include file contains information pertaining to the port of * the executive to the SPARC processor. * - * COPYRIGHT (c) 1989-2006. + * COPYRIGHT (c) 1989-2011. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -927,6 +927,35 @@ void _CPU_Context_restore( Context_Control *new_context ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; +#if defined(RTEMS_SMP) + /* + * _CPU_Context_switch_to_first_task_smp + * + * This routine is only used to switch to the first task on a + * secondary core in an SMP configuration. We do not need to + * flush all the windows and, in fact, this can be dangerous + * as they may or may not be initialized properly. + */ + void _CPU_Context_switch_to_first_task_smp( + Context_Control *new_context + ); + + /* address space 1 is uncacheable */ + #define SMP_CPU_SWAP( _address, _value, _previous ) \ + do { \ + register unsigned int _val = _value; \ + asm volatile( \ + "swapa [%2] %3, %0" : \ + "=r" (_val) : \ + "0" (_val), \ + "r" (_address), \ + "i" (1) \ + ); \ + _previous = _val; \ + } while (0) + +#endif + /* * _CPU_Context_save_fp * |