rtems - RTEMS Kernel, file-systems, drivers, BSPs, samples, and testsuite.

	Commit message (Expand)	Author	Files	Lines
2019-04-02	doxygen: score: Add RISC-V CPU architecture group	Andreas Dachsberger	4	-1/+26
2019-03-26	score: Rename ScoreCPU Doxygen group	Sebastian Huber	1	-1/+1
2019-03-14	Remove superfluous <rtems/system.h> includes	Sebastian Huber	1	-1/+0
2019-02-28	Remove explicit file names from @file	Sebastian Huber	3	-3/+3
2019-02-02	riscv: Fix misaligned access in context validate	Sebastian Huber	1	-1/+1
2019-01-22	riscv: add griscv bsp	Jiri Gaisler	1	-4/+1
2019-01-22	grlib: use cpu-independent routines for uncached access	Jiri Gaisler	3	-0/+83
2019-01-09	riscv: Enable robust thread dispatch	Sebastian Huber	1	-0/+3
2018-10-10	build: Include header.am in cpukit/Makefile.am	Sebastian Huber	2	-14/+7
2018-10-10	build: Merge score/cpu/*/Makefile.am	Sebastian Huber	1	-12/+0
2018-10-09	build: Remove specialized CPPFLAGS	Sebastian Huber	1	-1/+0
2018-10-05	score: Remove CPU_PROVIDES_IDLE_THREAD_BODY	Sebastian Huber	1	-1/+0
2018-08-02	score: Remove CPU_PARTITION_ALIGNMENT	Sebastian Huber	1	-2/+0
2018-08-02	riscv: Fix CPU_ALIGNMENT	Sebastian Huber	1	-1/+3
2018-07-27	riscv: Rework CPU counter support	Sebastian Huber	4	-5/+91
2018-07-25	riscv: Add CLINT and PLIC support	Sebastian Huber	1	-5/+45
2018-07-25	riscv: Use wfi instruction for idle task	Sebastian Huber	2	-12/+3
2018-07-25	riscv: Rework exception handling	Sebastian Huber	6	-144/+54
2018-07-25	riscv: New CPU_Exception_frame	Sebastian Huber	4	-64/+203
2018-07-25	riscv: Add exception codes	Sebastian Huber	1	-0/+39
2018-07-23	score: Add _CPU_Instruction_illegal()	Sebastian Huber	1	-0/+5
2018-07-20	score: Add _CPU_Instruction_no_operation()	Sebastian Huber	1	-0/+5
2018-07-20	score: Move context validation declarations	Sebastian Huber	2	-4/+4
2018-07-20	score: Remove obsolete CPU port defines	Sebastian Huber	1	-4/+0
2018-07-06	riscv: Add LADDR assembler define	Sebastian Huber	2	-2/+12
2018-07-06	riscv: Implement CPU counter	Sebastian Huber	2	-2/+16
2018-07-05	riscv: Clear reservations	Sebastian Huber	5	-6/+25
2018-07-02	riscv: Fix fcsr initialization	Sebastian Huber	2	-1/+19
2018-06-29	riscv: Fix SMP context switch support	Sebastian Huber	1	-2/+2
2018-06-29	riscv: Add SMP context switch support	Sebastian Huber	1	-0/+47
2018-06-29	riscv: Add floating-point support	Sebastian Huber	8	-50/+538
2018-06-29	riscv: Fix global construction	Sebastian Huber	1	-4/+5
2018-06-29	riscv: Add TLS support	Sebastian Huber	2	-0/+9
2018-06-29	riscv: Remove dead code	Sebastian Huber	1	-41/+1
2018-06-29	riscv: Optimize context switch and interrupts	Sebastian Huber	6	-174/+255
2018-06-29	riscv: Fix _CPU_Context_Initialize() prototype	Sebastian Huber	2	-12/+12
2018-06-29	riscv: Fix interrupt save/restore	Sebastian Huber	1	-1/+1
2018-06-29	riscv: Implement _CPU_Context_validate()	Sebastian Huber	2	-160/+168
2018-06-29	riscv: Make some CPU port defines visible to asm	Sebastian Huber	2	-37/+49
2018-06-29	riscv: Implement _CPU_Context_volatile_clobber()	Sebastian Huber	2	-16/+16
2018-06-29	riscv: Remove mstatus from thread context	Sebastian Huber	4	-27/+14
2018-06-29	riscv: Remove x8 initialization	Sebastian Huber	1	-2/+0
2018-06-29	riscv: Properly align the thread stack	Sebastian Huber	1	-3/+7
2018-06-29	riscv: Do not clear thread context	Sebastian Huber	1	-5/+2
2018-06-29	riscv: Fix CPU_STACK_ALIGNMENT	Sebastian Huber	1	-1/+2
2018-06-29	riscv: Remove RISCV_GCC_RED_ZONE_SIZE	Sebastian Huber	2	-5/+1
2018-06-29	riscv: Enable interrupts during dispatch after ISR	Sebastian Huber	5	-55/+91
2018-06-28	riscv: Add _CPU_Get_current_per_CPU_control()	Sebastian Huber	2	-0/+23
2018-06-28	riscv: Avoid namespace pollution	Sebastian Huber	3	-10/+4
2018-06-28	riscv: Optimize and fix interrupt disable/enable	Sebastian Huber	1	-15/+16