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2023-09-15score: Add _CPU_Get_TLS_thread_pointer()Sebastian Huber1-0/+7
2023-06-12score: Remove CPU port specific cpuatomic.hSebastian Huber1-31/+0
2023-05-20Update company nameSebastian Huber10-10/+10
2022-11-14cpukit: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman1-3/+22
2022-11-09riscv: Simplify _CPU_ISR_Set_level()Sebastian Huber1-15/+13
2022-11-09riscv: Remove superfluous init/fini functionsSebastian Huber1-12/+0
2022-10-14riscv: Move functions to avoid build issuesSebastian Huber1-0/+10
2022-10-14score: Add CPU_THREAD_LOCAL_STORAGE_VARIANTSebastian Huber2-1/+3
2022-09-20bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2-2/+2
2022-09-19Do not use RTEMS_INLINE_ROUTINESebastian Huber2-5/+5
2022-09-09score: Remove _CPU_Counter_difference()Sebastian Huber1-8/+0
2022-07-04score: Add _CPU_Use_thread_local_storage()Sebastian Huber1-0/+12
2022-06-24riscv: Include missing header fileSebastian Huber1-0/+2
2022-03-09SMP: Fix start multitasking for some targetsSebastian Huber2-0/+19
2022-02-25riscv: Use zicsr architecture extensionSebastian Huber5-11/+46
2021-09-21build: Remove old build systemSebastian Huber1-11/+0
2021-07-28score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2-2/+2
2021-07-28score: Remove processor event broadcast/receiveSebastian Huber1-10/+0
2021-06-24score: Remove _CPU_Initialize_vectors()Sebastian Huber1-2/+0
2021-05-18score: Add _CPU_Context_switch_no_return()Sebastian Huber2-0/+7
2020-10-10rtems: Improve RTEMS_NO_RETURN attributeSebastian Huber1-4/+2
2020-06-30score: Add CPU_USE_LIBC_INIT_FINI_ARRAYKinsey Moore1-0/+2
2019-11-29Regenerate headers.amSebastian Huber1-0/+1
2019-11-12riscv: preliminarily support for libdlHesham Almatary1-0/+144
2019-04-02doxygen: score: Add RISC-V CPU architecture groupAndreas Dachsberger4-1/+26
2019-03-26score: Rename ScoreCPU Doxygen groupSebastian Huber1-1/+1
2019-03-14Remove superfluous <rtems/system.h> includesSebastian Huber1-1/+0
2019-02-28Remove explicit file names from @fileSebastian Huber3-3/+3
2019-02-02riscv: Fix misaligned access in context validateSebastian Huber1-1/+1
2019-01-22riscv: add griscv bspJiri Gaisler1-4/+1
2019-01-22grlib: use cpu-independent routines for uncached accessJiri Gaisler3-0/+83
2019-01-09riscv: Enable robust thread dispatchSebastian Huber1-0/+3
2018-10-10build: Include header.am in cpukit/Makefile.amSebastian Huber2-14/+7
2018-10-10build: Merge score/cpu/*/Makefile.amSebastian Huber1-12/+0
2018-10-09build: Remove specialized CPPFLAGSSebastian Huber1-1/+0
2018-10-05score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber1-1/+0
2018-08-02score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber1-2/+0
2018-08-02riscv: Fix CPU_ALIGNMENTSebastian Huber1-1/+3
2018-07-27riscv: Rework CPU counter supportSebastian Huber4-5/+91
2018-07-25riscv: Add CLINT and PLIC supportSebastian Huber1-5/+45
2018-07-25riscv: Use wfi instruction for idle taskSebastian Huber2-12/+3
2018-07-25riscv: Rework exception handlingSebastian Huber6-144/+54
2018-07-25riscv: New CPU_Exception_frameSebastian Huber4-64/+203
2018-07-25riscv: Add exception codesSebastian Huber1-0/+39
2018-07-23score: Add _CPU_Instruction_illegal()Sebastian Huber1-0/+5
2018-07-20score: Add _CPU_Instruction_no_operation()Sebastian Huber1-0/+5
2018-07-20score: Move context validation declarationsSebastian Huber2-4/+4
2018-07-20score: Remove obsolete CPU port definesSebastian Huber1-4/+0
2018-07-06riscv: Add LADDR assembler defineSebastian Huber2-2/+12
2018-07-06riscv: Implement CPU counterSebastian Huber2-2/+16