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Add _CPU_Get_TLS_thread_pointer() to get the thread pointer which is
used to get the address of thread-local storage objects associated with
a thread.
Update #4920.
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All CPU ports used the same <rtems/score/cpustdatomic.h> header file to
provide the atomic operations. Remove the header file indirection.
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
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Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt
level allowed to set is 0 (interrupts enabled). This constraint is enforced by
the API level functions which return an error status for other interrupt
levels.
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The _RISCV_Map_cpu_index_to_hardid() and _RISCV_Map_hardid_to_cpu_index()
functions must be available to all riscv BSPs.
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Update #3835.
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The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
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Directly use "static inline" which is available in C99 and later. This brings
the RTEMS implementation closer to standard C.
Close #3935.
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All CPU ports used the same _CPU_Counter_difference() implementation. Remove
this CPU port interface and mandate a monotonically increasing CPU counter.
Close #3456.
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At some point during system initialization, the idle threads are created.
Afterwards, the boot processor basically executes within the context of an idle
thread with thread dispatching disabled. On some architectures, the
thread-local storage area of the associated thread must be set in dedicated
processor registers. Add the new CPU port function to do this:
void _CPU_Use_thread_local_storage( const Context_Control *context )
Close #4672.
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The previous SMP multitasking start assumed that the initial heir thread of a
processor starts execution in _Thread_Handler(). The _Thread_Handler() sets
the interrupt state explicitly by _ISR_Set_level() before it calls the thread
entry. Under certain timing conditions, processors may perform an initial
context switch to a thread which already executes its thread body (see
smptests/smpstart01). In this case, interrupts are disabled after the context
switch on targets which do not save/restore the interrupt state during a
context switch (aarch64, arm, and riscv).
Close #4627.
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This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
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Close #3250.
Close #4081.
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Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().
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Remove _CPU_SMP_Processor_event_broadcast() and
_CPU_SMP_Processor_event_receive(). These functions are hard to use since they
are subject to the lost wake up problem.
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This CPU port macro was not used. Since the _ISR_Vector_table[] is statically
allocated, CPU ports could initialize this table in _CPU_Initialize() if
necessary. Remove _CPU_Initialize_vectors() to simplify the CPU port
interface.
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The __builtin_unreachable() cannot be used with current GCC versions to
tell the compiler that a function does not return to the caller, see:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151
Add a no return variant of _CPU_Context_switch() to avoid generation of
dead code in _Thread_Start_multitasking() if RTEMS was built with SMP
support enabled.
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Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors
like this:
error: no return statement in function returning non-void [-Werror=return-type]
Use C11 and C++11 standard means to declare a no-return function.
Close #4122.
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This introduces the CPU_USE_LIBC_INIT_FINI_ARRAY define for use by CPU
ports to determine which global constructor and destructor methods are
used instead of placing architecture defines where they shouldn't be.
Close #4018
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Support for targets compiled with -fno-pic and -mno-relax
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Update #3706.
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Update #3706.
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This makes the @file documentation independent of the actual file name.
Update #3707.
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Update #3678.
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Update #3678.
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It must be enabled, since the context switch code does not save/restore
the interrupt status.
Update #3433.
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Include all cpukit/*/header.am files in cpukit/Makefile.am. This gets
rid of all subtree Makefile.am and the sudirs hack.
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Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary
conditional compilation.
Close #3539.
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Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.
It seems that previously the condition
CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)
was true on all CPU ports. Now, we need an additional check.
Update #3482.
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Update #3433.
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Update #3433.
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The CLINT and PLIC need some per-processor state.
Update #3433.
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Update #3433.
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Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.
Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.
Update #3433.
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Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.
Update #3433.
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Update #3433.
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On some architectures/simulators it is difficult to provoke an
exception with misaligned or illegal data loads. Use an illegal
instruction instead.
Update #3433.
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This helps to reduce the use of architecture-specific defines throughout
the code base.
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The context validation support functions _CPU_Context_validate() and
_CPU_Context_volatile_clobber() are used only by one test program
(spcontext01). Move the function declarations to the CPU port
implementation header file.
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An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.
Update #3433.
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Update #3433.
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