summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu/riscv/riscv-context-switch.S (unfollow)
Commit message (Expand)AuthorFilesLines
2023-05-20Update company nameSebastian Huber1-1/+1
2022-03-09SMP: Fix start multitasking for some targetsSebastian Huber1-0/+15
2022-02-25riscv: Use zicsr architecture extensionSebastian Huber1-0/+1
2021-05-18score: Add _CPU_Context_switch_no_return()Sebastian Huber1-0/+2
2018-07-05riscv: Clear reservationsSebastian Huber1-0/+2
2018-06-29riscv: Fix SMP context switch supportSebastian Huber1-2/+2
2018-06-29riscv: Add SMP context switch supportSebastian Huber1-0/+47
2018-06-29riscv: Add floating-point supportSebastian Huber1-9/+37
2018-06-29riscv: Add TLS supportSebastian Huber1-0/+1
2018-06-29riscv: Optimize context switch and interruptsSebastian Huber1-62/+29
2018-06-29riscv: Remove mstatus from thread contextSebastian Huber1-12/+0
2018-06-29riscv: Enable interrupts during dispatch after ISRSebastian Huber1-8/+15
2018-06-28riscv: Avoid namespace pollutionSebastian Huber1-0/+1
2018-06-27bsp/riscv: Load global pointerSebastian Huber1-2/+0
2018-06-27riscv: Format assembler filesSebastian Huber1-93/+93
2017-11-01cpukit: RISC-V - make riscv32 code work for riscv64 - v2Hesham Almatary1-3/+0
2017-10-28cpukit: Add basic riscv32 architecture port v3Hesham Almatary1-0/+139