Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | riscv: Fix fcsr initialization | Sebastian Huber | 2018-07-02 | 1 | -1/+10 |
* | riscv: Add TLS support | Sebastian Huber | 2018-06-29 | 1 | -0/+8 |
* | riscv: Optimize context switch and interrupts | Sebastian Huber | 2018-06-29 | 1 | -6/+2 |
* | riscv: Fix _CPU_Context_Initialize() prototype | Sebastian Huber | 2018-06-29 | 1 | -6/+6 |
* | riscv: Remove mstatus from thread context | Sebastian Huber | 2018-06-29 | 1 | -4/+0 |
* | riscv: Remove x8 initialization | Sebastian Huber | 2018-06-29 | 1 | -2/+0 |
* | riscv: Properly align the thread stack | Sebastian Huber | 2018-06-29 | 1 | -3/+7 |
* | riscv: Do not clear thread context | Sebastian Huber | 2018-06-29 | 1 | -5/+2 |
* | riscv: Remove RISCV_GCC_RED_ZONE_SIZE | Sebastian Huber | 2018-06-29 | 1 | -2/+1 |
* | cpukit: RISC-V - make riscv32 code work for riscv64 - v2 | Hesham Almatary | 2017-11-01 | 1 | -0/+67 |