rtems - RTEMS Kernel, file-systems, drivers, BSPs, samples, and testsuite.

	Commit message (Expand)	Author	Files	Lines
2023-09-15	score: Add _CPU_Get_TLS_thread_pointer()	Sebastian Huber	1	-0/+7
2023-06-12	score: Remove CPU port specific cpuatomic.h	Sebastian Huber	1	-31/+0
2023-05-20	Update company name	Sebastian Huber	2	-2/+2
2022-11-09	riscv: Simplify _CPU_ISR_Set_level()	Sebastian Huber	1	-15/+13
2022-10-14	riscv: Move functions to avoid build issues	Sebastian Huber	1	-0/+10
2022-10-14	score: Add CPU_THREAD_LOCAL_STORAGE_VARIANT	Sebastian Huber	1	-0/+2
2022-09-20	bsps/riscv: Add Microchip PolarFire SoC BSP variant	Padmarao Begari	2	-2/+2
2022-09-19	Do not use RTEMS_INLINE_ROUTINE	Sebastian Huber	2	-5/+5
2022-09-09	score: Remove _CPU_Counter_difference()	Sebastian Huber	1	-8/+0
2022-07-04	score: Add _CPU_Use_thread_local_storage()	Sebastian Huber	1	-0/+12
2022-03-09	SMP: Fix start multitasking for some targets	Sebastian Huber	1	-0/+4
2022-02-25	riscv: Use zicsr architecture extension	Sebastian Huber	3	-11/+44
2021-07-28	score: Canonicalize _CPU_Fatal_halt()	Sebastian Huber	2	-2/+2
2021-07-28	score: Remove processor event broadcast/receive	Sebastian Huber	1	-10/+0
2021-06-24	score: Remove _CPU_Initialize_vectors()	Sebastian Huber	1	-2/+0
2021-05-18	score: Add _CPU_Context_switch_no_return()	Sebastian Huber	1	-0/+5
2020-10-10	rtems: Improve RTEMS_NO_RETURN attribute	Sebastian Huber	1	-4/+2
2020-06-30	score: Add CPU_USE_LIBC_INIT_FINI_ARRAY	Kinsey Moore	1	-0/+2
2019-04-02	doxygen: score: Add RISC-V CPU architecture group	Andreas Dachsberger	3	-0/+25
2019-02-28	Remove explicit file names from @file	Sebastian Huber	3	-3/+3
2019-01-22	riscv: add griscv bsp	Jiri Gaisler	1	-4/+1
2019-01-09	riscv: Enable robust thread dispatch	Sebastian Huber	1	-0/+3
2018-10-05	score: Remove CPU_PROVIDES_IDLE_THREAD_BODY	Sebastian Huber	1	-1/+0
2018-08-02	score: Remove CPU_PARTITION_ALIGNMENT	Sebastian Huber	1	-2/+0
2018-08-02	riscv: Fix CPU_ALIGNMENT	Sebastian Huber	1	-1/+3
2018-07-27	riscv: Rework CPU counter support	Sebastian Huber	2	-5/+41
2018-07-25	riscv: Add CLINT and PLIC support	Sebastian Huber	1	-5/+45
2018-07-25	riscv: Use wfi instruction for idle task	Sebastian Huber	1	-10/+0
2018-07-25	riscv: Rework exception handling	Sebastian Huber	2	-30/+7
2018-07-25	riscv: New CPU_Exception_frame	Sebastian Huber	2	-55/+121
2018-07-25	riscv: Add exception codes	Sebastian Huber	1	-0/+39
2018-07-23	score: Add _CPU_Instruction_illegal()	Sebastian Huber	1	-0/+5
2018-07-20	score: Add _CPU_Instruction_no_operation()	Sebastian Huber	1	-0/+5
2018-07-20	score: Move context validation declarations	Sebastian Huber	2	-4/+4
2018-07-20	score: Remove obsolete CPU port defines	Sebastian Huber	1	-4/+0
2018-07-06	riscv: Add LADDR assembler define	Sebastian Huber	1	-1/+11
2018-07-06	riscv: Implement CPU counter	Sebastian Huber	1	-1/+16
2018-07-05	riscv: Clear reservations	Sebastian Huber	3	-6/+21
2018-07-02	riscv: Fix fcsr initialization	Sebastian Huber	1	-0/+9
2018-06-29	riscv: Add floating-point support	Sebastian Huber	3	-40/+184
2018-06-29	riscv: Remove dead code	Sebastian Huber	1	-41/+1
2018-06-29	riscv: Optimize context switch and interrupts	Sebastian Huber	2	-17/+123
2018-06-29	riscv: Fix _CPU_Context_Initialize() prototype	Sebastian Huber	1	-6/+6
2018-06-29	riscv: Implement _CPU_Context_validate()	Sebastian Huber	1	-6/+1
2018-06-29	riscv: Make some CPU port defines visible to asm	Sebastian Huber	2	-37/+49
2018-06-29	riscv: Implement _CPU_Context_volatile_clobber()	Sebastian Huber	1	-4/+1
2018-06-29	riscv: Remove mstatus from thread context	Sebastian Huber	2	-11/+14
2018-06-29	riscv: Fix CPU_STACK_ALIGNMENT	Sebastian Huber	1	-1/+2
2018-06-29	riscv: Remove RISCV_GCC_RED_ZONE_SIZE	Sebastian Huber	1	-3/+0
2018-06-29	riscv: Enable interrupts during dispatch after ISR	Sebastian Huber	2	-0/+6