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* score/cpu: Add CPU_Per_CPU_controlSebastian Huber2013-08-091-0/+6
| | | | Add CPU port specific per-CPU control.
* update-all-architectures-to-new-atomic-implementationWeiY2013-07-171-6/+4
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* score: Add and use _Thread_Dispatch_is_enabled()Sebastian Huber2013-06-141-1/+1
| | | | | Delete _Thread_Dispatch_in_critical_section() and _Thread_Is_dispatching_enabled().
* score: Add CPU context validationSebastian Huber2013-05-104-0/+194
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* Revert bootstrap whitespace changes.Chris Johns2013-05-101-0/+1
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* Using the generic atomic ops to implement UP mode atomic for all ↵WeiY2013-05-013-0/+44
| | | | architectures. SMP atomic port will be later.
* nios2: DocumentationSebastian Huber2013-03-111-13/+2
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* nios2: Use NIOS2_CTLREG_INDEX_STATUSJeffrey O. Hill2013-03-111-1/+2
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* nios2: Set CPU_ISR_PASSES_FRAME_POINTER to FALSEJeffrey O. Hill2013-03-112-23/+3
| | | | | This reflects what is currently happening. Define CPU_Interrupt_frame type to void to prevent accidental usage.
* nios2: Add _Nios2_Count_leading_zeros()Jeffrey O. Hill2013-03-113-0/+75
| | | | | Add _Nios2_Count_trailing_zeros(). They are currently more efficient than the corresponding GCC builtins.
* nios2: Rename fileJeffrey O. Hill2013-03-112-1/+1
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* RTEMS: Delete ChangeLog files.Gedare Bloom2013-03-081-259/+0
| | | | | | | | | This commit deletes all RTEMS ChangeLog files. These files have been abandoned since converting to git version control. The historical data may be recovered by checking out any commit before this one. Most of the contents of these ChangeLog files can also be found in the git log. Two external ChangeLog files, ChangeLog.slac and ChangeLog.zlib, remain.
* NIOS2: Fix register restore sequence in epilogueSebastian Huber2013-01-141-3/+3
| | | | | This fix is critical. The previous implementation leads to system corruption.
* score: Doxygen Clean Up Task #17Alex Ivanov2013-01-093-18/+30
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* score: Doxygen Clean Up Task #16Alex Ivanov2013-01-083-17/+24
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* score misc: Clean up Doxygen #13 (GCI 2012)Mathew Kallada2012-12-0210-6/+76
| | | | | | | This patch is a task from GCI 2012 which improves the Doxygen comments in the RTEMS source. http://www.google-melange.com/gci/task/view/google/gci2012/8013205
* score: Add CPU_Exception_frameSebastian Huber2012-11-273-0/+27
| | | | | | | | | | | | | | | | | | | | | Add CPU port type CPU_Exception_frame and function _CPU_Exception_frame_print(). The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh, sparc64, and v850 use an empty default implementation of _CPU_Exception_frame_print(). Add rtems_exception_frame and rtems_exception_frame_print(). Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal() with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc, and sparc for unexpected exceptions. Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the BSP_PRINT_EXCEPTION_CONTEXT define used in the default bsp_fatal_extension(). Add test sptests/spfatal26.
* score: PR1607: Add and use CPU_SIZEOF_POINTERSebastian Huber2012-11-221-0/+2
| | | | | | | | | | | | | | | | | Add and use new CPU port define CPU_SIZEOF_POINTER. It must be an integer literal that can be used by the assembler. This value will be used to calculate offsets of structure members. These offsets will be used in assembler code. The size of a pointer is part of the application binary interface (ABI) and thus independent of the actual programming language. The compiler will provide defines to determine the current ABI. We use these defines to select the appropriate CPU_SIZEOF_POINTER value. Static assertions in the new file "cpukit/score/src/percpuasm.c" will ensure that the value of CPU_SIZEOF_POINTER is consistent with the current compiler settings. Also the offset values used by assembler code are verfied.
* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-1126-54/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* Revert: Remove CVS IdsJoel Sherrill2012-05-071-0/+4
| | | | | See http://www.rtems.org/pipermail/rtems-devel/2012-May/001006.html for details.
* Remove CVS-Ids.Ralf Corsépius2012-05-041-4/+0
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* nios2: New functionsSebastian Huber2012-04-112-0/+49
| | | | | | Add o _Nios2_MPU_Get_region_descriptor(), and o _Nios2_MPU_Set_region_registers().
* nios2: API changeSebastian Huber2012-04-113-4/+4
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* NIOS2: Add MPU support functionsSebastian Huber2012-03-304-21/+165
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* NIOS2: Fix outermost interrupt checkSebastian Huber2012-03-301-1/+4
| | | | | This fix is critical. The previous implementation leads to system corruption.
* Remove all .cvsignore files.Joel Sherrill2012-02-011-2/+0
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* 2011-10-21 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-10-218-2/+409
| | | | | | | | * nios2-mpu-configuration.c, nios2-mpu-descriptor.c, nios2-mpu-disable-protected.c, nios2-mpu-reset.c: New files. * Makefile.am: Reflect changes above. * rtems/score/nios2-utility.h, nios2-context-initialize.c: Added support for the memory protection unit (MPU).
* 2011-09-30 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-302-4/+7
| | | | | * nios2-context-switch.S: Use small-data area access for _Per_CPU_Information fields.
* 2011-09-27 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-272-0/+7
| | | | | PR 1914/cpukit * rtems/score/cpu.h: Select timestamp implementation.
* 2011-09-16 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-168-4/+401
| | | | | | | | * nios2-eic-il-low-level.S, nios2-eic-rsie-low-level.S: New files. * Makefile.am: Reflect changes above. * rtems/score/cpu.h, rtems/score/nios2-utility.h, nios2-thread-dispatch-disabled.c, nios2-context-switch.S: Added support for thread stack protection via the MPU.
* 2011-09-14 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-142-4/+6
| | | | | * rtems/score/cpu.h: Request cache alignment and small data area in CPU_STRUCTURE_ALIGNMENT.
* 2011-09-09 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-092-2/+6
| | | | | * nios2-thread-dispatch-disabled.c: Use offsetof() instead of RTEMS_offsetof().
* 2011-09-02 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-024-5/+10
| | | | | * rtems/score/nios2-utility.h, nios2-isr-set-level.c, nios2-isr-get-level.c: Renamed functions.
* 2011-09-02 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-022-12/+9
| | | | | * rtems/score/nios2-utility.h: Use the same values for defines used by Altera HAL.
* 2011-09-02 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-024-13/+48
| | | | | | | * rtems/score/nios2-utility.h: Avoid redefines with Altera HAL. Declare _Nios2_ISR_Set_level(). * nios2-context-initialize.c: Use _Nios2_ISR_Set_level(). * nios2-isr-set-level.c: Define _Nios2_ISR_Set_level().
* 2011-09-01 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-0119-304/+908
| | | | | | | | | | | | | | | | * cpu.c, cpu_asm.S: Removed files. * nios2-context-initialize.c, nios2-context-switch.S, nios2-fatal-halt.c, nios2-initialize-vectors.c, nios2-initialize.c, nios2-isr-get-level.c, nios2-isr-install-raw-handler.c, nios2-isr-install-vector.c, nios2-isr-is-in-progress.c, nios2-isr-set-level.c, nios2-thread-dispatch-disabled.c, rtems/score/nios2-utility.h: New files. * Makefile.am, preinstall.am: Reflect changes above. * irq.c: Update due to API changes. * rtems/score/cpu.h: New functions _CPU_Initialize_vectors(), _CPU_ISR_Set_level(), and _CPU_Fatal_halt() (instead of macros). Support for external interrupt controller (EIC). Documentation changes.
* 2011-08-18 Chris Johns <chrisj@rtems.org>Chris Johns2011-08-186-52/+119
| | | | | | | | | | | | * cpu.c: Fix the ISR get level for the IIC. Make _CPU_Context_Initialize a function rather than inlined. * cpu_asm.S: Do not enable interrupt on return, rather resume the state on entry to the ISR. * irq.c, nios2/nios2-iic-low-level.S: Change the ISR handler so the ipending decoding is in C and within the interrupt context. This is usable with the Altera HAL directly. * rtems/score/cpu.h: Add ienable and ipending interfaces. Add some comments. Remove _CPU_Context_Initialize.
* 2011-08-14 Chris Johns <chrisj@rtems.org>Chris Johns2011-08-143-7/+83
| | | | | | * rtems/score/cpu.h: Clear the vector table for simple vectored interrupts. * irq.c: Add support for using the IIC with the Altera HAL.
* 2011-08-10 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-08-102-1157/+143
| | | | | | * rtems/score/cpu.h: Removed superfluous comments. Format. Include by assembler support. Removed superfluous floating-point support. Stack alignment is now 4.
* 2011-08-10 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-08-103-66/+5
| | | | * rtems/score/cpu.h, cpu.c: Removed superfluous functions.
* 2011-08-09 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-08-094-300/+331
| | | | | | * nios2-iic-low-level.S: New file. * cpu_asm.S: Moved low-level interrupt handling into new file. * Makefile.am: Reflect change from above.
* 2011-08-09 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-08-093-31/+33
| | | | | | * cpu_asm.S, rtems/score/cpu.h: There is no need to save the global pointer (gp) in the thread register context since it is a system wide constant and set-up with the C runtime environment.
* 2011-07-24 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2011-07-242-10/+10
| | | | | * cpu.c: Remove /*PAGE markers which were interpreted by a long dead print script.
* 2011-05-18 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-05-182-2/+8
| | | | * Makefile.am: Reformat.
* 2011-04-21 Jennifer Averett <Jennifer.Averett@OARcorp.comJennifer Averett2011-04-211-3/+3
| | | | | | | | | | | | | PR 1777/cpukit * libcsupport/src/malloc_deferred.c, libcsupport/src/realloc.c, score/Makefile.am, score/cpu/lm32/irq.c, score/cpu/nios2/irq.c, score/include/rtems/score/coremutex.h, score/include/rtems/score/thread.h, score/inline/rtems/score/thread.inl, score/src/heapfree.c, score/src/pheapwalk.c, score/src/smp.c, score/src/threaddispatch.c: Consolidated access to _Thread_Dispatch_disable_level. * score/src/threaddisabledispatch.c, score/src/threadenabledispatch.c: New files.
* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-112-1/+6
| | | | | * irq.c: Use "__asm__" instead of "asm" for improved c99-compliance.
* 2010-10-21 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-10-212-1/+7
| | | | | | * rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to _CPU_Context_restore() because it does not return. Telling GCC this avoids generation of dead code.
* 2010-07-30 Gedare Bloom <giddyup44@yahoo.com>Joel Sherrill2010-07-302-1/+7
| | | | | | PR 1599/cpukit * irq.c: Rename _Context_Switch_necessary to _Thread_Dispatch_necessary to more properly reflect the intent.
* 2010-07-29 Gedare Bloom <giddyup44@yahoo.com>Joel Sherrill2010-07-293-2/+13
| | | | | | | | | | | PR 1635/cpukit * rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
* 2010-07-16 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2010-07-163-12/+8
| | | | | * rtems/score/cpu.h: Include <rtems/score/types.h> first. * rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
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