diff options
author | Chris Johns <chrisj@rtems.org> | 2011-08-14 07:38:14 +0000 |
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committer | Chris Johns <chrisj@rtems.org> | 2011-08-14 07:38:14 +0000 |
commit | 3848df4d72412f448350b2df1cada9c5e3308afd (patch) | |
tree | 15af48b44b4be215fad88367580ce69074eb29f8 /cpukit/score/cpu/nios2 | |
parent | 2011-08-10 Sebastian Huber <sebastian.huber@embedded-brains.de> (diff) | |
download | rtems-3848df4d72412f448350b2df1cada9c5e3308afd.tar.bz2 |
2011-08-14 Chris Johns <chrisj@rtems.org>
* rtems/score/cpu.h: Clear the vector table for simple vectored
interrupts.
* irq.c: Add support for using the IIC with the Altera HAL.
Diffstat (limited to 'cpukit/score/cpu/nios2')
-rw-r--r-- | cpukit/score/cpu/nios2/ChangeLog | 6 | ||||
-rw-r--r-- | cpukit/score/cpu/nios2/irq.c | 79 | ||||
-rw-r--r-- | cpukit/score/cpu/nios2/rtems/score/cpu.h | 5 |
3 files changed, 83 insertions, 7 deletions
diff --git a/cpukit/score/cpu/nios2/ChangeLog b/cpukit/score/cpu/nios2/ChangeLog index dbf96749d0..94ca8ec29d 100644 --- a/cpukit/score/cpu/nios2/ChangeLog +++ b/cpukit/score/cpu/nios2/ChangeLog @@ -1,3 +1,9 @@ +2011-08-14 Chris Johns <chrisj@rtems.org> + + * rtems/score/cpu.h: Clear the vector table for simple vectored + interrupts. + * irq.c: Add support for using the IIC with the Altera HAL. + 2011-08-10 Sebastian Huber <sebastian.huber@embedded-brains.de> * rtems/score/cpu.h: Removed superfluous comments. Format. Include diff --git a/cpukit/score/cpu/nios2/irq.c b/cpukit/score/cpu/nios2/irq.c index 5687f853c4..abfbeca0fb 100644 --- a/cpukit/score/cpu/nios2/irq.c +++ b/cpukit/score/cpu/nios2/irq.c @@ -34,7 +34,73 @@ register unsigned long *stack_ptr __asm__ ("sp"); +RTEMS_INLINE_ROUTINE void +__Dipatch_interrupt_vector(uint32_t vector, proc_ptr pp) +{ + if ( _ISR_Vector_table[ vector] ) + { + (*_ISR_Vector_table[ vector ])(vector, pp); + }; +} + +#if (RTEMS_NIOS_USE_ALT_HAL == TRUE) + +#include <bsp/alt/nios2.h> + +RTEMS_INLINE_ROUTINE void __IIC_Handler(void) +{ + uint32_t active; + uint32_t mask; + uint32_t vector; + + /* + * Obtain from the interrupt controller a bit list of pending interrupts, + * and then process the highest priority interrupt. This process loops, + * loading the active interrupt list on each pass until alt_irq_pending() + * return zero. + * + * The maximum interrupt latency for the highest priority interrupt is + * reduced by finding out which interrupts are pending as late as possible. + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + NIOS2_READ_IPENDING (active); + + while (active) + { + vector = 0; + mask = 1; + + /* + * Test each bit in turn looking for an active interrupt. Once one is + * found, the interrupt handler asigned by a call to alt_irq_register() is + * called to clear the interrupt condition. + */ + + while (active) + { + if (active & mask) + { + __Dipatch_interrupt_vector(vector, NULL); + active &= ~mask; + } + mask <<= 1; + ++vector; + }; + + NIOS2_READ_IPENDING (active); + } + +} +#endif + +#if (RTEMS_NIOS_USE_ALT_HAL == TRUE) +void __ISR_Handler(void) +#else void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr) +#endif { register uint32_t level; @@ -52,11 +118,12 @@ void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr) _Thread_Dispatch_increment_disable_level(); - if ( _ISR_Vector_table[ vector] ) - { - (*_ISR_Vector_table[ vector ])(vector, ifr); - }; - +#if (RTEMS_NIOS_USE_ALT_HAL == TRUE) + __IIC_Handler(); +#else + __Dipatch_interrupt_vector(vector, ifr); +#endif + /* Make sure that interrupts are disabled again */ _CPU_ISR_Disable( level ); @@ -87,5 +154,3 @@ void __Exception_Handler(CPU_Exception_frame *efr) { _CPU_Fatal_halt(0xECC0); } - - diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h index 4ace4c4f3a..61a1b421b8 100644 --- a/cpukit/score/cpu/nios2/rtems/score/cpu.h +++ b/cpukit/score/cpu/nios2/rtems/score/cpu.h @@ -182,7 +182,12 @@ typedef struct { uint32_t ipending; } CPU_Exception_frame; +#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE) +#define _CPU_Initialize_vectors() \ + memset(_ISR_Vector_table, 0, sizeof(ISR_Handler_entry) * ISR_NUMBER_OF_VECTORS) +#else #define _CPU_Initialize_vectors() +#endif #define _CPU_ISR_Disable( _isr_cookie ) \ do { \ |