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* 2006-03-17 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2006-03-171-1/+5
| | | | * cpu.c (_CPU_Initialize): Add fpu initialization.
* PR 730Greg Menke2004-12-061-8/+10
| | | | | * cpu_asm.S: Collected PR 601 changes for commit to cvshead for rtems-4.7
* 2004-04-14 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-04-141-5/+0
| | | | | | PR 605/bsps * cpu.c: Remove further c++ style comments having been missed in previous patch. Remove printf's entirely.
* 2004-04-09 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2004-04-091-2/+2
| | | | | PR 605/bsps * cpu.c: Do not use C++ style comments.
* 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-03-301-4/+4
| | | | * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-041-1/+1
| | | | | * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h: URL for license changed.
* 2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-081-0/+12
| | | | | | | | | | | | * cpu_asm.S: Added support for the debug exception vector, cleaned up the exception processing & exception return stuff. Re-added EPC in the task context structure so the gdb stub will know where a thread is executing. Should've left it there in the first place... * idtcpu.h: Added support for the debug exception vector. * cpu.c: Added ___exceptionTaskStack to hold a pointer to the stack frame in an interrupt so context switch code can get the userspace EPC when scheduling. * rtems/score/cpu.h: Re-added EPC to the task context.
* 2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-011-8/+23
| | | | | | | | | | | | | | | | * cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling. * idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions. * iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores.
* 2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-02-011-18/+33
| | | | | | | | | * cpu.c: Enhancements and fixes for modifying the SR when changing the interrupt level. * cpu_asm.S: Fixed handling of FP enable bit so it is properly managed on a per-task basis, improved handling of interrupt levels, and made deferred FP contexts work on the MIPS. * rtems/score/cpu.h: Modified to support above changes.
* 2001-07-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-07-031-1/+1
| | | | * cpu.c: Fixed typo.
* 2001-03-14 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-03-141-41/+21
| | | | | | * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments.
* 2001-03-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-03-141-5/+43
| | | | | | | * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h: Merged MIPS1 and MIPS3 code reducing the number of lines of assembly. Also reimplemented some assembly routines in C further reducing the amount of assembly and increasing maintainability.
* 2000-12-19 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-191-11/+0
| | | | | * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here because it has not been allocated yet.
* 2000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-131-2/+0
| | | | | | | | * cpu.c: Removed duplicate declaration for _ISR_Vector_table. * cpu_asm.S: Removed assembly language to vector ISR handler on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No longer a constant -- get the real value from libcpu.
* 2000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-131-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cpu_asm.h: Removed. * Makefile.am: Remove cpu_asm.h. * rtems/score/mips64orion.h: Renamed mips.h. * rtems/score/mips.h: New file, formerly mips64orion.h. Header rewritten. (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, mips_disable_in_interrupt_mask): New macros. * rtems/score/Makefile.am: Reflect renaming mips64orion.h. * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the few defines that were in <cpu_asm.h>. * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. MIPS ISA 3 is still in assembly for now. (_CPU_Thread_Idle_body): Rewrote in C. * cpu_asm.S: Rewrote file header. (FRAME,ENDFRAME) now in asm.h. (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and leaves other bits in SR alone on task switch. (mips_enable_interrupts,mips_disable_interrupts, mips_enable_global_interrupts,mips_disable_global_interrupts, disable_int, enable_int): Removed. (mips_get_sr): Rewritten as C macro. (_CPU_Thread_Idle_body): Rewritten in C. (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and placed in libcpu. (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved to libcpu/mips/shared/interrupts. (general): Cleaned up comment blocks and #if 0 areas. * idtcpu.h: Made ifdef report an error. * iregdef.h: Removed warning. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable number defined by libcpu. (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines to access SR. (_CPU_ISR_Set_level): Rewritten as macro for ISA I. (_CPU_Context_Initialize): Honor ISR level in task initialization. (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
* 2000-10-24 Alan Cudmore <alanc@linuxstart.com> andJoel Sherrill2000-10-241-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Joel Sherrill <joel@OARcorp.com> * This is a major reworking of the mips64orion port to use gcc predefines as much as possible and a big push to multilib the mips port. The mips64orion port was copied/renamed to mips to be more like other GNU tools. Alan did most of the technical work of determining how to map old macro names used by the mips64orion port to standard compiler macro definitions. Joel did the merge with CVS magic to keep individual file history and did the BSP modifications. Details follow: * Makefile.am: idtmon.h in mips64orion port not present. * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. * cpu.c: Comments added. * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. First attempt at exception/interrupt processing for ISA level 1 and minus any use of IDT/MON added. * idtcpu.h: Conditionals changed to use gcc predefines. * iregdef.h: Ditto. * cpu_asm.h: No real change. Merger required commit. * rtems/Makefile.am: Ditto. * rtems/score/Makefile.am: Ditto. * rtems/score/cpu.h: Change MIPS64ORION to MIPS. * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
* Removed no cpu references.Joel Sherrill2000-07-111-1/+1
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* Updated copyright notice.Joel Sherrill1999-11-171-2/+1
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* updated copyright to 1998Joel Sherrill1998-02-171-1/+1
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* Fixed typo in the pointer to the license terms.Joel Sherrill1997-10-081-2/+2
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* headers updated to reflect new style copyright notice as partJoel Sherrill1997-04-221-5/+5
| | | | of switching to the modified GNU GPL.
* commented out sccs_id to eliminate warning.Joel Sherrill1997-04-071-3/+6
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* added $Id$ to file headersJoel Sherrill1996-09-111-1/+1
| | | | cpu.h: added prototype for _CPU_ISR_Get_level()
* new file for MIPS port by Craig Lebakken (lebakken@minn.net) andJoel Sherrill1996-09-061-0/+216
Derrick Ostertag (ostertag@transition.com).
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