| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
Update #3706.
|
|
|
|
| |
Update #3706.
|
|
|
|
| |
Update #3585.
|
|
|
|
|
|
|
|
|
| |
Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the
interrupts are always enabled during a context switch even after
interrupt processing (see #2751). Remove the CPSR from the context
control since it contains only volatile bits.
Close #2954.
|
|
|
|
| |
Update #2751.
|
|
|
|
| |
Update #2751.
|
|
|
|
|
|
|
|
|
|
|
| |
The stack pointer must be aligned on 8 byte boundary on ARM, so the size of
the exception frame must be a multiple of 8 bytes. Otherwise we might/will
get an alignment fault, when executing code in the data abort handler for
example.
Close #2318.
Signed-off-by: Daniel Krueger <daniel.krueger@systec-electronic.com>
|
|
|
|
|
| |
This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
|
|
|
|
|
|
|
|
|
|
| |
We must not alter the is executing indicator in
_CPU_Context_Initialize() since this would cause an invalid state during
a self restart.
The is executing indicator must be valid at creation time since
otherwise _Thread_Kill_zombies() uses an undefined value for not started
threads. This could result in a system life lock.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
|
| |
|
|
|
|
|
| |
Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.
|
| |
|
|
|
|
|
| |
The set of interrupt levels must be a continuous range of non-negative
integers starting at zero.
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* rtems/score/armv7m.h, armv7m-context-initialize.c,
armv7m-context-restore.c, armv7m-context-switch.c,
armv7m-exception-handler-get.c, armv7m-exception-handler-set.c,
armv7m-exception-priority-get.c, armv7m-exception-priority-set.c,
armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c,
armv7m-isr-level-get.c, armv7m-isr-level-set.c,
armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New
files.
* Makefile.am, preinstall.am: Reflect changes above.
* rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and
ARM_MULTILIB_ARCH_V7M.
* rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S,
arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S:
Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE. Use
ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
|
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
|
| |
|
|
|
|
|
| |
* arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S,
arm_exc_interrupt.S, cpu.c, cpu_asm.S: Add include of config.h
|
| |
|
| |
|
| |
|
|
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
comments.
|
| |
|
|
|
|
| |
* cpu.c: Remove extraneous spaces.
|
| |
|
| |
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h: Add void.
|
|
|
|
| |
* cpu.c: Add comment.
|
|
|
|
|
| |
* cpu.c: Add arm_cpu_mode so ARM BSP can overrid default value for
cpsr.
|
|
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
Table to Configuration Table. Eliminate CPU Table from all ports.
Delete references to CPU Table in all forms.
|
|
|
|
|
| |
* cpu.c, score/cpu.h: Fix headers. Remove extra inline definition.
* cpu_asm.S: Note origin of Thumb support.
|
|
|
|
| |
* cpu.c: Fix headers.
|
|
|
|
|
|
|
|
|
|
| |
* cpu.c, cpu_asm.S, score/cpu.h : add support for ARM<->THUMB veneer
thumb new dir to controll CPSR/SPRS in thumb mode
2007-05-09 Ray Xu <rayx.cn@gmail.com>
* cpu.c: move do_data_abort() to libbsp/arm/shared/abort/
implement a compact do_data_abort() in simple_abort.c
|
|
|
|
|
|
|
|
|
| |
* score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c,
score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c,
score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c,
score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c,
cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared
executive initialization.
|
|
|
|
|
| |
* cpu.c: move do_data_abort() to libbsp/arm/shared/abort/
implement a compact do_data_abort() in simple_abort.c
|
|
|
|
| |
* cpu.c: Remove warning.
|
|
|
|
| |
* cpu.c, cpu_asm.S: Fixed ARM Data Abort handling.
|
| |
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
|
|
|
|
|
| |
* asm.h, cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h,
rtems/score/cpu_asm.h, rtems/score/types.h: URL for license changed.
|
|
|
|
| |
* cpu.c: Removed warning.
|
|
|
|
| |
* cpu.c: Removed warnings.
|
|
|
|
|
|
|
|
|
| |
* cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h,
rtems/score/cpu_asm.h, rtems/score/types.h: ARM port works
well enough to run all sptests, tmtests, and ttcp.
In addition to general cleanup, there has been considerable
optimization to interrupt disable/enable, endian swapping,
and context switching.
|
|
|
|
|
|
|
|
|
|
|
| |
* rtems/score/cpu_asm.h: Enhanced to include register offsets.
* Makefile.am: Install rtems/score/cpu_asm.h.
* cpu.c: Significantly enhanced including the implementation of
_CPU_ISR_Get_level.
* cpu_asm.S: Improved behavior of context switch and interrupt
dispatching.
* rtems/score/arm.h: Improved the CPU model name determination.
* rtems/score/cpu.h: Improved interrupt disable/enable functions.
|
|
|
|
| |
* cpu.c: Include rtems/bspIo.h instead of bspIo.h.
|
|
|
|
|
| |
* cpu.c: Spacing issues.
* rtems/score/cpu.h: Removed warning by setting _level.
|
|
<valette@crf.canon.fr> and Emmanuel Raguet <raguet@crf.canon.fr>
of Canon CRF - Communication Dept. This port includes a
basic BSP that is sufficient to link hello world.
|