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* score: Add ARM CPU architecture groupSebastian Huber2019-03-261-1/+1
| | | | Update #3706.
* score: Rename ScoreCPU Doxygen groupSebastian Huber2019-03-261-1/+1
| | | | Update #3706.
* arm: Remove use of proc_ptrSebastian Huber2018-11-121-8/+8
| | | | Update #3585.
* arm: Optimize context switchSebastian Huber2017-03-281-24/+9
| | | | | | | | | Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the interrupts are always enabled during a context switch even after interrupt processing (see #2751). Remove the CPSR from the context control since it contains only volatile bits. Close #2954.
* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-021-0/+1
| | | | Update #2751.
* arm: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-181-1/+9
| | | | Update #2751.
* arm: Align ARM exception frame to 8 bytesDaniel Krueger2015-04-101-0/+5
| | | | | | | | | | | The stack pointer must be aligned on 8 byte boundary on ARM, so the size of the exception frame must be a multiple of 8 bytes. Otherwise we might/will get an alignment fault, when executing code in the data abort handler for example. Close #2318. Signed-off-by: Daniel Krueger <daniel.krueger@systec-electronic.com>
* arm: Add support for FPv4-SP floating point unitSebastian Huber2014-08-121-1/+1
| | | | | This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
* score: Fix CPU context usage on SMPSebastian Huber2014-05-081-4/+0
| | | | | | | | | | We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
* score: Implement forced thread migrationSebastian Huber2014-05-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* Add thread-local storage (TLS) supportSebastian Huber2014-02-041-1/+19
| | | | | Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
* arm: Fix ISR level context initializationSebastian Huber2013-08-051-1/+2
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* arm: Fix CPU_MODES_INTERRUPT_MASKSebastian Huber2013-08-051-3/+5
| | | | | The set of interrupt levels must be a continuous range of non-negative integers starting at zero.
* arm: Support VFP-D32 and NeonSebastian Huber2013-05-101-0/+23
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* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2011-09-24 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-241-10/+9
| | | | | | | | | | | | | | | | | | * rtems/score/armv7m.h, armv7m-context-initialize.c, armv7m-context-restore.c, armv7m-context-switch.c, armv7m-exception-handler-get.c, armv7m-exception-handler-set.c, armv7m-exception-priority-get.c, armv7m-exception-priority-set.c, armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c, armv7m-isr-level-get.c, armv7m-isr-level-set.c, armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New files. * Makefile.am, preinstall.am: Reflect changes above. * rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M. * rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S: Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE. Use ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-111-2/+2
| | | | | * cpu.c, rtems/score/cpu.h: Use "__asm__" instead of "asm" for improved c99-compliance.
* add/adapt documentationThomas Doerfler2010-04-081-1/+3
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* 2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-03-271-0/+4
| | | | | * arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S, cpu.c, cpu_asm.S: Add include of config.h
* add support for lpc32xxThomas Doerfler2010-01-121-14/+14
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* Whitespace removal.Ralf Corsepius2009-12-041-2/+2
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* exception handler maintenanceThomas Doerfler2009-07-171-214/+69
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* 2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2009-02-111-6/+3
| | | | | | * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch to _CPU_Initialize. Clean up comments.
* Fix typo.Ralf Corsepius2008-12-071-1/+1
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* 2008-09-08 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2008-09-081-4/+4
| | | | * cpu.c: Remove extraneous spaces.
* Convert to "bool".Ralf Corsepius2008-09-051-1/+1
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* Add missing prototypes.Ralf Corsepius2008-08-191-3/+3
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* 2008-08-18 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-08-181-1/+1
| | | | * cpu.c, rtems/score/cpu.h: Add void.
* 2008-04-18 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-04-181-2/+7
| | | | * cpu.c: Add comment.
* 2008-04-17 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2008-04-171-1/+3
| | | | | * cpu.c: Add arm_cpu_mode so ARM BSP can overrid default value for cpsr.
* 2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-12-041-3/+0
| | | | | | * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU Table to Configuration Table. Eliminate CPU Table from all ports. Delete references to CPU Table in all forms.
* 2007-11-26 Ray Xu <rayx.cn@gmail.com>Joel Sherrill2007-11-261-0/+2
| | | | | * cpu.c, score/cpu.h: Fix headers. Remove extra inline definition. * cpu_asm.S: Note origin of Thumb support.
* 2007-11-06 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-11-061-0/+1
| | | | * cpu.c: Fix headers.
* 2007-11-03 Ray Xu <rayx.cn@gmail.com>Joel Sherrill2007-11-061-2/+43
| | | | | | | | | | * cpu.c, cpu_asm.S, score/cpu.h : add support for ARM<->THUMB veneer thumb new dir to controll CPSR/SPRS in thumb mode 2007-05-09 Ray Xu <rayx.cn@gmail.com> * cpu.c: move do_data_abort() to libbsp/arm/shared/abort/ implement a compact do_data_abort() in simple_abort.c
* 2007-05-22 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-05-221-1/+0
| | | | | | | | | * score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c, score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c, score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c, score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c, cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared executive initialization.
* 2007-05-09 Ray Xu <rayx@gmail.com>Joel Sherrill2007-05-151-150/+0
| | | | | * cpu.c: move do_data_abort() to libbsp/arm/shared/abort/ implement a compact do_data_abort() in simple_abort.c
* 2006-09-11 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2006-09-111-0/+2
| | | | * cpu.c: Remove warning.
* 2006-06-02 Jay Monkman <jtm@lopingdog.com>Jay Monkman2006-06-021-3/+51
| | | | * cpu.c, cpu_asm.S: Fixed ARM Data Abort handling.
* Remove stray white spaces.Ralf Corsepius2004-04-151-3/+0
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* 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-03-301-20/+20
| | | | * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-041-1/+1
| | | | | * asm.h, cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/types.h: URL for license changed.
* 2002-11-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-11-041-1/+1
| | | | * cpu.c: Removed warning.
* 2002-11-01 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-11-011-2/+1
| | | | * cpu.c: Removed warnings.
* 2002-07-30 Jay Monkman <jtm@smoothsmoothie.com>Joel Sherrill2002-07-301-59/+140
| | | | | | | | | * cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/types.h: ARM port works well enough to run all sptests, tmtests, and ttcp. In addition to general cleanup, there has been considerable optimization to interrupt disable/enable, endian swapping, and context switching.
* 2002-07-17 Jay Monkman <jtm@smoothsmoothie.com>Joel Sherrill2002-07-171-57/+130
| | | | | | | | | | | * rtems/score/cpu_asm.h: Enhanced to include register offsets. * Makefile.am: Install rtems/score/cpu_asm.h. * cpu.c: Significantly enhanced including the implementation of _CPU_ISR_Get_level. * cpu_asm.S: Improved behavior of context switch and interrupt dispatching. * rtems/score/arm.h: Improved the CPU model name determination. * rtems/score/cpu.h: Improved interrupt disable/enable functions.
* 2002-01-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2002-01-061-1/+1
| | | | * cpu.c: Include rtems/bspIo.h instead of bspIo.h.
* 2000-08-28 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2000-08-291-4/+5
| | | | | * cpu.c: Spacing issues. * rtems/score/cpu.h: Removed warning by setting _level.
* Port of RTEMS to the ARM processor family by Eric ValetteJoel Sherrill2000-07-271-0/+169
<valette@crf.canon.fr> and Emmanuel Raguet <raguet@crf.canon.fr> of Canon CRF - Communication Dept. This port includes a basic BSP that is sufficient to link hello world.
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