| Commit message (Collapse) | Author | Age | Files | Lines |
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- Add resize to the allocator interface
- Rework the trampoline variables in the obj struct
to make better sense of what is happening
Closes #4944
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This change requires an rtems-tools update for symbol generation.
Working architectures:
- aarch64
- arm
- powerpc
- sparc
No newlib TLS support but checked:
- i386
- m69k
Updates #4920
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Updates #3969
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- Load symbols before allocation.
- Parse reloc records and place any reloc recs in a cache to use
while the allocator is locked.
- Relocate symbols after section allocation.
- Split section loading into allocation/locating and loading.
- Update all arch back-ends with a new reloc interface to control
tramp handling.
- Add `-a` and `-t` to the object list shell command.
Closes #3741
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- Add support for architecure sections that can be handled by the
architecture back end.
- Add trampoline/fixup support for PowerPC. This means the PowerPC
now supports large memory loading of applications.
- Add a bit allocator to manage small block based regions of memory.
- Add small data (sdata/sbss) support for the PowerPC. The support
makes the linker allocated small data region of memory a global
resource available to libdl loaded object files.
Updates #3687
Updates #3685
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- Trampolines or fixups for veneers provide long jump support
for instruciton sets that implement short relative address
branches. The linker provides trampolines when creating a
static image. This patch adds trampoline support to libdl
and the ARM architecture.
- The dl09 test requires enough memory so modules are outside
the relative branch instruction ranges for the architecture.
Updates #3685
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Prepare for header file move to common include directory.
Update #3254.
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The ARM C++ exception ABI uses an address ordered index table to
locate the correct frame data and this requires the EXIDX sections are
loaded in the order the order the matching text is loaded.
The EXIDX sections set the SHF_LINK_ORDER flag and link field. This patch
adds support to load those flagged sections in the linked-to section
order.
Updates #2955.
Closes #2959
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This has been tested on SPARC, i386, PowerPC and ARM.
Closes #2767.
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updates #2802.
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This is a merge of the RTL project.
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