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* libdebugger: Build for ARM's without a CP15.Chris Johns2016-12-026-1/+25
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* Remove sparc/sis BSP.Joel Sherrill2016-11-299-104/+0
| | | | closes #2810.
* arm/zynq: Wait for the UART TX FIFO to empty on reset.Chris Johns2016-11-293-0/+24
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* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-286-81/+107
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* or1k: Avoid multiple iterations over cacheMartin Erik Werner2016-11-281-0/+27
| | | | | | | | | Previously, if the cache range operations were called with a range that was larger than the cache size, this would lead to multiple iterations over the cache, which is unnecessary. Limit this so that if the range is larger than the cache size, the operations will only iterate over the whole cache once.
* or1k: Remove secondary functions in cache managerMartin Erik Werner2016-11-281-56/+34
| | | | | | | | | | Move the code of the _CPU_OR1K_Cache_{enable,disable}_* functions into the equivalent exported _CPU_cache_{enable,disable}_* functions instead, and then delete them, in order to reduce the code indirection and aid readability. This does not touch the currently unused prefetch, writeback, and lock functions.
* or1k: Avoid excessive ISR toggle in cache managerMartin Erik Werner2016-11-282-44/+123
| | | | | | | | | | | | | | | | | Previously _ISR_Local_{disable,enable}() was executed twice for each cache line operation, and since operations over the entire cache were implemented by calling the single-line operations in a loop, this made those operations rather costly. Fix the double-toggle by calling _OR1K_mtspr() directly, and removing the now-unused corresponding _CPU_OR1K_Cache_* functions. Fix the entire-operations by moving the ISR toggle outside of the loop, and by calling _OR1K_mtspr() directly instead of the single-line operations. Also implement range functions, since otherwise the cache manager falls back on looping over the single-line operations.
* or1k: Indent & comment fix in cache.cMartin Erik Werner2016-11-281-14/+25
| | | | | | | * Fix indentation of variable declarations. * Change commented-out asm -> __asm__ to meet c99 standard if uncommented.
* or1k: Add functions for entire cache operationsMartin Erik Werner2016-11-281-3/+42
| | | | | | | | | | | | | | | Add functions for flushing and invalidating whole cache. Since we don't have system calls that can operate on anything more than a single cache line, these simply retrieves the cache size and iterates over the full size, invalidating each line. The current implementation assumes that there's only one level of cache. These changes were contributed by Antmicro under contract by ÅAC Microtec AB. Close #2602
* bsps/arm: Add Cortex-M DWT CPU counterSebastian Huber2016-11-243-1/+57
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* score: Fix interrupt profilingSebastian Huber2016-11-241-20/+13
| | | | | | | | | | Callers of _Thread_Do_dispatch() must have a valid Per_CPU_Control::Stats::thread_dispatch_disabled_instant. Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt stack to not exceed Per_CPU_Control::Interrupt_frame. Update #2751.
* powerpc: Fix interrupt profiling for e6500Sebastian Huber2016-11-241-1/+3
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* bsp/lpc23xx_tli800: Disable tar01 testSebastian Huber2016-11-231-0/+1
| | | | Close #2824.
* powerpc/mpc5xx: Rename CPU_Interrupt_frameSebastian Huber2016-11-212-4/+4
| | | | | | The MPC5XX support uses a legacy interrupt/exception infrastructure. Close #2819.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-20/+66
| | | | Update #2751.
* sparc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-181-5/+5
| | | | Update #2751.
* score: Allow interrupts during thread dispatchSebastian Huber2016-11-182-19/+29
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
* powerpc: Add up to date CPU_Interrupt_frameSebastian Huber2016-11-186-388/+13
| | | | | | | Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the corresponding defines to <rtems/score/cpuimpl.h>. Update #2809.
* powerpc: Move legacy CPU_Interrupt_frameSebastian Huber2016-11-182-1/+33
| | | | | | | The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx support. Move it to here. Update #2809.
* bsps/powerpc: Avoid use of CPU_Interrupt_frameSebastian Huber2016-11-181-3/+3
| | | | | | | This type is not relevant for the code since only a pointer is passed around. Update #2809.
* sparc: Move CPU_Interrupt_frame related definesSebastian Huber2016-11-181-1/+1
| | | | | | Move CPU_Interrupt_frame related defines to <rtems/score/cpuimpl.h>. Update #2809.
* sparc: Rename CPU_Minimum_stack_frameSebastian Huber2016-11-182-5/+5
| | | | | | | | Rename SPARC-specific CPU_Minimum_stack_frame to SPARC_Minimum_stack_frame. Rename SPARC-specific CPU_MINIMUM_STACK_FRAME_SIZE to SPARC_MINIMUM_STACK_FRAME_SIZE. Update #2809.
* sparc64: Rename CPU_Minimum_stack_frameSebastian Huber2016-11-182-3/+3
| | | | | | | | Rename SPARC64-specific CPU_Minimum_stack_frame to SPARC64_Minimum_stack_frame. Rename SPARC64-specific CPU_MINIMUM_STACK_FRAME_SIZE to SPARC64_MINIMUM_STACK_FRAME_SIZE. Update #2809.
* bsps/mips: Use <libcpu/isr_entries.h>Sebastian Huber2016-11-187-7/+8
| | | | Avoid duplicate mips_vector_isr_handlers() declarations.
* arm: Use TPIDRPRW for current per-CPU controlSebastian Huber2016-11-181-5/+13
| | | | | | Use the previously unused TPIDRPRW register to get the per-CPU control of the current processor. This avoids instructions in GET_SELF_CPU_CONTROL which are not available in Thumb mode.
* bsp/atsamv: Make size of nocache-memory configurable.Christian Mauderer2016-11-172-2/+3
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* powerpc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-102-1/+12
| | | | | | | | Add _CPU_Get_current_per_CPU_control() on SMP configurations. Use SPRG0 for the current per-CPU control. This reduces the code size by three instructions and is slightly faster. Update #2805.
* score: Add and use Thread_Control::is_idleSebastian Huber2016-11-094-15/+4
| | | | Update #2797.
* bsp/qoriq: Remove duplicate qoriq_gpio definitionSebastian Huber2016-11-071-4/+0
| | | | Close #2800.
* virtex4, virtex5 bsp.h: Use BSP_INTERRUPT_STACK_SIZE not user space ↵Tim Cussins2016-11-032-2/+2
| | | | | | CONFIGURE_INTERRUPT_STACK_SIZE closes #2801.
* m68k/mrm332/make/custom/mrm332-testsuite.tcfg: Add dl05Joel Sherrill2016-11-031-0/+1
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* m68k/mcf5225x/make/custom/mcf5225x-testsuite.tcfg: Add dl05Joel Sherrill2016-11-031-0/+1
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* m68k/mcf52235/make/custom/mcf52235-testsuite.tcfg: Add dl05Joel Sherrill2016-11-031-0/+1
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* mcf5206elite/make/custom/mcf5206elite-testsuite.tcfg: Add dl05Joel Sherrill2016-11-031-0/+1
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* moxiesim/bsp_specs: Add crtbegin/end to fix link issuesJoel Sherrill2016-11-031-2/+2
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* bsps/sparc: Fix copy of initialized dataSebastian Huber2016-11-022-7/+8
| | | | | The text and data sections may have different alignment requirements. Support a data section alignment greater than 16.
* Updated xilinx_zynq_a9_qemu bsp README instructions.James2016-10-251-2/+2
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* bsps/sparc: Add interrupt controller registersSebastian Huber2016-10-191-2/+5
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* bsp/leon3: Avoid implicit integer conversionsSebastian Huber2016-10-191-8/+8
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* atsam: multiple messages on one cs low levelAlexander Krutwig2016-10-172-8/+14
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* libchip/network/if_fxp.c: do not use rtems_interrupt_disable.Pavel Pisa2016-10-171-7/+4
| | | | | | | | | | The single write to memory or ioport output are mostly atomic operations already. The proper memory synchronization barrier should be used around them to guarantee ordering (sync or eieio on PowerPC for example) but because I have not found settable portable primitive only compiler barrier is used. It should be enough on x86 because the externally visible order should be/is guaranteed to be preserved on x86 architecture.
* bsps/i386: use Pentimum instructions for pc586 and pc686 builds.Pavel Pisa2016-10-172-2/+2
| | | | | | | | | | | | | | | | | | When GCC option -march is not specifies i386-rtems toolchain defaults to i386 architecture instruction set. It does not provide atomic instructions which results in really inefficient atomic_fetch_or even on UP build. SMP build is broken with i386 set because libatomic and GCC generate infinite loop for __atomic_fetch_add_4 used in rtems_interrupt_lock_acquire __atomic_fetch_add_4: push %ebp mov %esp,%ebp movl $0x5,0x10(%ebp) pop %ebp jmp __atomic_fetch_add_4
* bsps/i386: replace global interrupt disable by SMP build supporting locking.Pavel Pisa2016-10-179-72/+148
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* bsp/atsamv: Fix typoSebastian Huber2016-10-131-1/+1
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* bsps/i386: Separate variable for i8259 IRQs disable due to in progress state.Pavel Pisa2016-10-111-19/+36
| | | | | | | | The global state of enabled and disabled interrupts has to hold interrupts really disabled by drivers and system. If the state is combined with interrupts temporarily disabled because they are processed at given time then it is impossible to maintain state by interrupt handlers in drivers.
* bsp/qoriq: Add GPIO register mapSebastian Huber2016-10-111-1/+14
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* bsps/sparc: Support GR740 GPIOSebastian Huber2016-10-111-0/+22
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* bsp/atsam: Provide default buffer countsSebastian Huber2016-10-051-2/+11
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* bsp/atsam: Fix PHY detectionSebastian Huber2016-10-051-16/+11
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* bsp/mvme147*: Fix linker issueSebastian Huber2016-09-232-6/+2
| | | | | The GNU linker does not allow a nonconstant expression for a region length.
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