diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-10-11 08:25:39 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-10-11 08:33:28 +0200 |
| commit | 00bac953f75db975739d05146fdfadc0a50168a5 (patch) | |
| tree | 6cfacc2b21d7cd02dbcd56b3a7f1809ae03e6e17 /c | |
| parent | tmfine01: Add self-contained mutex test case (diff) | |
| download | rtems-00bac953f75db975739d05146fdfadc0a50168a5.tar.bz2 | |
bsps/sparc: Support GR740 GPIO
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/include/grlib.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/include/grlib.h b/c/src/lib/libbsp/sparc/shared/include/grlib.h index 3c207933a9..72698e6b14 100644 --- a/c/src/lib/libbsp/sparc/shared/include/grlib.h +++ b/c/src/lib/libbsp/sparc/shared/include/grlib.h @@ -104,6 +104,28 @@ struct grgpio_regs { volatile unsigned int ipol; /* 0x10 Interrupt polarity register */ volatile unsigned int iedge; /* 0x14 Interrupt edge register */ volatile unsigned int bypass; /* 0x18 Bypass register */ + volatile unsigned int cap; /* 0x1C Capability register */ + volatile unsigned int irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */ + volatile unsigned int res_30; /* 0x30 Reserved */ + volatile unsigned int res_34; /* 0x34 Reserved */ + volatile unsigned int res_38; /* 0x38 Reserved */ + volatile unsigned int res_3C; /* 0x3C Reserved */ + volatile unsigned int iavail; /* 0x40 Interrupt available register */ + volatile unsigned int iflag; /* 0x44 Interrupt flag register */ + volatile unsigned int res_48; /* 0x48 Reserved */ + volatile unsigned int pulse; /* 0x4C Pulse register */ + volatile unsigned int res_50; /* 0x50 Reserved */ + volatile unsigned int output_or; /* 0x54 I/O port output register, logical-OR */ + volatile unsigned int dir_or; /* 0x58 I/O port direction register, logical-OR */ + volatile unsigned int imask_or; /* 0x5C Interrupt mask register, logical-OR */ + volatile unsigned int res_60; /* 0x60 Reserved */ + volatile unsigned int output_and; /* 0x64 I/O port output register, logical-AND */ + volatile unsigned int dir_and; /* 0x68 I/O port direction register, logical-AND */ + volatile unsigned int imask_and; /* 0x6C Interrupt mask register, logical-AND */ + volatile unsigned int res_70; /* 0x70 Reserved */ + volatile unsigned int output_xor; /* 0x74 I/O port output register, logical-XOR */ + volatile unsigned int dir_xor; /* 0x78 I/O port direction register, logical-XOR */ + volatile unsigned int imask_xor; /* 0x7C Interrupt mask register, logical-XOR */ }; /* L2C - Level 2 Cache Controller registers */ |