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* libcpu/sh: Build cache stubs so apps usign cache API linkJoel Sherrill2014-04-223-8/+40
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* score: Clarify TLS supportSebastian Huber2014-04-171-1/+1
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* bsps/powerpc: SMP support for SPR functionsSebastian Huber2014-04-161-19/+19
| | | | | These registers are local to a processor, there is no need to use SMP locks here.
* bsps/powerpc: SMP support for one TSEC driverSebastian Huber2014-04-151-13/+16
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* bsps/powerpc: PR757: Fix PPC_IRQ_TRACE for ppc601Sebastian Huber2014-04-011-0/+1
| | | | We could probably also remove the ppc601 support entirely.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-21261-262/+262
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* bsps/powerpc: Add support for interrupt profilingSebastian Huber2014-03-141-2/+51
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* bsp/arm: Add CP15 methodsRalf Kirchner2014-03-131-1/+98
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* bsps/powerpc: Fix GET_INTERRUPT_MASK macroSebastian Huber2014-03-121-1/+2
| | | | | Use _PPC_INTERRUPT_DISABLE_MASK introduced with 801b5d80325dbd3e92218271d54e75f389da7136.
* sapi: Use one SMP lock for all chainsSebastian Huber2014-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This partially reverts commit 1215fd4d9426a59d568560e9a485628560363133. In order to support profiling of SMP locks and provide a future compatible SMP locks API it is necessary to add an SMP lock destroy function. Since the commit above adds an SMP lock to each chain control we would have to add a rtems_chain_destroy() function as well. This complicates the chain usage dramatically. Thus revert the patch above. A global SMP lock for all chains is used to implement the protected chain operations. Advantages: * The SAPI chain API is now identical on SMP and non-SMP configurations. * The size of the chain control is reduced and is then equal to the Score chains. * The protected chain operations work correctly on SMP. Disadvantage: * Applications using many different chains and the protected operations may notice lock contention. The chain control size drop is a huge benefit (SAPI chain controls are 66% larger than the Score chain controls). The only disadvantage is not really a problem since these applications can use specific interrupt locks and unprotected chain operations to avoid this issue.
* rtems: Add cache size functionsSebastian Huber2014-02-281-0/+21
| | | | | Add rtems_cache_get_data_cache_size() and rtems_cache_get_instruction_cache_size().
* rtems: Use size_t for cache line sizeSebastian Huber2014-02-283-4/+4
| | | | A cache line cannot have a negative size.
* score: Add RTEMS_FATAL_SOURCE_BSPSebastian Huber2014-02-193-6/+7
| | | | | | Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to figure out the code position given a fatal source and code.
* powerpc: Change interrupt disable implemetationSebastian Huber2014-02-192-6/+0
| | | | | | | | | | | | Instead of SPRG0 (= special purpose register 272) use the new global symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask. The benefit is that it is now possible to disable interrupts without further run-time initialization in boot_card(). At least on Freescale e500 cores this leads also to a faster execution since the mfmsr and mfspr instruction require four cycles to complete. The instructions to load the mask value can execute while the mfmsr is in progress.
* Add thread-local storage (TLS) supportSebastian Huber2014-02-041-3/+13
| | | | | Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
* rtems_cache_invalidate_multiple_instruction_linesAleksandr Platonov2014-01-141-1/+1
| | | | | | | | According with comment in rtems_cache_invalidate_multiple_instruction_lines(), final_address indicates the last address which needs to be invalidated. But if in while loop we got final_address == i_addr condition then loop breaks and final_address will not be invalidated.
* bsps/arm: Use Normal memory for code and dataSebastian Huber2014-01-131-3/+7
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* libcpu/powerpc/mpc5xx: use THREAD_DISABLE_DISPATCH_LEVEL in asmChirayu Desai2013-12-061-13/+13
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* bsps/powerpc: Unconditionally clear reservationsSebastian Huber2013-12-031-7/+8
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* powerpc: Add r2 to CPU contextSebastian Huber2013-11-182-1/+7
| | | | The r2 may be used for thread-local storage.
* bsps/arm: ARMV7_MMU_DATA_READ_WRITE_SHAREABLESebastian Huber2013-10-271-5/+9
| | | | | Delete ARMV7_MMU_DATA_READ_WRITE_SHAREABLE and move RTEMS_SMP specific MMU attribute settings to arm-cp15.h.
* Add a new necessary definition needed for raspberrypi MMU supportHesham AL-Matary2013-10-031-0/+21
| | | | | | | | | | | The new ARM_CP15_CTRL_XP is necessary to share ARMv6 and ARMv7 page-table formats and definitions. It enables the extended page tables (introduced in ARMv6) to be configured for the hardware page translation mechanism. This way we can share ARMv6 and ARMv7 page tables entry formats. Other Fault Status Register Definitions can be useful for debugging or excpetion handlers.
* libcpu/sparc/.../access_le.c: Add include file to fix warningJoel Sherrill2013-09-231-0/+1
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* bsps: Fix cache manager supportSebastian Huber2013-09-103-0/+12
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* bsps/arm: Fix ARM CP15 opcode for get functionsSebastian Huber2013-09-051-3/+3
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* sapi: SMP support for chainsSebastian Huber2013-08-301-1/+1
| | | | | | | | Add ISR lock to chain control for proper SMP protection. Replace rtems_chain_extract() with rtems_chain_explicit_extract() and rtems_chain_insert() with rtems_chain_explicit_insert() on SMP configurations. Use rtems_chain_explicit_extract() and rtems_chain_explicit_insert() to provide SMP support.
* bsp/xilinx-zynq: Add cache supportRic Claus2013-08-261-1/+18
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* bsps/arm: Add more CP15 cache functionsRic Claus2013-08-221-0/+65
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* bsps: Fix clock driver definesSebastian Huber2013-08-142-3/+3
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* bsps/powerpc: Per-CPU thread dispatch disableSebastian Huber2013-08-093-53/+45
| | | | Interrupt support for per-CPU thread dispatch disable level.
* score: Per-CPU thread dispatch disable levelSebastian Huber2013-08-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
* bsp/csb336: implement bsp_interrupt_vector_enable/disable.Pavel Pisa2013-08-091-0/+10
| | | | Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* score: Rename tod.h to todimpl.hSebastian Huber2013-08-011-1/+1
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* bsp/csb336: mc9328mxl correct AITC access in bsp_interrupt_dispatch.Pavel Pisa2013-07-261-1/+2
| | | | | | | | | | | The original version is missing void and result is that (*x >> 16) is optimized to ldh rX,[rY]. But it is not allowed/supported to access bus/address range used by AITC by other than 32 bit wide accesses and 16-bit access results in the data abort exception. The corrected version works on real hardware and is even more readable. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* score: Merge tod implementation into one fileSebastian Huber2013-07-261-0/+1
| | | | | Delete TOD_MICROSECONDS_PER_SECOND, TOD_MICROSECONDS_TO_TICKS() and TOD_MILLISECONDS_TO_TICKS().
* Include missing <rtems/score/threaddispatch.h>Sebastian Huber2013-07-266-8/+11
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* bsp/mpc55xx: Fix prototypePeter Dufault2013-07-241-1/+1
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* score: Merge sysstate API into one fileSebastian Huber2013-07-241-0/+1
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* bsp/mpc55xx: Add MPC5668G supportSebastian Huber2013-07-157-13/+6770
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* bsps/powerpc: Add ppc_count_leading_zeros()Sebastian Huber2013-07-091-0/+13
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* powerpc: Fix Altivec supportSebastian Huber2013-06-261-1/+1
| | | | Use the right context.
* termios: Update due to API changesSebastian Huber2013-06-259-60/+58
| | | | | Termios notifies now the driver about an inactive transmit with the length argument set to zero.
* bsps/powerpc: Delete clock_4xx.cSebastian Huber2013-06-241-225/+0
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* bsps: Move bsp_generic_fatal_code to new fileSebastian Huber2013-06-211-5/+2
| | | | Add bsp_generic_fatal().
* bsps/powerpc: Delete bsp_exceptions_in_RAMSebastian Huber2013-06-214-68/+77
| | | | | Delete ppc_exc_vector_base. Add and use ppc_exc_initialize_with_vector_base().
* bsps/arm: Set vector base address if necessarySebastian Huber2013-06-201-0/+47
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* score: Add and use _Thread_Dispatch_is_enabled()Sebastian Huber2013-06-144-4/+4
| | | | | Delete _Thread_Dispatch_in_critical_section() and _Thread_Is_dispatching_enabled().
* smp: Fix PowerPC context switchSebastian Huber2013-06-071-1/+1
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* bsps/arm: Add SMP supportSebastian Huber2013-05-311-0/+57
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* smp: Add PowerPC supportSebastian Huber2013-05-311-0/+23
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