diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-02-26 11:00:17 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-02-28 08:59:02 +0100 |
| commit | e7549ff4a195e6985044945ac4e1f37a5f1ef7fb (patch) | |
| tree | 765b9e7ea45ebc1a33b5536707eab1d60d88ba93 /c/src/lib/libcpu | |
| parent | rtems: Cache manager documentation (diff) | |
| download | rtems-e7549ff4a195e6985044945ac4e1f37a5f1ef7fb.tar.bz2 | |
rtems: Use size_t for cache line size
A cache line cannot have a negative size.
Diffstat (limited to 'c/src/lib/libcpu')
| -rw-r--r-- | c/src/lib/libcpu/bfin/network/ethernet.c | 2 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c | 2 | ||||
| -rw-r--r-- | c/src/lib/libcpu/shared/src/cache_manager.c | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/c/src/lib/libcpu/bfin/network/ethernet.c b/c/src/lib/libcpu/bfin/network/ethernet.c index 873d105250..8903e0355a 100644 --- a/c/src/lib/libcpu/bfin/network/ethernet.c +++ b/c/src/lib/libcpu/bfin/network/ethernet.c @@ -629,7 +629,7 @@ static void initializeHardware(struct bfin_ethernetSoftc *sc) { including other status structures, so we can safely manage both the processor and DMA writing to them. So this rounds up the structure sizes to a multiple of the cache line size. */ - cacheAlignment = rtems_cache_get_data_line_size(); + cacheAlignment = (int) rtems_cache_get_data_line_size(); if (cacheAlignment == 0) cacheAlignment = 1; rxStatusSize = cacheAlignment * ((sizeof(rxStatusT) + cacheAlignment - 1) / diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c index fc144e3e24..3b9d06ff60 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c @@ -21,7 +21,7 @@ int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum) /* Do we have a dcbz instruction? */ if ((opcode & 0xffe007ff) == 0x7c0007ec) { - unsigned clsz = (unsigned) rtems_cache_get_data_line_size(); + unsigned clsz = rtems_cache_get_data_line_size(); unsigned a = (opcode >> 16) & 0x1f; unsigned b = (opcode >> 11) & 0x1f; unsigned *regs = &frame->GPR0; diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index c2c460a0d6..8fa0477748 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src/lib/libcpu/shared/src/cache_manager.c @@ -149,7 +149,7 @@ rtems_cache_invalidate_entire_data( void ) /* * This function returns the data cache granularity. */ -int +size_t rtems_cache_get_data_line_size( void ) { #if defined(CPU_DATA_CACHE_ALIGNMENT) @@ -264,7 +264,7 @@ rtems_cache_invalidate_entire_instruction( void ) /* * This function returns the instruction cache granularity. */ -int +size_t rtems_cache_get_instruction_line_size( void ) { #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |