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* sparc: Move libcpu content to cpukitSebastian Huber2018-03-137-748/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Rework cache manager implementationSebastian Huber2018-01-313-71/+0
| | | | | | | | | | | | | | | | | | The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
* Remove make preinstallChris Johns2018-01-254-79/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
* sparc: Move <libcpu/byteorder.h>Sebastian Huber2018-01-023-71/+0
| | | | | Update #3254. Update #3260.
* bsps: Do not install <libcpu/cache.h>Sebastian Huber2017-12-082-5/+1
| | | | | | This is a cache manager implementation header file. Update #3254.
* sparc: Add lazy floating point switchSebastian Huber2017-07-251-1/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus, from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically, the deferred floating point switch was used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus, in case an interrupt handler uses the floating point unit then this will result in a trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT). In uniprocessor configurations, a lazy floating point context switch is used. In case an active floating point thread is interrupted (PSR[EF] == 1) and a thread dispatch is carried out, then this thread is registered as the floating point owner. When a floating point owner is present during a context switch, the floating point unit is disabled for the heir thread (PSR[EF] == 0). The floating point disabled trap checks that the use of the floating point unit is allowed and saves/restores the floating point context on demand. Update #3077.
* bsps/sparc: Fix cache supportSebastian Huber2017-07-191-4/+9
| | | | | | | Fix infinite loop in rtems_invalidate_multiple_instruction_lines(). Implement this function. Close #3080.
* sparc: Add assembly workaround for LEON3FT B2BST errataDaniel Cederman2017-07-172-0/+40
| | | | | | | | | | | | | | | This patch adds NOP instructions to prevent instruction sequences that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with Data Tag Parity Error" for more information. The sequences are only modified if __FIX_LEON3FT_B2BST is defined. The patch works in conjunction with the -mfix-ut700, -mfix-gr712rc, and -mfix-ut699 GCC flags that prevents the sensitive sequences from being generated. Update #3057.
* sparc: Adjust assembly to improve compability with LLVMJacob Hansen2017-05-143-5/+5
| | | | | | | | | | | | | - All references of %0 changed to %g0 - 'call label,0' changed to 'call label'. According to the sparc specification call does not take any registers - '.seg "text"' changed to '.section ".text"' - the synonym stub is replaced with stb - the synonym stuh is replaced with sth
* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-281-0/+37
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* sparc: Fix window underflow trap handlerDaniel Hellstrom2016-03-171-6/+6
| | | | | | | | | | | | The window underflow trap handler used %i5 which destroyed the %o5 of the calling context. Bug introduced by 0d3b5d47429effb350448d9e9123a67db722109f. Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour and use the two unused instructions in the trap vector to optimize a bit. Update #2651.
* bsps/sparc: Use inline functions for cache managerSebastian Huber2015-04-273-46/+32
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* Update bug report URLSebastian Huber2014-12-051-1/+1
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* SPARC: optimize IRQ enable & disableDaniel Hellstrom2014-12-042-55/+65
| | | | | | | | | | | | | | | | * Coding style cleanups. * Use OS reserved trap 0x89 for IRQ Disable * Use OS reserved trap 0x8A for IRQ Enable * Add to SPARC CPU supplement documentation This will result in faster Disable/Enable code since the system trap handler does not need to decode which function the user wants. Besides the IRQ disable/enabled can now be inline which avoids the caller to take into account that o0-o7+g1-g4 registers are destroyed by trap handler. It was also possible to reduce the interrupt trap handler by five instructions due to this.
* SPARC: optimize window underflow trapDaniel Hellstrom2014-12-021-8/+6
| | | | | | | | | | | Save five instructions on underflow handling. By using an optimized trap entry we can move instructions from the window underflow function into the trap entry vector. By setting WIM=0 and using RESTORE it is possible to move the new WIM register content from the trapped window into the to-be-restored register window. It is then possible to avoid the WIM write delay.
* SPARC: optimize window overflow trap entryDaniel Hellstrom2014-12-021-0/+1
| | | | | | | | By using a optimized trap entry we can move instructions from the window overflow function into the trap entry vector. By using the saved locals instead of g1 we don't need to save that register temporarily. Also spead out non store instructions inbetween stores to use the write buffer better.
* SPARC: window overflow optimizationDaniel Hellstrom2014-12-021-16/+9
| | | | | I see no need for waiting the 3 instruction delay for wim to be written in this case, since the STD after does not depend on WIM
* rtems: Move rtems_cache_aligned_malloc()Sebastian Huber2014-11-251-1/+1
| | | | | | Make sure also the size is cache aligned since otherwise we may have some overlap with the next allocation block. A cache invalidate on this area would be fatal.
* score/sparc: Add support for paravirtualizationChristian Mauderer2014-06-031-0/+36
| | | | | | | Guest systems in paravirtualization environments run usually in user mode. Thus it is not possible to directly access the PSR and TBR registers. Use functions instead of inline assembler to access these registers if RTEMS_PARAVIRT is defined.
* SPARC: syscall optimizations and PSR-write fixDaniel Hellstrom2014-05-281-14/+14
| | | | | | | | | | | | | | | The last optimization missed was incorrect in regards to PSR write instruction delay must be 3 instructions. New optimizations: * align to 32-byte cache line. * rearrange code into three "blocks" of 4 instructions that is executed by syscall 2 and 3. This is to optimize for 16/32 byte cache lines. * use delay-slot instruction in trap table to reduce by one instruction. * use the fact that "wr %PSR" implements XOR to reduce by one instruction.
* SPARC: add syscall 1 (exit) function entry pointDaniel Hellstrom2014-05-231-0/+13
| | | | | | The exit SPARC system call doesn't have a function entry point like the others do. This is probably why people use TA 0x0 instruction directly for shutting down the system.
* SPARC: syscall code clean-up and minor optimizationsDaniel Hellstrom2014-05-231-16/+11
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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-214-4/+4
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* libcpu/sparc/.../access_le.c: Add include file to fix warningJoel Sherrill2013-09-231-0/+1
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* bsps: Fix cache manager supportSebastian Huber2013-09-102-0/+9
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* RTEMS: Delete ChangeLog files.Gedare Bloom2013-03-081-276/+0
| | | | | | | | | This commit deletes all RTEMS ChangeLog files. These files have been abandoned since converting to git version control. The historical data may be recovered by checking out any commit before this one. Most of the contents of these ChangeLog files can also be found in the git log. Two external ChangeLog files, ChangeLog.slac and ChangeLog.zlib, remain.
* Require automake-1.12.2.Ralf Corsépius2012-07-191-1/+1
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* Require autoconf-2.69.Ralf Corsépius2012-07-191-1/+1
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* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-113-5/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* Remove CVS-Ids.Ralf Corsépius2012-05-042-6/+0
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* SPARC: added libcpu lowlevel access and byteorder routines/definitionsDaniel Hellstrom2012-03-216-0/+244
| | | | | | | | | | | | The low level routines can be used in different occasions, it will be required when accessing PCI. Note the difference between byteorder.h (inlined functions) and access.S where the functions will be declared in the library archive librtemscpu.a. Function names starting with _ are in library and can be referenced by function pointers. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* Remove all .cvsignore files.Joel Sherrill2012-02-011-8/+0
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* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-112-1/+6
| | | | | * cache/cache.c: Use "__asm__" instead of "asm" for improved c99-compliance.
* 2011-02-02 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-022-2/+6
| | | | * configure.ac: Require autoconf-2.68, automake-1.11.1.
* Whitespace removal.Ralf Corsepius2009-11-302-27/+27
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* Whitespace removal.Ralf Corsepius2009-11-281-1/+1
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* 2008-09-30 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2008-09-302-1/+5
| | | | * preinstall.am: Regenerated.
* 2008-09-26 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2008-09-262-1/+5
| | | | * Makefile.am: Remove superfluous $(top_srcdir).
* Cleanup.Ralf Corsepius2008-07-141-6/+0
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* 2007-07-31 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-07-312-1/+8
| | | | | | | PR 1249/build * configure.ac: Jerry Needell <jerry.needell@unh.edu> reported that the leon3 was left out of the cache enable logic. Thus the cache management support code was empty on LEON3 CPUs.
* Regenerate.Ralf Corsepius2007-01-081-1/+1
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* 2006-12-02 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2006-12-022-1/+5
| | | | * configure.ac: New BUG-REPORT address.
* 2006-10-17 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2006-10-172-2/+6
| | | | * configure.ac: Require autoconf-2.60. Require automake-1.10.
* 2006-05-16 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2006-05-162-3/+5
| | | | * configure.ac: Use RTEMS_AMPOLISH3.
* Regenerate.Ralf Corsepius2006-01-141-1/+1
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* Regenerate.Ralf Corsepius2006-01-121-0/+2
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* Remove all-local:.Ralf Corsepius2006-01-121-2/+0
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* Regenerate.Ralf Corsepius2006-01-121-2/+2
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* Cleanup.Ralf Corsepius2006-01-121-4/+0
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* 2005-11-04 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-11-042-2/+4
| | | | * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP.
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