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* bsps/powerpc: Move MMU support to bspsSebastian Huber2018-03-261-545/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps/powerpc: Fix warningsSebastian Huber2017-02-151-10/+10
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* libcpu/powerpc/mpc6xx/mmu/bat.c: Now compiles with gcc 5.xJoel Sherrill2015-01-131-12/+12
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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-111-3/+3
| | | | | | | | | | | | | | * e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c, mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c, mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c, mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c, new-exceptions/bspsupport/ppc_exc_initialize.c, ppc403/clock/clock.c, ppc403/console/console.c, ppc403/console/console.c.polled, ppc403/console/console405.c, ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c, rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c: Use "__asm__" instead of "asm" for improved c99-compliance.
* 2011-01-28 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2011-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | * mpc5xx/exceptions/raw_exception.c, mpc5xx/exceptions/raw_exception.h, mpc5xx/include/console.h, mpc5xx/include/mpc5xx.h, mpc5xx/irq/irq.c, mpc5xx/irq/irq.h, mpc5xx/irq/irq_asm.S, mpc5xx/vectors/vectors.h, mpc5xx/vectors/vectors_init.c, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, new-exceptions/bspsupport/irq.c, new-exceptions/bspsupport/irq_supp.h, new-exceptions/bspsupport/nested_irq_test.c, new-exceptions/bspsupport/ppc_exc_address.c, new-exceptions/bspsupport/ppc_exc_categories.c, new-exceptions/bspsupport/ppc_exc_global_handler.c, new-exceptions/bspsupport/ppc_exc_hdl.c, new-exceptions/bspsupport/ppc_exc_initialize.c, new-exceptions/bspsupport/ppc_exc_prologue.c, new-exceptions/bspsupport/ppc_exc_test.c, new-exceptions/bspsupport/vectors.h, shared/include/byteorder.h, shared/include/cpuIdent.c, shared/include/cpuIdent.h, shared/include/io.h, shared/include/mmu.h, shared/include/page.h, shared/include/pgtable.h, shared/include/spr.h: Fix typo where license said found in found in.
* 2009-12-01 Till Straumann <strauman@slac.stanford.edu>Till Straumann2009-12-021-1/+2
| | | | | | * mpc6xx/mmu/bat.c, mpc6xx/mmu/pte121.c: skip data- streaming (dssall etc.) instructions on PPC_PSIM currently (unimplemented by PSIM :-( ).
* Whitespace removal.Ralf Corsepius2009-11-301-2/+2
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* 2009-10-22 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2009-10-221-3/+3
| | | | * mpc6xx/mmu/bat.c: Add missing prototypes.
* 2009-10-16 Jennifer Averett <jennifer.averett@OARcorp.com>Joel Sherrill2009-10-161-6/+7
| | | | | * mpc6xx/mmu/bat.c: Resolved bug: It is not an overlap if the batindex being set is the batindex of the overlap.
* 2009-08-27 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2009-08-271-1/+1
| | | | * mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h: Fix spelling.
* 2009-05-05 Jennifer Averett <jennifer.averett@OARcorp.com>Jennifer Averett2009-05-051-3/+3
| | | | | | | | * mpc6xx/mmu/bat.c, new-exceptions/e500_raw_exc_init.c, new-exceptions/raw_exception.h, new-exceptions/bspsupport/irq_supp.h, shared/include/cpuIdent.c: Removed warnings. Split bsp_irq_dispatch_list to allow non-standard/non-existant pics to call with interrupts off.
* 2007-11-30 Till Straumann <strauman@slac.stanford.edu>Till Straumann2007-12-011-10/+3
| | | | | | | * mpc6xx/mmu/bat.c, mpc6xx/mmu/pte121.c: use new feature-checks from cpuIdent.h rather than filtering CPU types when checking for availability of high BATs and an MMU with hardware page-table lookup.
* 2007-11-29 Till Straumann <strauman@slac.stanford.edu>Till Straumann2007-11-301-99/+163
| | | | | * mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h: Added support for setting & reading IBATs.
* * mpc6xx/mmu/bat.c, mpc6xx/mmu/pte121.c, shared/src/cache.c:Till Straumann2006-07-131-0/+1
| | | | | | Checked inline assembly code; added 'm' operands and paranoia 'memory' clobbers. Also, made sure that no pure input operands are modified by the asm.
* 2005-11-02 straumanatslacdotstanford.eduTill Straumann2005-11-031-28/+445
| | | | | | | | * mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S: moved assembly code to C; setdbat now supports high bats on 7450 CPUs; added argument checking to setdbat; added getdbat; moved early initialization code (clear_bats) from BSP to libcpu (CPU_clear_bats_early)
* 2004-11-10 Richard Campbell <richard.campbell@oarcorp.com>Joel Sherrill2004-11-101-2/+2
| | | | | | | | * configure.ac, mpc6xx/exceptions/raw_exception.c, mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, shared/include/cpuIdent.c, shared/include/cpuIdent.h: Add MPC8240 and MPC8245 support. There was also a significant amount of spelling and whitespace cleanup.
* Remove stray white spaces.Ralf Corsepius2004-04-151-1/+0
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* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-041-1/+1
| | | | | | | | | | | | | | | | | | | | | * mpc6xx/clock/c_clock.c, mpc6xx/clock/c_clock.h, mpc6xx/exceptions/raw_exception.c, mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, mpc6xx/timer/timer.c, mpc8260/clock/clock.c, mpc8260/console-generic/console-generic.c, mpc8260/cpm/brg.c, mpc8260/exceptions/raw_exception.c, mpc8260/exceptions/raw_exception.h, mpc8260/include/cpm.h, mpc8260/include/mmu.h, mpc8260/mmu/mmu.c, mpc8260/timer/timer.c, mpc8xx/clock/clock.c, mpc8xx/console-generic/console-generic.c, mpc8xx/exceptions/raw_exception.c, mpc8xx/exceptions/raw_exception.h, mpc8xx/include/cpm.h, mpc8xx/include/mmu.h, mpc8xx/mmu/mmu.c, mpc8xx/timer/timer.c, ppc403/clock/clock.c, ppc403/console/console.c.polled, ppc403/timer/timer.c, rtems/powerpc/debugmod.h, shared/include/byteorder.h, shared/include/cpuIdent.c, shared/include/cpuIdent.h, shared/include/io.h, shared/include/mmu.h, shared/include/page.h, shared/include/pgtable.h, shared/include/spr.h: URL for license changed.
* 2003-02-20 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill2003-02-201-2/+7
| | | | | | | | | | | | | | | PR 349/bsps * mpc6xx/exceptions/raw_exception.c, mpc6xx/mmu/bat.c, mpc6xx/mmu/pte121.c, shared/include/cpuIdent.c, shared/include/cpuIdent.h, shared/src/Makefile.am, shared/src/stack.c, shared/src/stackTrace.h, powerpc/registers.h: - undo improper 'fix' who broke mpc604r identification - fix: 7400 identification PVR value was wrong - enhance 'setdbat()' to switch OFF a given BAT if called with 0 size - fix: page table support bugfix - enhancement: provide routines to take and print stack trace snapshots - add definitions for HID1 and DABR SPRs
* 2002-10-31 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-10-311-0/+1
| | | | | * mpc6xx/clock/c_clock.c, mpc6xx/exceptions/raw_exception.c, mpc6xx/mmu/bat.c: Removed warnings.
* 2002-07-22 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill2002-07-221-1/+1
| | | | | | * mpc6xx/mmu/bat.c: Per PR241, fix a tiny bug introduced by the fix for an earlier patch (PR213) which added support for setting BAT0 to setdbat().
* 2001-05-14 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill2002-05-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | * rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add the following: - support for the MPC74000 (AKA G4); there is no AltiVec support yet, however. - the cache flushing assembly code uses hardware-flush on the G4. Also, a couple of hardcoded numerical values were replaced by more readable symbolic constants. - extended interrupt-disabled code section so enclose the entire cache flush/invalidate procedure (as recommended by the book). This is not (latency) critical as it is only used by init code but prevents possible corruption. - Trivial page table support as been added. (1:1 effective-virtual-physical address mapping which is only useful only on CPUs which feature hardware TLB replacement, e.g. >604. This allows for write-protecting memory regions, e.g. text/ro-data which makes catching corruptors a lot easier. It also frees one DBAT/IBAT and gives more flexibility for setting up address maps :-) - setdbat() allows changing BAT0 also (since the BSP may use a page table, BAT0 could be available...). - asm_setdbatX() violated the SVR ABI by using r20 as a scratch register; changed for r0 - according to the book, a context synchronizing instruction is necessary prior to and after changing a DBAT -> isync added
* Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>.Joel Sherrill1999-12-021-0/+64
As part of this effort, the mpc750 libcpu code is now shared with the ppc6xx.
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