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* bsps: Move interrupt controller support to bspsSebastian Huber2018-04-231-661/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* libbsp/mips/shared: Fix warningsJoel Sherrill2014-10-191-11/+4
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* score: Statically initialize _ISR_Vector_tableSebastian Huber2014-04-291-1/+0
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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* score: Per-CPU thread dispatch disable levelSebastian Huber2013-08-091-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2010-07-30 Gedare Bloom <giddyup44@yahoo.com>Joel Sherrill2010-07-301-1/+1
| | | | | | PR 1599/cpukit * shared/irq/exception.S: Rename _Context_Switch_necessary to _Thread_Dispatch_necessary to more properly reflect the intent.
* 2010-07-06 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2010-07-061-1/+0
| | | | | * shared/irq/exception.S: Removed _ISR_Signals_to_thread_executing declaration.
* 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-06-291-10/+8
| | | | | | | | PR 1573/cpukit * shared/irq/exception.S: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
* 2010-05-13 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-05-131-22/+56
| | | | | * shared/irq/exception.S: rbtx4925, rbtx4938, and hurricane had very similar versions of exception. Now all use shared/irq/exception.S
* 2010-05-13 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-05-131-0/+641
* shared/irq/exception.S: New file.