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2018-04-20bsps: Move startup files to bspsSebastian Huber1-673/+0
2017-04-24uC5282/startup/bspstart.c: Fix printf() format warningsJoel Sherrill1-6/+16
2014-10-16mcf5282: Move cache to libcpu and update av5282 and uC5282 BSPsJoel Sherrill1-108/+22
2014-10-13m68k/uC5282: Fix warningsJoel Sherrill1-48/+4
2014-10-09m68k/uC5282/startup/bspstart.c: Add include of <bsp/bootcard.h> to fix warnin...Joel Sherrill1-12/+5
2014-03-21Change all references of rtems.com to rtems.org.Chris Johns1-1/+1
2012-05-11Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill1-2/+0
2011-03-152011-03-15 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill1-5/+20
2011-02-172011-02-17 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill1-4/+67
2011-02-112011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius1-7/+7
2010-04-26 * startup/bspstart.c: Clean up some warnings.Eric Norum1-1/+2
2009-11-29Whitespace removal.Ralf Corsepius1-18/+18
2009-11-032009-11-03 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius1-1/+1
2009-09-092009-09-09 Till Straumann <strauman@slac.stanford.edu>Till Straumann1-0/+40
2009-07-30Enable data cache.Eric Norum1-5/+4
2009-07-28PR 1420/bspsEric Norum1-2/+7
2009-06-02As per Freescale chip errata, disable buffered writes.Eric Norum1-3/+15
2008-09-232008-09-23 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill1-3/+3
2008-09-162008-09-16 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill1-6/+6
2008-09-162008-09-16 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill1-37/+12
2008-05-19Back out changes from 2008-05-16 -- they don't seem to work.Eric Norum1-4/+24
2008-05-16Use shared version of bootstrap to set up workspace.Eric Norum1-24/+4
2008-05-122008-05-12 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill1-1/+0
2008-04-24More clean up of FPGA interrupts.Eric Norum1-2/+1
2008-04-08startup/bspstart.c: Clean up non-FPGA use of EPORT interrupts.Eric Norum1-11/+3
2007-12-112007-12-11 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill1-9/+1
2007-12-042007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill1-6/+0
2007-12-032007-12-03 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill1-6/+0
2007-11-262007-11-26 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill1-199/+202
2007-03-122007-03-12 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-1/+1
2007-03-112007-03-11 Joel Sherrill <joel@OARcorp.com>Joel Sherrill1-3/+2
2006-12-15 * startup/bspstart.c: Changed BSP_installVME_isr() so thatTill Straumann1-69/+138
2006-08-01Add bsp_setbenv system call.Eric Norum1-1/+2
2006-05-15Allow single spurious FPGA interrupt.Eric Norum1-3/+8
2006-05-15Improve handling of unexpected FPGA interrupt conditions.Eric Norum1-3/+19
2006-04-11Add default exception handler.Eric Norum1-0/+52
2006-03-24Add missing reset cause bit.Eric Norum1-0/+1
2006-02-06Avoid possible division by zero.Eric Norum1-1/+1
2006-01-29Add code to maintain CPU load average.Eric Norum1-1/+4
2005-12-19Add another 'extended BSP' routine which returns reboot status register infor...Eric Norum1-0/+37
2005-11-07Assign copyright to OAR since all files descend from OAR's source.Eric Norum1-6/+2
2005-09-16Add bsp_reset bootrom call.Eric Norum1-0/+1
2005-07-06Enable CS1* and CS2* now that Arcturus bootstrap PROMs no longer take care of...Eric Norum1-0/+1
2005-05-24Try to maintain compatability with everyone else's VBR changes.Eric Norum1-5/+0
2005-05-11Followup fix to Joel's earlier _VBR changes.Eric Norum1-0/+5
2005-04-21Try insructioin-only cache.Eric Norum1-7/+19
2005-04-19Expose some read/write copies of configuration registers.Eric Norum1-22/+25
2005-04-10Set up IRQ1* handling properly.Eric Norum1-10/+11
2005-04-09FPGA interrupt status register is now 16-bit.Eric Norum1-3/+56
2005-03-10Add NOP after writing the CACR is there to address the issueEric Norum1-1/+24
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