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Adjust build support files to new directory layout.
This patch is a part of the BSP source reorganization.
Update #3285.
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Added register definition headers for STM32F4 ADC, EXTI, PWR, SYSCFG,
TIM, OTGFS and updated FLASH and RCC. Fixed PLL_Q for USB 48MHz
operation. Added flash prefetch enable.
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Added simple math to caclulate register values for the PLL
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
Also it will set latency on the Flash memory for the high speeds.
Limitations:
It is assumed that 1MHz resolution is enough.
Best fits for the clocks are achieved with multiplies of 42MHz.
Even though APB1, APB2 and AHB are calculated user is still required
to provide correct values for the bsp configuration for the:
STM32F4_PCLK1
STM32F4_PCLK2
STM32F4_HCLK (= system clock)
as those are used for the peripheral clocking calculations.
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