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* bsps/arm: Fix basic cache support for SMPSebastian Huber2016-07-051-8/+8
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* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-07-042-45/+69
| | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-07-041-0/+134
| | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support
* bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.Pavel Pisa2016-07-041-0/+4
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* bsps/arm: Support recent bootloaders starting kernel in HYP modePavel Pisa2016-07-045-7/+175
| | | | | | | | | | | | | | | | | | | When HYP mode is detected at startup then setup HYP mode vectors table (for future extensions) clean exceptions switching to HYP mode and switch CPU to ARM SVC mode. BSPs which want to use this support need to include next option in their configure.ac RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") and need to include next lines in corresponding Makefile.am if BSP_START_IN_HYP_SUPPORT libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S endif
* score: Fix SMP message handlingSebastian Huber2016-06-291-1/+0
| | | | | | | | According to the C11 standard only atomic read-modify-write operations guarantee that the last value written in modification order is read, see "7.17.3 Order and consistency". Thus we must use a read-modify-write in _SMP_Inter_processor_interrupt_handler() to make sure we read an up-to-date message.
* bsps: Include missing <rtems/bspIo.h>Sebastian Huber2016-06-241-0/+2
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* bsps: Add CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSORSebastian Huber2016-06-141-2/+2
| | | | | | | | | Add CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR clock driver option. If defined, then do the clock tick processing on the boot processor on behalf of all other processors. Currently, this is intended as a workaround for a Qemu shortcoming on ARM. Update #2737.
* bsps: Add defines for some linker subsectionsSebastian Huber2016-05-311-1/+7
| | | | The GNU ld sort by name or alignment needs distinct input sections.
* bsps: Sort some sections first by alignmentSebastian Huber2016-05-311-3/+3
| | | | | This helps to avoid alignment padding and thus may reduce some memory waste.
* score: Distribute clock tick to all online CPUsSebastian Huber2016-03-043-9/+82
| | | | Update #2554.
* arm: Use DWT CYCCNT for timecounter if availableSebastian Huber2016-01-211-15/+47
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* bsp/atsam: NewSebastian Huber2016-01-192-0/+183
| | | | Close #2529.
* bsps/arm: Copy vector table only if necessarySebastian Huber2016-01-191-5/+7
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* bsps/arm: Use common ARMv7-M bsp_reset()Sebastian Huber2016-01-191-0/+38
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* bsps/arm: Update CMSIS/IncludeSebastian Huber2016-01-1917-0/+22144
| | | | Remove duplicate and outdated files.
* score: Fix simple timecounter supportSebastian Huber2016-01-191-14/+37
| | | | Update #2502.
* bsps/arm: Fix broken switch statementSebastian Huber2016-01-181-3/+4
| | | | Update #2530.
* bsps: Generalize .nocacheheap to .nocachenoloadSebastian Huber2015-10-283-3/+13
| | | | Add ability to place data in a non-loadable cache-inhibited area.
* basdefs.h: Add and use RTEMS_UNUSEDSebastian Huber2015-10-261-3/+3
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* bsps/arm: Add missing translation table entrySebastian Huber2015-10-141-0/+4
| | | | See also bc820946793426dbdc450dc8bba4a15d01006182.
* bsps: Add .nocacheheap sectionSebastian Huber2015-10-082-11/+14
| | | | | This avoids consumption of a loadable address space for the nocache heap.
* SMP: Fix and optimize thread dispatchingSebastian Huber2015-09-281-1/+2
| | | | | | | | According to the C11 and C++11 memory models only a read-modify-write operation guarantees that we read the last value written in modification order. Avoid the sequential consistent thread fence and instead use the inter-processor interrupt to set the thread dispatch necessary indicator.
* bsps/arm: Fix function definitionSebastian Huber2015-09-041-1/+1
| | | | Close #2385.
* bsps/arm: Do not use __ARM_ARCH_7A__Sebastian Huber2015-07-311-28/+16
| | | | | This would lead to link-time errors in case less specialized compiler machine options are used, e.g. to run the GCC test suite.
* bsps/arm: Update due to API changesSebastian Huber2015-07-211-4/+4
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* bsps/arm: Update due to API changesSebastian Huber2015-06-261-2/+2
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* arm/shared/lpc/clock/lpc-clock-config.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* bsps: Convert clock drivers to use a timecounterAlexander Krutwig2015-05-203-75/+75
| | | | Update #2271.
* ARM: Add BSP_START_NEEDS_REGISTER_INITIALIZATIONMartin Galvan2015-02-272-0/+133
| | | | | | | | | | | | | This patch adds the macro BSP_START_NEEDS_REGISTER_INITIALIZATION and three hooks for BSP-specific register init code to arm/shared/start.S. Said hooks are bsp_start_init_registers_core (intended for initializing the ARM core registers), bsp_start_init_registers_banked_fiq (for the FIQ mode banked registers) and bsp_start_init_registers_vfp (for the FPU registers). BSP_START_NEEDS_REGISTER_INITIALIZATION would be defined in a BSP's configure.ac (so that it appears in its bspopts.h). This patch also adds the register init code required by the TMS570. We've tested it with the tms570ls3137_hdk.cfg config and it works fine.
* ARM: Support VFP-D16Martin Galvan2015-02-201-3/+5
| | | | | | | | | This patch allows the existing FPU code to support both VFP-D16 and VFP-D32. According to ARM, writes to D32DIS are ignored for D16 so there's no need to enclose the bic instruction with an #ifdef. We tested it on a TMS570LS3137 using TI initialization code and it works fine. Signed-off by: Martin Galvan <martin.galvan@tallertechnologies.com>
* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-171-0/+5
| | | | Update #2268.
* bsps/arm: Add .nocache sectionSebastian Huber2014-11-273-1/+30
| | | | | This section can be use to provide a cache coherent memory area via rtems_cache_coherent_add_area().
* bsps/arm: L2C 310 avoid infinite loopsSebastian Huber2014-11-251-0/+8
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* bsps/arm: Enable L2C for Cortex-A9 MPCore BSPsSebastian Huber2014-11-201-9/+9
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* bsps/arm: L2C 310 drop exclusive cache supportSebastian Huber2014-11-201-71/+50
| | | | Optimize locking.
* bsps/arm: L1 cache support changesSebastian Huber2014-11-201-16/+21
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* bsps/arm: L2C 310 compile-time errata 588369Sebastian Huber2014-11-201-49/+19
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* bsps/arm: L2C 310 compile-time errata 753970Sebastian Huber2014-11-201-71/+43
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* bsps/arm: L2C 310 exclusive config is fatalSebastian Huber2014-11-201-7/+16
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* bsps/arm: L2C 310 use l2c_310_* prefix throughoutSebastian Huber2014-11-201-99/+99
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* bsps/arm: L2C 310 use L2C_310_* prefix throughoutSebastian Huber2014-11-201-232/+232
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* bsps/arm: L2C 310 add compile time checksSebastian Huber2014-11-201-81/+68
| | | | Simplify initialization. Replace some assert() with fatal errors.
* bsps/arm: L2C 310 delete invalid linkSebastian Huber2014-11-201-2/+0
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* bsps/arm: L2C 310 simplify and remove white spaceSebastian Huber2014-11-201-292/+177
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* bsps/arm: L2C 310 rename BSP_ARM_L2CC_BASESebastian Huber2014-11-201-26/+26
| | | | Rename BSP_ARM_L2CC_BASE to BSP_ARM_L2C_310_BASE.
* bsps/arm: Adjust stacks for ARMv4Sebastian Huber2014-11-202-19/+7
| | | | | | | | Reduce non-IRQ stacks to size zero. All non-IRQ stacks overlap now the IRQ stack. This is all right since the SVC stack is used only during startup and here interrupts are disabled. The other exception stacks lead to a system termination by default, so we can here also use the IRQ stack since interrupts are disabled on exception entry.
* ARM removed shared/abort from several ARM BSPsAlan Cudmore2014-11-203-50/+55
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* bsps/arm: Convert PL011 and PL050 console driversSebastian Huber2014-10-144-110/+98
| | | | Use Termios device API.
* bsps/arm: Move abort stackSebastian Huber2014-10-131-4/+4
| | | | | Move abort stack above the other exception stacks to use them just in case.
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