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* score: Rename _SMP_Get_processor_count()Sebastian Huber2019-04-111-9/+9
| | | | | | | Rename _SMP_Get_processor_count() in _SMP_Get_processor_maximum() to be in line with the API level rtems_scheduler_get_processor_maximum(). Update #3732.
* rtems: Add rtems_scheduler_get_processor_maximum()Sebastian Huber2019-04-092-3/+3
| | | | | | | | | | | Add rtems_scheduler_get_processor_maximum() as a replacement for rtems_get_processor_count(). The rtems_get_processor_count() is a bit orphaned. Adopt it by the Scheduler Manager. The count is also misleading, since the processor set may have gaps and the actual count of online processors may be less than the value returned by rtems_get_processor_count(). Update #3732.
* bsps: Adjust shared Doxygen groupsSebastian Huber2019-03-082-2/+10
| | | | Update #3706.
* bsps: Adjust bsp.h Doxygen groupsSebastian Huber2019-03-083-3/+57
| | | | Update #3706.
* bsps: Adjust architecture Doxygen groupsSebastian Huber2019-03-041-0/+7
| | | | | | | | | | - Use CamelCase as it is not used in our C code. Enables simple search and replace. - Prefix with "RTEMS" to aid deployment and integration. It aids searching and sorting. Update #3706.
* griscv: add additional cpu configurationsJiri Gaisler2019-02-085-1/+37
| | | | | * Also switch default config to imafd as the C extension is not supported for code coverage
* riscv: add griscv bspJiri Gaisler2019-01-2219-0/+1315
| | | | Update #3678.
* bsp/riscv: Clear boot command lineSebastian Huber2019-01-081-0/+1
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* score: Rename interrupt stack symbolsSebastian Huber2018-11-081-3/+3
| | | | | | | | | | | | | Rename * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin, * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and * _Configuration_Interrupt_stack_size in _ISR_Stack_size. Move definitions to <rtems/score/isr.h>. The new names are considerable shorter and in the right namespace. Update #3459.
* riscv: Allow platforms with no PLIC to proceedHesham Almatary2018-09-171-0/+5
| | | | Spike simulator and QEMU's spike_v1.10 don't have a PLIC
* bsp/riscv: Add missing BSP variantSebastian Huber2018-08-021-0/+9
| | | | Update #3433.
* bsp/riscv: Fix build with RTEMS_SMP undefinedSebastian Huber2018-08-023-12/+10
| | | | Update #3433.
* bsp/riscv: Fix a synchronization issue for PLICSebastian Huber2018-08-021-0/+8
| | | | Update #3433.
* bsp/riscv: Remove unused variableSebastian Huber2018-08-011-4/+0
| | | | Update #3433.
* bsp/riscv: Add NS16750 support to console driverSebastian Huber2018-08-011-36/+74
| | | | Update #3433.
* bsp/riscv: Initialize FPU depending on ISASebastian Huber2018-08-011-1/+4
| | | | | | Initialize fcsr to zero for a defined rounding mode. Update #3433.
* bsp/riscv: Fix clock driverSebastian Huber2018-08-011-17/+49
| | | | | | Do not assume that mtime is zero at boot time. Update #3433.
* bsp/riscv: Fix inter-processor interruptsSebastian Huber2018-07-271-1/+7
| | | | | | | | The previous version worked only on a patched Qemu. Writes to mip are illegal according to the The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Privileged Architecture Version 1.10. Update #3433.
* riscv: Rework CPU counter supportSebastian Huber2018-07-271-4/+18
| | | | Update #3433.
* bsp/riscv: Use interrupt driven NS16550 driverSebastian Huber2018-07-251-1/+9
| | | | Update #3433.
* bsp/riscv: Add PLIC supportSebastian Huber2018-07-254-2/+258
| | | | Update #3433.
* bsp/riscv: Add simple SMP support to clock driverSebastian Huber2018-07-251-0/+2
| | | | | | This is a hack. The clock interrupt should be handled by each hart. Update #3433.
* bsp/riscv: Use CPU counter btimerSebastian Huber2018-07-251-68/+0
| | | | Update #3433.
* bsp/riscv: Add basic SMP startupSebastian Huber2018-07-256-26/+295
| | | | Update #3433.
* riscv: Add CLINT and PLIC supportSebastian Huber2018-07-253-62/+4
| | | | | | The CLINT and PLIC need some per-processor state. Update #3433.
* bsps/riscv: Update linker-symbols.hSebastian Huber2018-07-251-15/+16
| | | | Update #3433.
* bsp/riscv: Add reset via for SiFive Test FinisherSebastian Huber2018-07-251-5/+18
| | | | Update #3433.
* bsp/riscv: Add and use riscv_fdt_get_address()Sebastian Huber2018-07-254-24/+79
| | | | Update #3433.
* bsp/riscv: Fix HTIF warningsSebastian Huber2018-07-255-5/+62
| | | | Update #3433.
* riscv: Rework exception handlingSebastian Huber2018-07-257-51/+86
| | | | | | | | | | | Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
* bsp/riscv: Add console support for NS16550 devicesSebastian Huber2018-07-061-0/+100
| | | | Update #3433.
* bsp/riscv: Simplify printk() supportSebastian Huber2018-07-063-19/+16
| | | | | | | This is a prepartion to add NS16550 driver support to the console driver. Update #3433.
* riscv: Add LADDR assembler defineSebastian Huber2018-07-061-8/+8
| | | | | | | An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
* riscv: Implement CPU counterSebastian Huber2018-07-061-10/+2
| | | | Update #3433.
* bsps: Update headers.amSebastian Huber2018-07-051-0/+8
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* riscv: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2018-06-281-1/+5
| | | | Update #3433.
* riscv: Avoid namespace pollutionSebastian Huber2018-06-281-0/+1
| | | | | | | Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h> (which is visible via <rtems.h> for example). Update #3433.
* bsp/riscv: Remove bsp_interrupt_handler_default()Sebastian Huber2018-06-281-9/+0
| | | | | | It duplicated the default implementation. Update #3433.
* bsp/riscv: Rework clock driverSebastian Huber2018-06-283-63/+120
| | | | | | | Use device tree provided timebase frequency. Do not write to read-only mtime register. Update #3433.
* bsp/riscv: Add device tree support for consoleSebastian Huber2018-06-283-60/+215
| | | | Update #3433.
* bsp/riscv: Fix vector table for lp64Sebastian Huber2018-06-281-16/+22
| | | | Update #3433.
* bsp/riscv: Add SMP startup synchronizationSebastian Huber2018-06-281-2/+20
| | | | Update #3433.
* bsp/riscv: Add device tree supportSebastian Huber2018-06-282-6/+14
| | | | Update #3433.
* riscv: Add dummy SMP supportSebastian Huber2018-06-281-0/+10
| | | | Update #3433.
* bsp/riscv: Load global pointerSebastian Huber2018-06-271-0/+6
| | | | Update #3433.
* bsp/riscv: Use memset() to clear .bssSebastian Huber2018-06-271-10/+5
| | | | Update #3433.
* riscv: Format assembler filesSebastian Huber2018-06-271-33/+36
| | | | | | Use tabs to match the GCC generated assembler output. Update #3433.
* bsp/riscv: Do not clear integer registers at startSebastian Huber2018-06-271-31/+0
| | | | | | There is no need to do this. Update #3433.
* bsp/riscv: Fix some warningsSebastian Huber2018-06-271-20/+4
| | | | Update #3444.
* bsp/riscv: Add BSP options to define RAM regionSebastian Huber2018-06-271-1/+1
| | | | Update #3433.
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