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authorSebastian Huber <sebastian.huber@embedded-brains.de>2018-08-02 14:13:25 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-08-02 14:13:25 +0200
commit4c740de6e2e1e5235abc2756fb6b325e640dde48 (patch)
treeddcc6c488cdbd260439858c373b42d2e2986be39 /bsps/riscv
parentriscv: Fix CPU_ALIGNMENT (diff)
downloadrtems-4c740de6e2e1e5235abc2756fb6b325e640dde48.tar.bz2
bsp/riscv: Fix build with RTEMS_SMP undefined
Update #3433.
Diffstat (limited to 'bsps/riscv')
-rw-r--r--bsps/riscv/riscv/include/bsp/riscv.h6
-rw-r--r--bsps/riscv/riscv/irq/irq.c4
-rw-r--r--bsps/riscv/riscv/start/bspstart.c12
3 files changed, 10 insertions, 12 deletions
diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h
index 6701bb6cc6..374d5f7a77 100644
--- a/bsps/riscv/riscv/include/bsp/riscv.h
+++ b/bsps/riscv/riscv/include/bsp/riscv.h
@@ -40,11 +40,11 @@ void *riscv_fdt_get_address(const void *fdt, int node);
#ifdef RTEMS_SMP
extern uint32_t riscv_hart_count;
-
-extern uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS];
+#else
+#define riscv_hart_count 1
+#endif
uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle);
-#endif
#if RISCV_ENABLE_HTIF_SUPPORT != 0
void htif_poweroff(void);
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index ea33a3239c..1a768464d4 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -116,11 +116,9 @@ static void riscv_clint_init(const void *fdt)
{
volatile RISCV_CLINT_regs *clint;
int node;
-#ifdef RTEMS_SMP
const uint32_t *val;
int len;
int i;
-#endif
node = fdt_node_offset_by_compatible(fdt, -1, "riscv,clint0");
@@ -131,7 +129,6 @@ static void riscv_clint_init(const void *fdt)
riscv_clint = clint;
-#ifdef RTEMS_SMP
val = fdt_getprop(fdt, node, "interrupts-extended", &len);
for (i = 0; i < len; i += 16) {
@@ -147,7 +144,6 @@ static void riscv_clint_init(const void *fdt)
cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16];
cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16];
}
-#endif
}
static void riscv_plic_init(const void *fdt)
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c
index 2cb453f125..d4c4e1ff7f 100644
--- a/bsps/riscv/riscv/start/bspstart.c
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -74,7 +74,10 @@ void *riscv_fdt_get_address(const void *fdt, int node)
#ifdef RTEMS_SMP
uint32_t riscv_hart_count;
-uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS];
+static uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS];
+#else
+static uint32_t riscv_hart_phandles[1];
+#endif
static void riscv_find_harts(void)
{
@@ -100,7 +103,7 @@ static void riscv_find_harts(void)
hart_index = fdt32_to_cpu(val[0]);
- if (hart_index >= CPU_MAXIMUM_PROCESSORS) {
+ if (hart_index >= RTEMS_ARRAY_SIZE(riscv_hart_phandles)) {
continue;
}
@@ -140,7 +143,9 @@ static void riscv_find_harts(void)
riscv_hart_phandles[hart_index] = phandle;
}
+#ifdef RTEMS_SMP
riscv_hart_count = max_hart_index + 1;
+#endif
}
uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
@@ -155,12 +160,9 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
return UINT32_MAX;
}
-#endif
void bsp_start(void)
{
-#ifdef RTEMS_SMP
riscv_find_harts();
-#endif
bsp_interrupt_initialize();
}