riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions.  Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

7 files changed, 86 insertions, 51 deletions

diff --git a/bsps/riscv/include/bsp/linker-symbols.h b/bsps/riscv/include/bsp/linker-symbols.h
index 34bf4873ba..426b17451f 100644
--- a/bsps/riscv/include/bsp/linker-symbols.h
+++ b/bsps/riscv/include/bsp/linker-symbols.h
@@ -63,10 +63,6 @@ LINKER_SYMBOL(bsp_vector_table_begin)
 LINKER_SYMBOL(bsp_vector_table_end)
 LINKER_SYMBOL(bsp_vector_table_size)
 
-LINKER_SYMBOL(bsp_start_vector_table_begin)
-LINKER_SYMBOL(bsp_start_vector_table_end)
-LINKER_SYMBOL(bsp_start_vector_table_size)
-
 LINKER_SYMBOL(bsp_translation_table_base)
 LINKER_SYMBOL(bsp_translation_table_end)
 
diff --git a/bsps/riscv/riscv/btimer/btimer.c b/bsps/riscv/riscv/btimer/btimer.c
index 4dd3193685..796979fbb2 100644
--- a/bsps/riscv/riscv/btimer/btimer.c
+++ b/bsps/riscv/riscv/btimer/btimer.c
@@ -29,8 +29,6 @@
 #include <rtems/btimer.h>
 #include <rtems/score/riscv-utility.h>
 
-extern char bsp_start_vector_table_begin[];
-
 bool benchmark_timer_find_average_overhead;
 
 static void benchmark_timer1_interrupt_handler(void)
diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c
index d2d7a406a0..52fb441ce1 100644
--- a/bsps/riscv/riscv/clock/clockdrv.c
+++ b/bsps/riscv/riscv/clock/clockdrv.c
@@ -72,11 +72,20 @@ static void riscv_clock_at_tick(void)
 #endif
 }
 
-static void riscv_clock_handler_install(proc_ptr new_isr)
+static void riscv_clock_handler_install(void)
 {
-  _CPU_ISR_install_vector(RISCV_MACHINE_TIMER_INTERRUPT,
-                          new_isr,
-                          NULL);
+  rtems_status_code sc;
+
+  sc = rtems_interrupt_handler_install(
+    RISCV_INTERRUPT_VECTOR_TIMER,
+    "Clock",
+    RTEMS_INTERRUPT_UNIQUE,
+    (rtems_interrupt_handler) Clock_isr,
+    NULL
+  );
+  if (sc != RTEMS_SUCCESSFUL) {
+    bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL);
+  }
 }
 
 static uint32_t riscv_clock_get_timecount(struct timecounter *tc)
@@ -136,6 +145,6 @@ uint32_t _CPU_Counter_frequency( void )
 #define Clock_driver_support_initialize_hardware() riscv_clock_initialize()
 
 #define Clock_driver_support_install_isr(isr) \
-  riscv_clock_handler_install(isr)
+  riscv_clock_handler_install()
 
 #include "../../../shared/dev/clock/clockimpl.h"
diff --git a/bsps/riscv/riscv/include/bsp/irq.h b/bsps/riscv/riscv/include/bsp/irq.h
index d7ee45b378..353005fadf 100644
--- a/bsps/riscv/riscv/include/bsp/irq.h
+++ b/bsps/riscv/riscv/include/bsp/irq.h
@@ -7,6 +7,7 @@
  */
 
 /*
+ * Copyright (c) 2018 embedded brains GmbH
  *
  * Copyright (c) 2015 University of York.
  * Hesham Almatary <hesham@alumni.york.ac.uk>
@@ -38,12 +39,20 @@
 
 #ifndef ASM
 
-#include <rtems.h>
+#include <bsp.h>
 #include <rtems/irq.h>
 #include <rtems/irq-extension.h>
 
-#define BSP_INTERRUPT_VECTOR_MIN  0x0
-#define BSP_INTERRUPT_VECTOR_MAX  0x24
+#define RISCV_INTERRUPT_VECTOR_SOFTWARE 0
+
+#define RISCV_INTERRUPT_VECTOR_TIMER 1
+
+#define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2)
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+#define BSP_INTERRUPT_VECTOR_MAX RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1)
 
 #endif /* ASM */
+
 #endif /* LIBBSP_GENERIC_RISCV_IRQ_H */
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index ac4f1ca115..61cf13153b 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -7,7 +7,7 @@
  */
 
 /*
- * RISCV CPU Dependent Source
+ * Copyright (c) 2018 embedded brains GmbH
  *
  * Copyright (c) 2015 University of York.
  * Hesham Almatary <hesham@alumni.york.ac.uk>
@@ -35,11 +35,33 @@
  */
 
 #include <bsp/irq.h>
+#include <bsp/fatal.h>
 #include <bsp/irq-generic.h>
 
-rtems_status_code bsp_interrupt_facility_initialize()
+#include <rtems/score/percpu.h>
+
+void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
+{
+  /*
+   * Get rid of the most significant bit which indicates if the exception was
+   * caused by an interrupt or not.
+   */
+  mcause <<= 1;
+
+  if (mcause == (RISCV_INTERRUPT_TIMER_MACHINE << 1)) {
+    bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_TIMER);
+  } else if (mcause == (RISCV_INTERRUPT_EXTERNAL_MACHINE << 1)) {
+    /* TODO: Handle PLIC interrupt */
+  } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
+    bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
+  } else {
+    bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION);
+  }
+}
+
+rtems_status_code bsp_interrupt_facility_initialize(void)
 {
-  return RTEMS_NOT_IMPLEMENTED;
+  return RTEMS_SUCCESSFUL;
 }
 
 void bsp_interrupt_vector_enable(rtems_vector_number vector)
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c
new file mode 100644
index 0000000000..217e6f23a6
--- /dev/null
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018 embedded brains GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <bsp/bootcard.h>
+#include <bsp/irq-generic.h>
+
+void bsp_start(void)
+{
+  bsp_interrupt_initialize();
+}
diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S
index 0dad170c3c..83926a9272 100644
--- a/bsps/riscv/riscv/start/start.S
+++ b/bsps/riscv/riscv/start/start.S
@@ -1,4 +1,6 @@
 /*
+ * Copyright (c) 2018 embedded brains GmbH
+
  * Copyright (c) 2015 University of York.
  * Hesham Almatary <hesham@alumni.york.ac.uk>
  *
@@ -33,13 +35,6 @@
 #include <bsp/linker-symbols.h>
 #include <bspopts.h>
 
-EXTERN(bsp_section_bss_begin)
-EXTERN(bsp_section_bss_end)
-EXTERN(ISR_Handler)
-EXTERN(bsp_section_stack_begin)
-
-PUBLIC(bsp_start_vector_table_begin)
-PUBLIC(bsp_start_vector_table_end)
 PUBLIC(_start)
 
 	.section	.bsp_start_text, "wax", @progbits
@@ -70,7 +65,7 @@ SYM(_start):
 	call	bsp_fdt_copy
 #endif
 
-	LADDR	t0, ISR_Handler
+	LADDR	t0, _RISCV_Exception_handler
 	csrw	mtvec, t0
 
 	/* Clear .bss */
@@ -107,29 +102,3 @@ SYM(_start):
 .Lsecondary_processor_go:
 	.word	0xdeadbeef
 #endif
-
-#if __riscv_xlen == 32
-#define ADDR .word
-#elif __riscv_xlen == 64
-#define ADDR .quad
-#endif
-
-	.align	4
-bsp_start_vector_table_begin:
-	ADDR	_RISCV_Exception_default /* User int */
-	ADDR	_RISCV_Exception_default /* Supervisor int */
-	ADDR	_RISCV_Exception_default /* Reserved */
-	ADDR	_RISCV_Exception_default /* Machine int */
-	ADDR	_RISCV_Exception_default /* User timer int */
-	ADDR	_RISCV_Exception_default /* Supervisor Timer int */
-	ADDR	_RISCV_Exception_default /* Reserved */
-	ADDR	_RISCV_Exception_default /* Machine Timer int */
-	ADDR	_RISCV_Exception_default /* User external int */
-	ADDR	_RISCV_Exception_default /* Supervisor external int */
-	ADDR	_RISCV_Exception_default /* Reserved */
-	ADDR	_RISCV_Exception_default /* Machine external int */
-	ADDR	_RISCV_Exception_default
-	ADDR	_RISCV_Exception_default
-	ADDR	_RISCV_Exception_default
-	ADDR	_RISCV_Exception_default
-bsp_start_vector_table_end: