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path: root/bsps/riscv/riscv/irq/irq.c (unfollow)
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2024-03-27bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber1-1/+0
2023-05-20Update company nameSebastian Huber1-1/+1
2023-01-12riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber1-7/+11
2022-12-23RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORTHesham Almatary1-6/+9
2022-11-23bsps/riscv: Simplify PLIC supportSebastian Huber1-28/+30
2022-11-23bsps/riscv: Fix PLIC enable register countSebastian Huber1-3/+5
2022-11-23bsps/riscv: Add riscv_plic_cpu_0_init()Sebastian Huber1-13/+23
2022-11-11bsps/riscv: Fix software interrupt dispatchingSebastian Huber1-2/+4
2022-11-10bsps/riscv: Fix PLIC enable register countSebastian Huber1-2/+2
2022-11-10bsps/riscv: Skip init on not configured processorsSebastian Huber1-0/+11
2022-11-10bsps/riscv: Simplify riscv_plic_init()Sebastian Huber1-30/+39
2022-11-10bsps/riscv: Simplify riscv_clint_init()Sebastian Huber1-14/+25
2022-11-10bsps/riscv: Always dispatch software interruptsSebastian Huber1-3/+2
2022-11-10bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber1-13/+6
2022-11-10bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber1-4/+20
2022-11-10bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber1-2/+25
2022-11-10bsps/riscv: bsp_interrupt_get_attributes()Sebastian Huber1-0/+15
2022-11-10bsps/riscv: Improve bsp_interrupt_vector_disable()Sebastian Huber1-0/+8
2022-11-10bsps/riscv: Improve bsp_interrupt_vector_enable()Sebastian Huber1-0/+8
2022-11-10bsps/riscv: bsp_interrupt_vector_is_enabled()Sebastian Huber1-2/+47
2022-11-10bsps/riscv: bsp_interrupt_is_valid_vector()Sebastian Huber1-1/+16
2022-09-20bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari1-0/+81
2021-07-27bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber1-3/+1
2021-07-26bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber1-3/+5
2021-07-26bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber1-1/+3
2021-07-26bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber1-1/+3
2021-07-26bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber1-1/+3
2021-07-26bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber1-0/+11
2021-07-26bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber1-0/+8
2021-07-26bsps/irq: Add rtems_interrupt_raise()Sebastian Huber1-0/+23
2021-07-26bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber1-0/+11
2019-04-11score: Rename _SMP_Get_processor_count()Sebastian Huber1-9/+9
2018-09-17riscv: Allow platforms with no PLIC to proceedHesham Almatary1-0/+5
2018-08-02bsp/riscv: Fix build with RTEMS_SMP undefinedSebastian Huber1-4/+0
2018-08-02bsp/riscv: Fix a synchronization issue for PLICSebastian Huber1-0/+8
2018-08-01bsp/riscv: Remove unused variableSebastian Huber1-4/+0
2018-07-27bsp/riscv: Fix inter-processor interruptsSebastian Huber1-1/+7
2018-07-25bsp/riscv: Add PLIC supportSebastian Huber1-1/+240
2018-07-25bsp/riscv: Add basic SMP startupSebastian Huber1-0/+56
2018-07-25riscv: Rework exception handlingSebastian Huber1-3/+25
2018-06-28bsp/riscv: Remove bsp_interrupt_handler_default()Sebastian Huber1-9/+0
2018-06-27bsp/riscv_generic: Rename to "riscv"Sebastian Huber1-0/+0
2018-04-23bsps: Move interrupt controller support to bspsSebastian Huber1-0/+0
2018-03-27bsps/riscv: Fix warningsSebastian Huber1-6/+1
2017-11-01bsp: Make riscv_generic work for both riscv32 and riscv64 - v2Hesham Almatary1-0/+0
2017-10-28bsp: Add new riscv_generic bsp v3Hesham Almatary1-8/+9
2017-06-20bsps: Improve interrupt vector enable/disable APISebastian Huber1-4/+4
2017-04-25rtems/inttypes.h epiphany_sim/irq/irq.c: Add PRIdrtems_vector_number and use itJoel Sherrill1-1/+3
2015-05-21Epiphany: Add the first epiphany_sim BSP v4Hesham ALMatary1-30/+24
2015-05-21cpukit: Add Epiphany architecture port v4Hesham ALMatary1-12/+39
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