summaryrefslogtreecommitdiffstats
path: root/bsps/riscv/riscv (unfollow)
Commit message (Expand)AuthorFilesLines
2024-03-27bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber2-14/+0
2024-03-20bsps: Avoid unused argument in clock interruptSebastian Huber1-8/+5
2023-05-20Update company nameSebastian Huber10-10/+10
2023-03-28bsps/riscv: add riscv/kendrytek210 BSP variant source changesAlan Cudmore7-6/+171
2023-03-28bsps/riscv: add device tree source and device tree blob header for k210 bsp v...Alan Cudmore2-0/+531
2023-03-17bsps/riscv: Use per-CPU mtimecmp in clock driverSebastian Huber1-26/+15
2023-03-17bsps/riscv: Fix riscv_get_hart_index_by_phandle()Sebastian Huber2-2/+10
2023-03-17bsps/riscv: Make SMP start more robustSebastian Huber1-4/+1
2023-01-24clockdrv: Add clock driver implementation groupSebastian Huber1-2/+3
2023-01-24tm27: Avoid function pointer castsSebastian Huber1-4/+2
2023-01-12riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber5-10/+30
2022-12-23RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORTHesham Almatary5-24/+18
2022-12-02bsps/irq: Rename handler in dispatch tableSebastian Huber1-2/+2
2022-11-23bsps/riscv: Simplify PLIC supportSebastian Huber1-28/+30
2022-11-23bsps/riscv: Fix PLIC enable register countSebastian Huber1-3/+5
2022-11-23bsps/riscv: Add riscv_plic_cpu_0_init()Sebastian Huber1-13/+23
2022-11-23bsps/riscv: Fix bsp_fdt_map_intr()Sebastian Huber1-1/+1
2022-11-11bsps/riscv: Fix software interrupt dispatchingSebastian Huber1-2/+4
2022-11-10bsps/riscv: Fix PLIC enable register countSebastian Huber1-2/+2
2022-11-10bsps/riscv: Skip init on not configured processorsSebastian Huber1-0/+11
2022-11-10bsps/riscv: Simplify riscv_plic_init()Sebastian Huber1-30/+39
2022-11-10bsps/riscv: Simplify riscv_clint_init()Sebastian Huber1-14/+25
2022-11-10bsps/riscv: Add tm27 supportSebastian Huber1-1/+136
2022-11-10bsps/riscv: Always dispatch software interruptsSebastian Huber1-3/+2
2022-11-10bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber1-13/+6
2022-11-10bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber1-4/+20
2022-11-10bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber1-2/+25
2022-11-10bsps/riscv: bsp_interrupt_get_attributes()Sebastian Huber1-0/+15
2022-11-10bsps/riscv: Improve bsp_interrupt_vector_disable()Sebastian Huber1-0/+8
2022-11-10bsps/riscv: Improve bsp_interrupt_vector_enable()Sebastian Huber1-0/+8
2022-11-10bsps/riscv: bsp_interrupt_vector_is_enabled()Sebastian Huber1-2/+47
2022-11-10bsps/riscv: bsp_interrupt_is_valid_vector()Sebastian Huber2-1/+18
2022-10-14bsps: Improve riscv console FDT parsingAlan Cudmore1-9/+5
2022-10-14riscv: Move functions to avoid build issuesSebastian Huber1-10/+0
2022-09-20bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari7-4/+130
2022-09-20bsps/riscv: Add device tree blobPadmarao Begari2-0/+967
2022-09-19bsps/riscv/riscv: Fix fe310_uart_readAlan Cudmore1-2/+5
2022-09-06bsp/riscv: Add NOEL-V BSPMartin Aberg2-0/+4
2022-02-25bsps/riscv: Add missing includeSebastian Huber1-0/+1
2021-11-29bsp_specs: Delete last remnants of these.Joel Sherrill1-0/+0
2021-09-21build: Remove old build systemSebastian Huber2-62/+0
2021-07-28score: Canonicalize _CPU_Fatal_halt()Sebastian Huber1-1/+2
2021-07-27bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber1-3/+1
2021-07-26bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2-4/+6
2021-07-26bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2-2/+4
2021-07-26bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber1-1/+3
2021-07-26bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber1-1/+3
2021-07-26bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber1-0/+11
2021-07-26bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber1-0/+8
2021-07-26bsps/irq: Add rtems_interrupt_raise()Sebastian Huber1-0/+23
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-10 15:01:39 +0000