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* bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber2024-03-271-1/+0
* Update company nameSebastian Huber2023-05-201-1/+1
* riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber2023-01-121-7/+11
* RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORTHesham Almatary2022-12-231-6/+9
* bsps/riscv: Simplify PLIC supportSebastian Huber2022-11-231-28/+30
* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-231-3/+5
* bsps/riscv: Add riscv_plic_cpu_0_init()Sebastian Huber2022-11-231-13/+23
* bsps/riscv: Fix software interrupt dispatchingSebastian Huber2022-11-111-2/+4
* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-101-2/+2
* bsps/riscv: Skip init on not configured processorsSebastian Huber2022-11-101-0/+11
* bsps/riscv: Simplify riscv_plic_init()Sebastian Huber2022-11-101-30/+39
* bsps/riscv: Simplify riscv_clint_init()Sebastian Huber2022-11-101-14/+25
* bsps/riscv: Always dispatch software interruptsSebastian Huber2022-11-101-3/+2
* bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber2022-11-101-13/+6
* bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber2022-11-101-4/+20
* bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber2022-11-101-2/+25
* bsps/riscv: bsp_interrupt_get_attributes()Sebastian Huber2022-11-101-0/+15
* bsps/riscv: Improve bsp_interrupt_vector_disable()Sebastian Huber2022-11-101-0/+8
* bsps/riscv: Improve bsp_interrupt_vector_enable()Sebastian Huber2022-11-101-0/+8
* bsps/riscv: bsp_interrupt_vector_is_enabled()Sebastian Huber2022-11-101-2/+47
* bsps/riscv: bsp_interrupt_is_valid_vector()Sebastian Huber2022-11-101-1/+16
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-201-0/+81
* bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber2021-07-271-3/+1
* bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2021-07-261-3/+5
* bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2021-07-261-1/+3
* bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber2021-07-261-1/+3
* bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber2021-07-261-1/+3
* bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber2021-07-261-0/+11
* bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber2021-07-261-0/+8
* bsps/irq: Add rtems_interrupt_raise()Sebastian Huber2021-07-261-0/+23
* bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber2021-07-261-0/+11
* score: Rename _SMP_Get_processor_count()Sebastian Huber2019-04-111-9/+9
* riscv: Allow platforms with no PLIC to proceedHesham Almatary2018-09-171-0/+5
* bsp/riscv: Fix build with RTEMS_SMP undefinedSebastian Huber2018-08-021-4/+0
* bsp/riscv: Fix a synchronization issue for PLICSebastian Huber2018-08-021-0/+8
* bsp/riscv: Remove unused variableSebastian Huber2018-08-011-4/+0
* bsp/riscv: Fix inter-processor interruptsSebastian Huber2018-07-271-1/+7
* bsp/riscv: Add PLIC supportSebastian Huber2018-07-251-1/+240
* bsp/riscv: Add basic SMP startupSebastian Huber2018-07-251-0/+56
* riscv: Rework exception handlingSebastian Huber2018-07-251-3/+25
* bsp/riscv: Remove bsp_interrupt_handler_default()Sebastian Huber2018-06-281-9/+0
* bsp/riscv_generic: Rename to "riscv"Sebastian Huber2018-06-271-0/+60
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