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2024-03-20bsps: Avoid unused argument in clock interruptSebastian Huber1-8/+5
Pass the parameter of the clock interrupt handler to Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes it possible to use the interrupt handler argument in clock drivers. Use the interrupt handler provided by Clock_driver_support_install_isr() to avoid local delarations of Clock_isr(). Update #4862.
2023-05-20Update company nameSebastian Huber1-1/+1
The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2023-03-17bsps/riscv: Use per-CPU mtimecmp in clock driverSebastian Huber1-26/+15
Use the mtimecmp from the PLIC/CLINT initialization in the clock driver. This register is defined by the device tree and does not assume a fixed mapping.
2023-01-24clockdrv: Add clock driver implementation groupSebastian Huber1-2/+3
Use standard wording in Clock Driver related files. Update #3706.
2022-09-20bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari1-1/+5
The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
2022-02-25bsps/riscv: Add missing includeSebastian Huber1-0/+1
2021-03-23bsps/riscv: Add per cpu clock interruptJan Sommer1-10/+49
- Fixes failure of test smpclock01
2019-10-23riscv: add freedom E310 Arty A7 bspPragnesh Patel1-5/+11
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2019-01-22riscv: add griscv bspJiri Gaisler1-0/+5
Update #3678.
2018-08-01bsp/riscv: Fix clock driverSebastian Huber1-17/+49
Do not assume that mtime is zero at boot time. Update #3433.
2018-07-27riscv: Rework CPU counter supportSebastian Huber1-4/+18
Update #3433.
2018-07-25bsp/riscv: Add simple SMP support to clock driverSebastian Huber1-0/+2
This is a hack. The clock interrupt should be handled by each hart. Update #3433.
2018-07-25bsp/riscv: Add basic SMP startupSebastian Huber1-8/+2
Update #3433.
2018-07-25riscv: Add CLINT and PLIC supportSebastian Huber1-5/+4
The CLINT and PLIC need some per-processor state. Update #3433.
2018-07-25bsp/riscv: Add and use riscv_fdt_get_address()Sebastian Huber1-15/+31
Update #3433.
2018-07-25riscv: Rework exception handlingSebastian Huber1-5/+14
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
2018-07-06riscv: Implement CPU counterSebastian Huber1-10/+2
Update #3433.
2018-06-28riscv: Avoid namespace pollutionSebastian Huber1-0/+1
Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h> (which is visible via <rtems.h> for example). Update #3433.
2018-06-28bsp/riscv: Rework clock driverSebastian Huber1-41/+67
Use device tree provided timebase frequency. Do not write to read-only mtime register. Update #3433.
2018-06-27bsp/riscv_generic: Rename to "riscv"Sebastian Huber1-0/+0
Update #3433.
2018-06-27Remove Clock_driver_support_shutdown_hardware()Sebastian Huber1-9/+0
The aim of this clock driver hook was to stop clock tick interrupts at some late point in the exit() procedure. The use of atexit() pulls in malloc() which pulls in errno. It is incompatible with the intention of the CONFIGURE_DISABLE_NEWLIB_REENTRANCY configuration option. The exit() function must be called from thread context, so accompanied clock tick interrupts should cause no harm. On the contrary, someone may assume a normal operating system operation, e.g. working timeouts. Remove the Clock_driver_support_shutdown_hardware() clock driver hook. Close #3436.
2018-04-20bsps: Move clock drivers to bspsSebastian Huber1-1/+1
This patch is a part of the BSP source reorganization. Update #3285.
2017-11-01bsp: Make riscv_generic work for both riscv32 and riscv64 - v2Hesham Almatary1-0/+0
Update #3109
2017-10-28bsp: Add new riscv_generic bsp v3Hesham Almatary1-0/+131
* Only runs/tested on simulator/spike. * Ticker, hello, capture work proprely * Tested via RTEMS Tester, Passed: 525/565 (92%) Update #3109
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