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* aarch64/versal: Support DDRMC0 region 0 and 1Chris Johns2022-07-282-0/+58
| | | | | | | | | | | - Support DDRMC0 region 0 up to 2G in size - Support DDRMC0 region 1 with DDR memory greater than 2G up to the DDRMC0 max amount - Extend the heap with region 1's memory Closes #4684
* basp/aarch64: Make the unexpected sections origin address 64bitChris Johns2022-07-281-1/+1
| | | | Update #4684
* aarch64: Use page table level 0Kinsey Moore2022-07-212-15/+57
| | | | | | | | | This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
* aarch64: Memory map the noinit sectionKinsey Moore2022-07-182-0/+8
| | | | | This section was added recently and must be mapped to be accessed without generating an exception.
* bsps: Sort .noinit* sectionsSebastian Huber2022-07-151-1/+1
| | | | | | | | Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
* bsps/aarch64: Use MMU pages appropriatelyKinsey Moore2022-07-061-2/+2
| | | | | | | | | There were two bugs with MMU page use that were partially hiding each other. The linker script page table section was 4x the size it needed to be and the page table allocation routine was allocating pages PTRSIZE times larger than it needed to. On ILP32, this resulted in incorrect but functional allocation. On LP64, this resulted in allocation failures earlier than expected.
* bsp/aarch64: Flush the cache before invalidating itChris Johns2022-06-161-1/+2
| | | | | - Any page tables need to be flushed if the cache is enabled. Disabling the cache may only be available in secure mode.
* bsp/aarch64: Fix array warningChris Johns2022-06-111-1/+1
| | | | Updates #4664
* aarch64: always boot into EL1NSGedare Bloom2022-01-122-20/+29
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* bsps/aarch64: refactor register init and hooksGedare Bloom2022-01-122-45/+48
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* bsps/aarch64: Support .noinit linker sectionSebastian Huber2021-12-131-0/+7
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* bsps/aarch64: Remove erroneous cache featureKinsey Moore2021-12-121-2/+0
| | | | | | | | | | The AArch64 cache implementation does not define rtems_cache_disable_data(), but declares that it does via CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of _CPU_cache_disable_data() is sufficient to enable this functionality without the erroneous cache feature flag. Closes #4569
* bsps/aarch64: Restore interrupt nestingKinsey Moore2021-11-101-1/+3
| | | | | Fixing the debug mask flag broke nested interrupts. This restores that functionality.
* cpukit/aarch64: Add libdebugger supportKinsey Moore2021-11-011-0/+11
| | | | | | This adds support for libdebugger under AArch64 using software breakpoints and the single-step execution mode present in all AArch64 CPUs.
* bsps/aarch64: Mask debug events from startupKinsey Moore2021-11-011-2/+2
| | | | | | Debug events should be masked at least until after the first context switch and should usually be masked until a debugger is attached for application debugging.
* bsps/aarch64: Set interrupt level correctlyKinsey Moore2021-11-011-1/+1
| | | | | | The existing code is functional but inccorrect and blindly modifies the other masking bits. It is important to preserve those other bits since they control masking of important system events.
* bsps/aarch64: Add missing MMU map recursion checkKinsey Moore2021-11-011-0/+9
| | | | | | | Certain input parameters for MMU mapping operations could cause an infinite recursion if block end boundaries didn't align to 4k. This ensures that recursion descent does not exceed 2 levels and instead rounds up to the nearest 4k block if necessary.
* aarch64: Break out MMU definitionsKinsey Moore2021-11-015-39/+121
| | | | | | This moves the AArch64 MMU memory type definitions into cpukit for use by libdebugger since remapping of memory is required to insert software breakpoints.
* cpukit: Add AArch64 SMP SupportKinsey Moore2021-09-217-26/+165
| | | | This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
* bsps/zynqmp: Use correct number of interruptsKinsey Moore2021-09-211-1/+1
| | | | | GICv2 can support up to 1024 interrupts, but ZynqMP hardware is only configured for 192 interrupts.
* bsps/zynqmp: Added I2C support for ZynqMPStephen Clark2021-09-094-0/+80
| | | | Added I2C drivers for ZynqMP and updated build system accordingly.
* aarch64/versal: Enable TX and RX FIFOsChris Johns2021-08-191-5/+8
| | | | - Wait for the tx holding register to empty in a tx flush
* bsps/irq: Implement new directives for GICv2/3Sebastian Huber2021-07-261-1/+1
| | | | Update #3269.
* bsps/zynq-uart: Make post baud change kick globalKinsey Moore2021-06-291-5/+0
| | | | | | | | The existing fix for the ZynqMP UART hardware bug only caught the vast majority of instances where it could occur. To fully fix the data corruption, this fix must be applied after every baud rate change. This makes the logic reset and kick apply in any locations where the baud rate could be changed.
* aarch64: whitespace fixes in start.SGedare Bloom2021-06-241-166/+166
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* bsps/aarch64: replace boot options with asm switch codeGedare Bloom2021-06-241-7/+8
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* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-241-2/+16
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* bsps/aarch64: add physical secure timerGedare Bloom2021-06-242-0/+9
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* aarch64: add support to drop EL3 to EL2Kinsey Moore2021-06-241-1/+26
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* aarch64/xilinx-versal: new BSPs for qemu and vck190Gedare Bloom2021-06-2410-0/+965
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* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MAXSebastian Huber2021-06-243-3/+0
| | | | | | This define is no longer used. Update #3269.
* bsps/irq: Add BSP_INTERRUPT_VECTOR_COUNTSebastian Huber2021-06-243-0/+3
| | | | | | | | | | | | | Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT. After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no interrupt vector at all. Using COUNT instead of MAX may avoid some interpretation issues, for example is the maximum value a valid vector number or not. Update #3269.
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MINSebastian Huber2021-06-243-3/+0
| | | | | | | | | | Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector numbers start with zero. The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit and building all BSPs. Update #3269.
* aarch64: add qemu bsps for cortex-a72Gedare Bloom2021-06-096-0/+355
| | | | The a72 BSPs are identical to the a53 BSPs just changing a53 to a72.
* bsps/aarch64: Add MMU driver to relax alignmentKinsey Moore2021-05-275-0/+518
| | | | | | | | | | | | | | | Currently, the AArch64 BSPs have a hard time running on real hardware without building the toolchain and the bsps with -mstrict-align in multiple places. Configuring the MMU on these chips allows for unaligned memory accesses for non-device memory which avoids requiring strict alignment in the toolchain and in the BSPs themselves. In writing this driver, it was found that the synchronous exception handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to avoid thread stack misalignments in RTEMS_DEBUG mode. This is now avoided by exactly preserving thread mode stack and flags and the new implementation is compatible with the draft information provided on the mailing list covering the Exception Management API.
* bsps/aarch64: Advertise cache function supportKinsey Moore2021-05-271-0/+10
| | | | | Ensure that cache functions are flagged as usable by the generic cache implementation code.
* bsps/aarch64: Align MVAs consistentlyKinsey Moore2021-05-271-8/+5
| | | | | | This fixes a bug where addresses were not being aligned correctly. Addresses used in cache functions are now aligned consistently using RTEMS_ALIGN_DOWN.
* bsps/aarch64: Break out system registersKinsey Moore2021-05-271-180/+33
| | | | | Break out system register definitions and accessors so that they're usable by other parts of RTEMS.
* bsps/xilinx-zynqmp: Avoid constant UART reinitKinsey Moore2021-04-191-0/+6
| | | | | | Constantly reinitializing the Cadence UART on every character output causes data corruption/loss on some ZynqMP hardware. Only initialize the UART once for early output and give it a kick on startup.
* bsps/aarch64: Add support for EL2 startKinsey Moore2021-03-051-0/+25
| | | | | Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for normal operation.
* bsps/aarch64: RTEMS_DEBUG stack alignment faultsKinsey Moore2021-03-051-0/+8
| | | | | | Run with stack alignment faults enabled under RTEMS_DEBUG to catch any stack misalignments early. This makes it easier to track them down should they ever occur.
* bsps: Allow override of ARM TM27 IRQsKinsey Moore2021-03-051-0/+8
| | | | | | ZynqMP hardware appears to have an odd hard-wired SGI implementation in which the SGIs are permanently set as enabled or disabled. Allow the TM27 IRQs to be overridden as necessary.
* bsps/aarch64: Resolve usage of SUBALIGN()Kinsey Moore2021-03-051-4/+2
| | | | | | | | Remove usage of SUBALIGN() in aarch64 linkcmds which works around a difference in behavior on AArch64 platforms. This is no longer necessary since alignment is now enforced explicitly. Closes #4178.
* bsps/aarch64: Add missing includeSebastian Huber2021-01-281-0/+1
| | | | | | | | | Fixes: bsps/shared/dev/irq/arm-gicv2.c:53:6: warning: no previous prototype for 'bsp_interrupt_dispatch' [-Wmissing-prototypes] Close #4227.
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
| | | | Sort alphabetically.
* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-8/+13
| | | | GCC 11 uses DWARF 5 by default.
* bsps/aarch64: Swap primary ZynqMP UARTKinsey Moore2021-01-142-4/+4
| | | | | Both Qemu and actual hardware treat the second UART in memory map as the primary UART. This adjusts the ZynqMP BSPs to match.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-3/+17
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps: Fix includesSebastian Huber2020-12-221-1/+0
| | | | Update #4202.
* bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber2020-12-161-5/+0
| | | | | | Avoid one level of indirection. Update #4202.
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