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* bsps/zynq-uart: Make post baud change kick globalKinsey Moore2021-06-291-5/+0
| | | | | | | | The existing fix for the ZynqMP UART hardware bug only caught the vast majority of instances where it could occur. To fully fix the data corruption, this fix must be applied after every baud rate change. This makes the logic reset and kick apply in any locations where the baud rate could be changed.
* aarch64: whitespace fixes in start.SGedare Bloom2021-06-241-166/+166
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* bsps/aarch64: replace boot options with asm switch codeGedare Bloom2021-06-241-7/+8
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* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-241-2/+16
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* bsps/aarch64: add physical secure timerGedare Bloom2021-06-242-0/+9
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* aarch64: add support to drop EL3 to EL2Kinsey Moore2021-06-241-1/+26
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* aarch64/xilinx-versal: new BSPs for qemu and vck190Gedare Bloom2021-06-2410-0/+965
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* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MAXSebastian Huber2021-06-243-3/+0
| | | | | | This define is no longer used. Update #3269.
* bsps/irq: Add BSP_INTERRUPT_VECTOR_COUNTSebastian Huber2021-06-243-0/+3
| | | | | | | | | | | | | Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT. After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no interrupt vector at all. Using COUNT instead of MAX may avoid some interpretation issues, for example is the maximum value a valid vector number or not. Update #3269.
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MINSebastian Huber2021-06-243-3/+0
| | | | | | | | | | Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector numbers start with zero. The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit and building all BSPs. Update #3269.
* aarch64: add qemu bsps for cortex-a72Gedare Bloom2021-06-096-0/+355
| | | | The a72 BSPs are identical to the a53 BSPs just changing a53 to a72.
* bsps/aarch64: Add MMU driver to relax alignmentKinsey Moore2021-05-275-0/+518
| | | | | | | | | | | | | | | Currently, the AArch64 BSPs have a hard time running on real hardware without building the toolchain and the bsps with -mstrict-align in multiple places. Configuring the MMU on these chips allows for unaligned memory accesses for non-device memory which avoids requiring strict alignment in the toolchain and in the BSPs themselves. In writing this driver, it was found that the synchronous exception handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to avoid thread stack misalignments in RTEMS_DEBUG mode. This is now avoided by exactly preserving thread mode stack and flags and the new implementation is compatible with the draft information provided on the mailing list covering the Exception Management API.
* bsps/aarch64: Advertise cache function supportKinsey Moore2021-05-271-0/+10
| | | | | Ensure that cache functions are flagged as usable by the generic cache implementation code.
* bsps/aarch64: Align MVAs consistentlyKinsey Moore2021-05-271-8/+5
| | | | | | This fixes a bug where addresses were not being aligned correctly. Addresses used in cache functions are now aligned consistently using RTEMS_ALIGN_DOWN.
* bsps/aarch64: Break out system registersKinsey Moore2021-05-271-180/+33
| | | | | Break out system register definitions and accessors so that they're usable by other parts of RTEMS.
* bsps/xilinx-zynqmp: Avoid constant UART reinitKinsey Moore2021-04-191-0/+6
| | | | | | Constantly reinitializing the Cadence UART on every character output causes data corruption/loss on some ZynqMP hardware. Only initialize the UART once for early output and give it a kick on startup.
* bsps/aarch64: Add support for EL2 startKinsey Moore2021-03-051-0/+25
| | | | | Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for normal operation.
* bsps/aarch64: RTEMS_DEBUG stack alignment faultsKinsey Moore2021-03-051-0/+8
| | | | | | Run with stack alignment faults enabled under RTEMS_DEBUG to catch any stack misalignments early. This makes it easier to track them down should they ever occur.
* bsps: Allow override of ARM TM27 IRQsKinsey Moore2021-03-051-0/+8
| | | | | | ZynqMP hardware appears to have an odd hard-wired SGI implementation in which the SGIs are permanently set as enabled or disabled. Allow the TM27 IRQs to be overridden as necessary.
* bsps/aarch64: Resolve usage of SUBALIGN()Kinsey Moore2021-03-051-4/+2
| | | | | | | | Remove usage of SUBALIGN() in aarch64 linkcmds which works around a difference in behavior on AArch64 platforms. This is no longer necessary since alignment is now enforced explicitly. Closes #4178.
* bsps/aarch64: Add missing includeSebastian Huber2021-01-281-0/+1
| | | | | | | | | Fixes: bsps/shared/dev/irq/arm-gicv2.c:53:6: warning: no previous prototype for 'bsp_interrupt_dispatch' [-Wmissing-prototypes] Close #4227.
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
| | | | Sort alphabetically.
* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-8/+13
| | | | GCC 11 uses DWARF 5 by default.
* bsps/aarch64: Swap primary ZynqMP UARTKinsey Moore2021-01-142-4/+4
| | | | | Both Qemu and actual hardware treat the second UART in memory map as the primary UART. This adjusts the ZynqMP BSPs to match.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-3/+17
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps: Fix includesSebastian Huber2020-12-221-1/+0
| | | | Update #4202.
* bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber2020-12-161-5/+0
| | | | | | Avoid one level of indirection. Update #4202.
* Add AArch64 ZynpMP BSPKinsey Moore2020-12-046-0/+426
| | | | | | | | This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC (ZynqMP) family of chips. It is configured to be usable on the Qemu ZCU102 machine definition and should be almost trivially portable to ZynqMP development boards and custom hardware. It is also configured to be usable with libbsd.
* bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2020-12-021-1/+1
| | | | | This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
* spec/aarch64: Only apply SUBALIGN(4) to ILP32Kinsey Moore2020-11-231-2/+4
| | | | | | | The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds was previously present on LP64 builds and causes no issues within RTEMS, but causes relocation/alignment issues when building libbsd. This restricts those alignment changes to ILP32 builds.
* bsps: Add Cortex-A53 ILP32 BSP variantKinsey Moore2020-10-051-0/+16
| | | | | | This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
* bsps: Add Cortex-A53 LP64 basic BSPKinsey Moore2020-10-0513-0/+2137
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
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