| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
| |
Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
|
| |
|
| |
|
|
|
|
|
|
|
|
|
|
| |
The AArch64 cache implementation does not define
rtems_cache_disable_data(), but declares that it does via
CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of
_CPU_cache_disable_data() is sufficient to enable this functionality
without the erroneous cache feature flag.
Closes #4569
|
|
|
|
|
| |
Fixing the debug mask flag broke nested interrupts. This restores that
functionality.
|
|
|
|
|
|
| |
This adds support for libdebugger under AArch64 using software
breakpoints and the single-step execution mode present in all AArch64
CPUs.
|
|
|
|
|
|
| |
Debug events should be masked at least until after the first context
switch and should usually be masked until a debugger is attached for
application debugging.
|
|
|
|
|
|
| |
The existing code is functional but inccorrect and blindly modifies the
other masking bits. It is important to preserve those other bits since
they control masking of important system events.
|
|
|
|
|
|
|
| |
Certain input parameters for MMU mapping operations could cause an
infinite recursion if block end boundaries didn't align to 4k. This
ensures that recursion descent does not exceed 2 levels and instead
rounds up to the nearest 4k block if necessary.
|
|
|
|
|
|
| |
This moves the AArch64 MMU memory type definitions into cpukit for use
by libdebugger since remapping of memory is required to insert software
breakpoints.
|
|
|
|
| |
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
|
|
|
|
|
| |
GICv2 can support up to 1024 interrupts, but ZynqMP hardware is only
configured for 192 interrupts.
|
|
|
|
| |
Added I2C drivers for ZynqMP and updated build system accordingly.
|
|
|
|
| |
- Wait for the tx holding register to empty in a tx flush
|
|
|
|
| |
Update #3269.
|
|
|
|
|
|
|
|
| |
The existing fix for the ZynqMP UART hardware bug only caught the vast
majority of instances where it could occur. To fully fix the data
corruption, this fix must be applied after every baud rate change. This
makes the logic reset and kick apply in any locations where the baud
rate could be changed.
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
|
|
|
|
| |
This define is no longer used.
Update #3269.
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT.
After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be
removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The
BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no
interrupt vector at all. Using COUNT instead of MAX may avoid some
interpretation issues, for example is the maximum value a valid vector number
or not.
Update #3269.
|
|
|
|
|
|
|
|
|
|
| |
Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector
numbers start with zero.
The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit
and building all BSPs.
Update #3269.
|
|
|
|
| |
The a72 BSPs are identical to the a53 BSPs just changing a53 to a72.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Currently, the AArch64 BSPs have a hard time running on real hardware
without building the toolchain and the bsps with -mstrict-align in
multiple places. Configuring the MMU on these chips allows for unaligned
memory accesses for non-device memory which avoids requiring strict
alignment in the toolchain and in the BSPs themselves.
In writing this driver, it was found that the synchronous exception
handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to
avoid thread stack misalignments in RTEMS_DEBUG mode. This is now
avoided by exactly preserving thread mode stack and flags and the new
implementation is compatible with the draft information provided on the
mailing list covering the Exception Management API.
|
|
|
|
|
| |
Ensure that cache functions are flagged as usable by the generic cache
implementation code.
|
|
|
|
|
|
| |
This fixes a bug where addresses were not being aligned correctly.
Addresses used in cache functions are now aligned consistently using
RTEMS_ALIGN_DOWN.
|
|
|
|
|
| |
Break out system register definitions and accessors so that they're
usable by other parts of RTEMS.
|
|
|
|
|
|
| |
Constantly reinitializing the Cadence UART on every character output
causes data corruption/loss on some ZynqMP hardware. Only initialize
the UART once for early output and give it a kick on startup.
|
|
|
|
|
| |
Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for
normal operation.
|
|
|
|
|
|
| |
Run with stack alignment faults enabled under RTEMS_DEBUG to catch any
stack misalignments early. This makes it easier to track them down
should they ever occur.
|
|
|
|
|
|
| |
ZynqMP hardware appears to have an odd hard-wired SGI implementation in
which the SGIs are permanently set as enabled or disabled. Allow the
TM27 IRQs to be overridden as necessary.
|
|
|
|
|
|
|
|
| |
Remove usage of SUBALIGN() in aarch64 linkcmds which works around a
difference in behavior on AArch64 platforms. This is no longer necessary
since alignment is now enforced explicitly.
Closes #4178.
|
|
|
|
|
|
|
|
|
| |
Fixes:
bsps/shared/dev/irq/arm-gicv2.c:53:6: warning: no previous prototype for
'bsp_interrupt_dispatch' [-Wmissing-prototypes]
Close #4227.
|
|
|
|
| |
Sort alphabetically.
|
|
|
|
| |
GCC 11 uses DWARF 5 by default.
|
|
|
|
|
| |
Both Qemu and actual hardware treat the second UART in memory map as the
primary UART. This adjusts the ZynqMP BSPs to match.
|
|
|
|
|
|
| |
This avoids a function call overhead in the interrupt dispatching.
Update #4202.
|
|
|
|
| |
Update #4202.
|
|
|
|
|
|
| |
Avoid one level of indirection.
Update #4202.
|
|
|
|
|
|
|
|
| |
This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC
(ZynqMP) family of chips. It is configured to be usable on the Qemu
ZCU102 machine definition and should be almost trivially portable to
ZynqMP development boards and custom hardware. It is also configured to
be usable with libbsd.
|
|
|
|
|
| |
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
|
|
|
|
|
|
|
| |
The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds
was previously present on LP64 builds and causes no issues within RTEMS,
but causes relocation/alignment issues when building libbsd. This
restricts those alignment changes to ILP32 builds.
|
|
|
|
|
|
| |
This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
|
|
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
|