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* arm/raspberrypi: Enable HYP to SVC switch for this BSP.Pavel Pisa2016-07-042-0/+7
| | | | | This support is required when newer firmware is used on Raspberry Pi 2 boards.
* bsps/arm: Support recent bootloaders starting kernel in HYP modePavel Pisa2016-07-045-7/+175
| | | | | | | | | | | | | | | | | | | When HYP mode is detected at startup then setup HYP mode vectors table (for future extensions) clean exceptions switching to HYP mode and switch CPU to ARM SVC mode. BSPs which want to use this support need to include next option in their configure.ac RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") and need to include next lines in corresponding Makefile.am if BSP_START_IN_HYP_SUPPORT libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S endif
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-07-042-0/+31
base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example).
* arm/raspberrypi: resolve BSP warnings.Pavel Pisa2016-06-285-2/+8
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* arm/raspberrypi: run VideoCore and mailbox code through rtems.uncrustify.Pavel Pisa2016-06-285-246/+266
Some changes have been reverted to keep readability. For example squash of BCM2835_MBOX_TAG_* defines which are visually aligned in column.
* arm/raspberrypi: Force VC mail box buffer to be synchronized through cache.Pavel Pisa2016-06-241-1/+13
| | | | | This solution is quick fix until CPU_DATA_CACHE_ALIGNMENT is defined and cache manager is checked on all Raspberry Pi variants.
* MAINTAINERS: added selfPavel Pisa2016-06-241-0/+3
* bsp/tms570: regenerate preinstall makefile by bootstrap -p.Pavel Pisa2016-06-211-0/+8
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* bsp/tms570: include complete peripheral initialization to SCI driver.Pavel Pisa2016-06-211-2/+36
| | | | Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: update pinmux to provide support for initialization lists and ↵Pavel Pisa2016-06-214-69/+196
| | | | clear of alt outputs.
* bsp/tms570: include package balls and PINMMR registers mapping for ↵Pavel Pisa2016-06-212-0/+700
TMS570LS3135ZWT chip.
* arm/raspberrypi: Ensure that buffers used for VC mail box communication are ↵Pavel Pisa2016-06-202-7/+56
synchronized through cache.
* arm/raspberrypi: move MMU in front of application image to respect variable ↵Pavel Pisa2016-05-314-4/+83
memory size. The page table is placed at address 0x00004000 which provides required 16 kB space till the start of application image. The RAM size specified in a linker script is upper limit address of RAM utilized for the work area initialization. If VideoCore reports to use lower address than expected then work area size is adjusted (shrinked) appropriately.
* arm/raspberrypi: Raspberry Pi v2 ALLOCATE_BUFFER VC4 operation returns ↵Pavel Pisa2016-05-311-0/+4
| | | | direct address.
* arm/raspberrypi: ensure that correct RPI_PERIPHERAL_BASE is provided by ↵Pavel Pisa2016-05-314-0/+4
| | | | | | | | | | | raspberrypi.h If the raspberrypi.h has been included without preceding inclussion of bsp.h then BSP_IS_RPI2 has not been set for Raspberry Pi 2 BSP variant and bad things happen later. The patch includes bspopts.h by raspberrypi.h and even includes bsp.h in critical peripherals support.
* arm/raspberrypi: cmdline enhancement and early access workaround.Pavel Pisa2016-05-311-4/+8
cmdline argument is returned without option name. The calls to command line parsing can be called earlier before BSS is cleaned out.
* arm/raspberrypi: add cmdline support for rpi bsp.Pavel Pisa2016-05-193-0/+54
* arm/raspberrypi: add locking around GPIO pin function selection.Pavel Pisa2016-05-191-0/+5
| | | | | | | | | | This is required if function or direction is changed by some driver after start of thread multitasking or in interrupts drivers. There can be problem with calling GPIO function selection before data section is initialized. But actual ticket lock implementation seems to be compatible even with memory initialized to zero oven on SMP.
* arm/raspberrypi: correct GPIO pin function selection.Pavel Pisa2016-05-192-10/+11
| | | | | | Original implementation does only bitwise-or with previous register value for all functions except IN. Switch from one to other function would lead to incorrect value.
* arm/raspberrypi: ensure that RTEMS application image can be started by U-boot.Pavel Pisa2016-05-192-1/+39
| | | | | | | | | | | | | | | | The current versions of U-boot start kernel/RTEMS application image with instruction and data caches enabled and it sets exception base register to new address after its self-relocation. ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ Included changes in bsp_start_hook_0 restore default state to allow RTEMS image to run after startup from newer U-boot version on Raspberry Pi. Clear interrupt enable registers in interrupt controller to ensure that RTEMS starts from well defined state.
* bsps/arm: CP15 support for flush prefetch buffer and table base control.Pavel Pisa2016-05-191-0/+48
* i386/pc386: reimplemented check for unused EDID entry in fb_vesa.c to ↵Pavel Pisa2016-04-162-1/+9
suppress GCC 6 warning. closes #2634
* bsp/tms570: ensure that linker symbol comparison to NULL is not optimized out.Pavel Pisa2015-12-011-2/+12
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* untar: do not exit with error when created directory already exists.Pavel Pisa2015-11-232-2/+46
The problem exists for both RTEMS untar implementations and their variants: Untar_FromMemory(), Untar_FromFile() and rtems_tarfs_load(). If filesystem object already exists at extracted directory path then if it is directory, creation is ignored. Attempt to delete/unlink object and make directory is tried for other cases. This simple approach problem reported in ticket fixes #2413. Behavior follows GNU tar and BSD tar practice for directories but much more work is required to achieve full semantics of the full featured tar implementation still.
* bsp/tms570: use common tms570ls3137.inc file for all board ling variants.Pavel Pisa2015-11-185-64/+24
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* bsp/tms570: use POM only when application image does not start at address 0.Pavel Pisa2015-11-187-14/+159
Parameters overlay module is initialized and cleared first. It is used later to replace exception target vectors only if that is required. The application loader code with CPU and SDRAM setup code has to provide well defined pattern of instructions at addresses 0x00000000 and 0x0000001f, because only data read accesses can be processed reliably by POM. The expected instruction pattern can be seen in the next example https://github.com/hornmich/tms570ls3137-hdk-sdram/blob/master/SDRAM_SCI_configuration/source/sys_intvecs.asm Comments with detailed description of code, background and reasons for selected approach have been included in TMS570 bsp startup code. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Premysl Houdek <kom541000@gmail.com>
* bsp/tms570: fix get time resolution after infrastructure change to timecounter.Pavel Pisa2015-07-161-6/+35
The update fixes breakage of TMS570 support after Alexander Krutwig switch of RTEMS time read to timecounter mechanism bsps: Convert clock drivers to use a timecounter Mechanism to specify odd (non 1 Mhz) time base update frequencies implemented after objections of Martin Galvan. Code is adjusted to convert RTEMS configuration parameter microseconds_per_tick to such odd base if TMS570_PREFERRED_TC_FREQUENCY is specified appropriately. Signed-off-by: Premysl Houdek <kom541000@gmail.com> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* arm/tms570: sci context has to be writable because it holds state variable.Pavel Pisa2015-02-042-4/+4
The structure tms570_sci_context holds state variable tx_chars_in_hw which holds if and how many characters (in the optional FIFO support for some Ti SCIs) are submitted into hardware. When field is not writable then code breaks when RTEMS is build for Flash area. The problem found and analyzed by Martin Galvan from tallertechnologies. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
* score: More strict RTEMS_DEQUALIFY implementation.Pavel Pisa2014-09-081-1/+53
This implementation is able to catch cast to type which differs not only in qualifiers. The error diagnostic message when used in function is self descriptive. Macro is compatible with used in initializers but there message about not constant initial value signals types incompatibility. The actual implementation does not distinguish between volatile and const removal.
* bsp/tms570: implemented and tested initialization of Cortex-R performance ↵Pavel Pisa2014-08-221-4/+84
counters. The code is written as BSP specific now but it should work for all Cortex-A and R based CPUs and can be moved to ARM generic place in future. StackOverflow suggested sequences of writes to the registers required to start counters is used. http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor
* bsp/tms570: disable huge memory demanding tests for internal RAM build variant.Pavel Pisa2014-08-212-13/+23
| | | | | | | | | | | | | BSP completes build with tests and debug enabled for all three variants now tms570ls3137_hdk tms570ls3137_hdk_intram tms570ls3137_hdk_sdram Even that all enabled tests builds for internal RAM variant, many of them are expected to fail on hardware because whole tests including code, data and runtime work area demands has to fit into 256 kB of RAM.
* bsp/tms570: implemented support functions to satisfy complete tests build ↵Pavel Pisa2014-08-219-4/+186
requirements. This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram BSP variant in in default build. Debug build with --enable-rtems-debug set has succeed for samples subset of tests as well.
* lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in ↵Pavel Pisa2014-08-201-1/+6
digital mode for non-analog function. The problem wit incorrect switching of pins into analog mode manifestes on LPC4088 based board. LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin with analog option). The pin was listed as D category on LPC1788 which does not have analog mode control bit. If analog option is not explicitly switched off on LPC4088 then the pin does not work as digital pin. Code tested on LPC1788 and no problems has been observed even that manual specifies the IOCON_ADMODE field as reserved and should be written as zero. But even RTEMS lpc24xx_gpio_config sets this bit unconditionally. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* SPI SD-Card: adapt common driver code to block devices core API changes.Pavel Pisa2014-03-311-3/+3
* bsps/arm: Add DP83848 PHY support to LPC EthernetPavel Pisa2014-03-141-0/+8
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* bsps/arm: Add PHY detection to LPC EthernetPavel Pisa2014-03-141-13/+45
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* bsps/arm: Reset MII management in LPC EthernetPavel Pisa2014-03-141-1/+7
| | | | Reduce MII clock to support LPC17XX.
* bsp/lpc24xx: Add LPC24XX_PIN_ETHERNET_POWER_DOWNPavel Pisa2014-03-142-0/+15
* SPI SD-Card: setup valid CRC-7 for STOP_TRANSMISSION command.Pavel Pisa2013-10-081-0/+5
STOP_TRANSMISSION command is used to finish READ_MULTIPLE_BLOCK command and its format is regular command format. It requires valid CRC-7 to have effect at least on same cards types else it is ignored and attempt to issue next READ or WRITE commands results in illegal command condition (0x04) preceded by strange (0x3f) for tested card. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/csb336: Memory map update and jump to start at image start provided.Pavel Pisa2013-08-142-3/+14
CSB336 i.MX1/i.MXS memory map organization - SDRAM starts at address 0x08000000 but 2 MB are reserved for boot-block/loader (or other use) before RTEMS image origin/load address (that is kept from previous setup) - Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000) is changed to writeback mode which provides higher throughput. - The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0 to provide area for ARM CPU exceptions table. - Internal registers and rest of the Flash (above 1 MB) are mapped one to one. Registers region is extended to 2 MB to cover eSRAM found on i.MX1 chip variant. - The first two megabytes of SDRAM unused by RTEMS are mapped with attributes to allow specific purposes. - the first MB (at address 0x08000000) is nocached to allow directly set some values read by booot-block after warm reset - the second MB (at address 0x08100000) is set for write-through caching. That allows to use memory for LCD frame-buffer without need to flush cache after each redraw. Jump to start provided at address 0x08200000 allows to load application image even as plain binary file and start it by jump to image start address. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/csb336: implement bsp_interrupt_vector_enable/disable.Pavel Pisa2013-08-091-0/+10
| | | | Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/csb336: Fix MMU _ttbl_base location to not overlap with exception vectors.Pavel Pisa2013-08-091-3/+4
The initial region (64 bytes) of SDRAM RTEMS image is remapped to provide overlay of the initial/ROM exceptions table. This area cannot be used for MMU mapping table. Different correctly aligned block has to be used for MMU table. Remapping of SDRAM (address 0x08200000) to address 0 is supported only on 1 MB block granularity and that is why SDRAM_VEC area has to be 1 MB aligned too but unused part of remapped region can be freely used for other purposes (as MMU tables). Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* bsp/csb336: mc9328mxl correct AITC access in bsp_interrupt_dispatch.Pavel Pisa2013-07-261-1/+2
The original version is missing void and result is that (*x >> 16) is optimized to ldh rX,[rY]. But it is not allowed/supported to access bus/address range used by AITC by other than 32 bit wide accesses and 16-bit access results in the data abort exception. The corrected version works on real hardware and is even more readable. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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