summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* posix: Fix fall back spinlock implementationSebastian Huber2016-12-022-10/+7
| | | | Update #2674.
* libdebugger: Build for ARM's without a CP15.Chris Johns2016-12-027-41/+139
|
* Remove sparc/sis BSP.Joel Sherrill2016-11-299-104/+0
| | | | closes #2810.
* cpukit: Add libdebugger, a remote debugger agent for GDB.Chris Johns2016-11-2930-0/+6991
|
* arm/zynq: Wait for the UART TX FIFO to empty on reset.Chris Johns2016-11-293-0/+24
|
* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-287-81/+110
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* score: Fix thread queue context initializationSebastian Huber2016-11-2810-10/+18
| | | | | Initialize the thread queue context with invalid data in debug configurations to catch missing set up steps.
* or1k: Avoid multiple iterations over cacheMartin Erik Werner2016-11-281-0/+27
| | | | | | | | | Previously, if the cache range operations were called with a range that was larger than the cache size, this would lead to multiple iterations over the cache, which is unnecessary. Limit this so that if the range is larger than the cache size, the operations will only iterate over the whole cache once.
* or1k: Remove secondary functions in cache managerMartin Erik Werner2016-11-281-56/+34
| | | | | | | | | | Move the code of the _CPU_OR1K_Cache_{enable,disable}_* functions into the equivalent exported _CPU_cache_{enable,disable}_* functions instead, and then delete them, in order to reduce the code indirection and aid readability. This does not touch the currently unused prefetch, writeback, and lock functions.
* or1k: Avoid excessive ISR toggle in cache managerMartin Erik Werner2016-11-282-44/+123
| | | | | | | | | | | | | | | | | Previously _ISR_Local_{disable,enable}() was executed twice for each cache line operation, and since operations over the entire cache were implemented by calling the single-line operations in a loop, this made those operations rather costly. Fix the double-toggle by calling _OR1K_mtspr() directly, and removing the now-unused corresponding _CPU_OR1K_Cache_* functions. Fix the entire-operations by moving the ISR toggle outside of the loop, and by calling _OR1K_mtspr() directly instead of the single-line operations. Also implement range functions, since otherwise the cache manager falls back on looping over the single-line operations.
* or1k: Indent & comment fix in cache.cMartin Erik Werner2016-11-281-14/+25
| | | | | | | * Fix indentation of variable declarations. * Change commented-out asm -> __asm__ to meet c99 standard if uncommented.
* or1k: Add functions for entire cache operationsMartin Erik Werner2016-11-281-3/+42
| | | | | | | | | | | | | | | Add functions for flushing and invalidating whole cache. Since we don't have system calls that can operate on anything more than a single cache line, these simply retrieves the cache size and iterates over the full size, invalidating each line. The current implementation assumes that there's only one level of cache. These changes were contributed by Antmicro under contract by ÅAC Microtec AB. Close #2602
* libblock: Fix for RTEMS_DEBUGSebastian Huber2016-11-241-0/+2
|
* bsps/arm: Add Cortex-M DWT CPU counterSebastian Huber2016-11-243-1/+57
|
* arm: Fix _CPU_ISR_Is_enabled() for ARMv7-MSebastian Huber2016-11-241-1/+1
| | | | Update #2811.
* score: Optimize _Thread_queue_Enqueue()Sebastian Huber2016-11-2420-28/+117
| | | | | | | | | Move thread state for _Thread_queue_Enqueue() to the thread queue context. This reduces the parameter count of _Thread_queue_Enqueue() from five to four (ARM for example has only four function parameter registers). Since the thread state is used after several function calls inside _Thread_queue_Enqueue() this parameter was saved on the stack previously.
* score: Fix interrupt profilingSebastian Huber2016-11-243-25/+33
| | | | | | | | | | Callers of _Thread_Do_dispatch() must have a valid Per_CPU_Control::Stats::thread_dispatch_disabled_instant. Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt stack to not exceed Per_CPU_Control::Interrupt_frame. Update #2751.
* powerpc: Fix interrupt profiling for e6500Sebastian Huber2016-11-241-1/+3
|
* posix: Fix typoSebastian Huber2016-11-231-1/+1
| | | | Update #2674.
* score: Explicitly define the fatal source numbersSebastian Huber2016-11-231-11/+11
| | | | Update #2825.
* smptests/smpfatal03: Use timer to provoke errorSebastian Huber2016-11-231-31/+21
| | | | | | Avoid use of internal _Thread_Dispatch_disable() function. Update #2825.
* score: Uncomment unused internal error codesSebastian Huber2016-11-233-38/+44
| | | | Update #2825.
* posix: Add self-contained pthread spinlockSebastian Huber2016-11-2336-1157/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Turn pthread_spinlock_t into a self-contained object. On uni-processor configurations, interrupts are disabled in the lock/trylock operations and the previous interrupt status is restored in the corresponding unlock operations. On SMP configurations, a ticket lock is a acquired and released in addition. The self-contained pthread_spinlock_t object is defined by Newlib in <sys/_pthreadtypes.h>. typedef struct { struct _Ticket_lock_Control _lock; __uint32_t _interrupt_state; } pthread_spinlock_t; This implementation is simple and efficient. However, this test case of the Linux Test Project would fail due to call of printf() and sleep() during spin lock ownership: https://github.com/linux-test-project/ltp/blob/master/testcases/open_posix_testsuite/conformance/interfaces/pthread_spin_lock/1-2.c There is only limited support for profiling on SMP configurations. Delete CORE spinlock implementation. Update #2674.
* score: Add RTEMS_ALIAS()Sebastian Huber2016-11-231-0/+10
|
* score: Rename _Thread_queue_Enqueue_critical()Sebastian Huber2016-11-2321-69/+31
| | | | | Delete unused _Thread_queue_Enqueue() and rename _Thread_queue_Enqueue_critical() to _Thread_queue_Enqueue().
* score: Add thread queue enqueue calloutSebastian Huber2016-11-2328-226/+351
| | | | | | | Replace the expected thread dispatch disable level with a thread queue enqueue callout. This enables the use of _Thread_Dispatch_direct() in the thread queue enqueue procedure. This avoids impossible exection paths, e.g. Per_CPU_Control::dispatch_necessary is always true.
* score: Robust thread dispatchSebastian Huber2016-11-2328-4/+190
| | | | | | | | | | | | On SMP configurations, it is a fatal error to call blocking operating system with interrupts disabled, since this prevents delivery of inter-processor interrupts. This could lead to executing threads which are not allowed to execute resulting in undefined behaviour. The ARM Cortex-M port has a similar problem, since the interrupt state is not a part of the thread context. Update #2811.
* smptests/smplock01: Test TAS and TTAS locksSebastian Huber2016-11-234-1560/+2508
| | | | Cache align locks in the context.
* libtests/cpuuse: Check status onlySebastian Huber2016-11-231-2/+2
| | | | We may own the allocator mutex during context switches.
* smptests/smpscheduler02: Fix task initializationSebastian Huber2016-11-231-2/+2
| | | | Set scheduler before the task start.
* score: Delete obsolete scheduler debug aidSebastian Huber2016-11-234-67/+0
|
* arm: Fix _ARMV4_Exception_interruptSebastian Huber2016-11-231-1/+1
| | | | | | | Use the right register to determine if a thread dispatch is allowed and necessary. Update #2751.
* psxtests/psxkey08: Avoid rtems_semaphore_flush()Sebastian Huber2016-11-232-48/+42
| | | | | | Avoid rtems_semaphore_flush() to reduce the maximum thread dispatch disabled time of this test. Remove superfluous yield and malloc(). Ensure that no resource leak occurs.
* score: Force Per_CPU_Control::executing alignmentSebastian Huber2016-11-231-0/+7
| | | | | | | | This fixes the CPU ports with relaxed alignment restrictions, e.g. type alignment is less than the type size. Close #2822. Close #2823.
* bsp/lpc23xx_tli800: Disable tar01 testSebastian Huber2016-11-231-0/+1
| | | | Close #2824.
* arm: Fix Thumb-1 targetsSebastian Huber2016-11-212-10/+40
| | | | | | | We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM mode for the Thumb-1 targets during interrupt low-level processing. Update #2751.
* powerpc/mpc5xx: Rename CPU_Interrupt_frameSebastian Huber2016-11-212-4/+4
| | | | | | The MPC5XX support uses a legacy interrupt/exception infrastructure. Close #2819.
* score: Group Per_CPU_Control members by alignmentSebastian Huber2016-11-211-19/+19
| | | | Close #2820.
* sparc64: Fix _CPU_ISR_Is_enabled()Sebastian Huber2016-11-211-1/+1
| | | | Update #2820.
* nios2: Fix _CPU_ISR_Is_enabled()Sebastian Huber2016-11-211-4/+4
| | | | Close #2818.
* arm: Fix ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLESebastian Huber2016-11-211-2/+4
| | | | Close #2816.
* bfin: ASM compatibility for <rtems/score/cpu.h>Sebastian Huber2016-11-211-2/+2
| | | | Close #2817.
* score: Optimize self-contained objectsSebastian Huber2016-11-184-41/+62
| | | | Avoid use of the stack for the hot paths.
* score: Constify _MRSP_Get_owner()Sebastian Huber2016-11-181-1/+3
|
* score: Add _ISR_Is_enabled()Sebastian Huber2016-11-1820-2/+126
| | | | | | | In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates a level parameter and returns a boolean value. Update #2811.
* score: Restrict task interrupt level to 0 on SMPSebastian Huber2016-11-182-3/+25
| | | | Update #2811.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-184-22/+71
| | | | Update #2751.
* arm: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-184-31/+94
| | | | Update #2751.
* arm: Simplify _ARMV4_Exception_interruptSebastian Huber2016-11-181-18/+22
| | | | | Move profiling code closer to bsp_interrupt_disable() to allow re-use of r9 later.
* arm: Use local labelsSebastian Huber2016-11-181-9/+9
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-09 10:10:36 +0000