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authorChris Johns <chrisj@rtems.org>2016-11-29 22:19:05 (UTC)
committerChris Johns <chrisj@rtems.org>2016-12-02 04:39:56 (UTC)
commite629076003998b004e9bcf3a0e71633383d93863 (patch)
tree01249460b294adbac50361efd14c76e74e1ed77b
parentde7b174e381ee60686487c03c6db8d0ed7596da1 (diff)
downloadrtems-e629076003998b004e9bcf3a0e71633383d93863.tar.bz2
libdebugger: Build for ARM's without a CP15.
-rw-r--r--c/src/lib/libbsp/arm/beagle/Makefile.am1
-rw-r--r--c/src/lib/libbsp/arm/gdbarmsim/Makefile.am6
-rw-r--r--c/src/lib/libbsp/arm/gdbarmsim/configure.ac2
-rw-r--r--c/src/lib/libbsp/arm/tms570/Makefile.am5
-rw-r--r--c/src/lib/libbsp/arm/tms570/preinstall.am9
-rw-r--r--c/src/lib/libcpu/arm/configure.ac3
-rw-r--r--cpukit/libdebugger/rtems-debugger-arm.c154
7 files changed, 139 insertions, 41 deletions
diff --git a/c/src/lib/libbsp/arm/beagle/Makefile.am b/c/src/lib/libbsp/arm/beagle/Makefile.am
index aa28f36..8bb8478 100644
--- a/c/src/lib/libbsp/arm/beagle/Makefile.am
+++ b/c/src/lib/libbsp/arm/beagle/Makefile.am
@@ -88,6 +88,7 @@ libbsp_a_SOURCES += ../../shared/timerstub.c
libbsp_a_SOURCES += ../../shared/cpucounterread.c
libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S
libbsp_a_SOURCES += ../shared/arm-cp15-set-exception-handler.c
+libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c
# Startup
libbsp_a_SOURCES += startup/bspreset.c
diff --git a/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am b/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am
index 8100c96..339a87f 100644
--- a/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am
+++ b/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am
@@ -69,5 +69,11 @@ libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
# ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer.rel \
# ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/irq.rel
+# Shared
+if shared
+libbsp_a_SOURCES += ../shared/arm-cp15-set-exception-handler.c
+libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c
+endif
+
include $(srcdir)/preinstall.am
include $(top_srcdir)/../../../../automake/local.am
diff --git a/c/src/lib/libbsp/arm/gdbarmsim/configure.ac b/c/src/lib/libbsp/arm/gdbarmsim/configure.ac
index 6e8b326..c561407 100644
--- a/c/src/lib/libbsp/arm/gdbarmsim/configure.ac
+++ b/c/src/lib/libbsp/arm/gdbarmsim/configure.ac
@@ -15,6 +15,8 @@ RTEMS_PROG_CCAS
RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
+AM_CONDITIONAL(shared, test "$RTEMS_BSP" = "armcortexa9")
+
# Explicitly list all Makefiles here
AC_CONFIG_FILES([Makefile])
AC_OUTPUT
diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am b/c/src/lib/libbsp/arm/tms570/Makefile.am
index 26c1bfe..f9d9815 100644
--- a/c/src/lib/libbsp/arm/tms570/Makefile.am
+++ b/c/src/lib/libbsp/arm/tms570/Makefile.am
@@ -10,6 +10,7 @@ ACLOCAL_AMFLAGS = -I ../../../../aclocal
include $(top_srcdir)/../../../../automake/compile.am
include_bspdir = $(includedir)/bsp
+include_libcpudir = $(includedir)/libcpu
include_bsp_ti_herculesdir = $(includedir)/bsp/ti_herc
@@ -46,6 +47,8 @@ include_bsp_HEADERS += include/tms570-pinmux.h
include_bsp_HEADERS += include/tms570-pins.h
include_bsp_HEADERS += include/tms570ls3137zwt-pins.h
+include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
+
include_bsp_ti_hercules_HEADERS = include/ti_herc/reg_adc.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_ccmsr.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_crc.h
@@ -121,6 +124,8 @@ libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
libbsp_a_SOURCES += ../../shared/sbrk.c
libbsp_a_SOURCES += ../../shared/src/stackalloc.c
libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
+libbsp_a_SOURCES += ../shared/arm-cp15-set-exception-handler.c
+libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c
# Startup
libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S
diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am
index 09b6c77..f996f8d 100644
--- a/c/src/lib/libbsp/arm/tms570/preinstall.am
+++ b/c/src/lib/libbsp/arm/tms570/preinstall.am
@@ -33,6 +33,11 @@ $(PROJECT_INCLUDE)/bsp/$(dirstamp):
@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
+ @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
+ @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+
$(PROJECT_INCLUDE)/bsp/ti_herc/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp/ti_herc
@: > $(PROJECT_INCLUDE)/bsp/ti_herc/$(dirstamp)
@@ -126,6 +131,10 @@ $(PROJECT_INCLUDE)/bsp/tms570ls3137zwt-pins.h: include/tms570ls3137zwt-pins.h $(
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tms570ls3137zwt-pins.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tms570ls3137zwt-pins.h
+$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
+
$(PROJECT_INCLUDE)/bsp/ti_herc/reg_adc.h: include/ti_herc/reg_adc.h $(PROJECT_INCLUDE)/bsp/ti_herc/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ti_herc/reg_adc.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ti_herc/reg_adc.h
diff --git a/c/src/lib/libcpu/arm/configure.ac b/c/src/lib/libcpu/arm/configure.ac
index 2b1ac61..81edac8 100644
--- a/c/src/lib/libcpu/arm/configure.ac
+++ b/c/src/lib/libcpu/arm/configure.ac
@@ -19,7 +19,8 @@ AM_PROG_CC_C_O
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
-AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "at91rm9200" || \
+AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "arm1136" || \
+ test "$RTEMS_CPU_MODEL" = "at91rm9200" || \
test "$RTEMS_CPU_MODEL" = "mc9328mxl" || \
test "$RTEMS_CPU_MODEL" = "s3c2410" || \
test "$RTEMS_CPU_MODEL" = "s3c2400" || \
diff --git a/cpukit/libdebugger/rtems-debugger-arm.c b/cpukit/libdebugger/rtems-debugger-arm.c
index 945dc9c..8126c14 100644
--- a/cpukit/libdebugger/rtems-debugger-arm.c
+++ b/cpukit/libdebugger/rtems-debugger-arm.c
@@ -36,7 +36,6 @@
#include <rtems.h>
#include <rtems/score/threadimpl.h>
-#include <libcpu/arm-cp15.h>
#include <bsp/linker-symbols.h>
#include "rtems-debugger-target.h"
@@ -47,6 +46,60 @@
#endif
/*
+ * ARM Variant controls.
+ */
+#if defined(__ARM_ARCH_7A__) || \
+ defined(__ARM_ARCH_7R__)
+ #define ARM_CP15 1
+#endif
+
+#if (defined(__ARM_ARCH_7M__) || \
+ defined(__ARM_ARCH_7EM__))
+ #define ARM_THUMB_ONLY 1
+#else
+ #define ARM_THUMB_ONLY 0
+#endif
+
+#if defined(ARM_MULTILIB_ARCH_V4)
+ #define ARM_PSR_HAS_INT_MASK 1
+ #define ARM_PSR_HAS_THUMB 1
+#else
+ #define ARM_PSR_HAS_INT_MASK 0
+ #define ARM_PSR_HAS_THUMB 0
+#endif
+
+#if ARM_CP15
+#include <libcpu/arm-cp15.h>
+#endif
+
+/**
+ * If thumb build of code switch the asm to thumb as required.
+ *
+ * If the variant only supports thumb insturctions disable the support.
+ */
+#define ARM_SWITCH_REG uint32_t arm_switch_reg
+#define ARM_SWITCH_REG_ASM [arm_switch_reg] "=&r" (arm_switch_reg)
+#if !ARM_THUMB_ONLY && defined(__thumb__)
+ #define ASM_ARM_MODE ".align 2\nbx pc\n.arm\n"
+ #define ASM_THUMB_MODE "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
+#else
+ #define ASM_ARM_MODE
+ #define ASM_THUMB_MODE
+#endif
+
+/*
+ * Hack to work around ARMv7-M not having a the T and I bits in the PSR.
+ *
+ * This needs to be fixed when real support for this ARM variant is added.
+ */
+#if !defined(ARM_PSR_I)
+ #define ARM_PSR_I 0
+#endif
+#if !defined(ARM_PSR_T)
+ #define ARM_PSR_T 0
+#endif
+
+/*
* The ARM has 2 interrupt bits.
*/
#define CPSR_IRQ_DISABLE 0x80 /* IIQ disabled when 1 */
@@ -112,7 +165,7 @@
#ifdef __thumb__
static const uint8_t breakpoint[2] = { 0x55, 0xbe };
#else
- static const uint8_t breakpoint[4] = { 0x75, 0xe0a, 0x20, 0xe1 };
+ static const uint8_t breakpoint[4] = { 0x75, 0xe0, 0x20, 0xe1 };
#endif
/**
@@ -121,11 +174,6 @@
RTEMS_INTERRUPT_LOCK_DEFINE(static, target_lock, "target_lock")
/**
- * The init value for the text section.
- */
-static uint32_t text_section_flags;
-
-/**
* Is a session active?
*/
static bool debug_session_active;
@@ -225,22 +273,24 @@ mode_label(int mode)
#define ARM_CP14_WRITE(_val, _CRn, _CRm, _opc2) \
do { \
- ARM_SWITCH_REGISTERS; \
+ ARM_SWITCH_REG; \
asm volatile( \
- ARM_SWITCH_TO_ARM \
+ ASM_ARM_MODE \
ARM_CP14_INSTR(mcr, val, _CRn, _CRm, _opc2) \
- ARM_SWITCH_BACK \
- : ARM_SWITCH_OUTPUT : [val] "r" (_val)); \
+ ASM_THUMB_MODE \
+ : ARM_SWITCH_REG_ASM \
+ : [val] "r" (_val)); \
} while (0)
#define ARM_CP14_READ(_val, _CRn, _CRm, _opc2) \
do { \
- ARM_SWITCH_REGISTERS; \
+ ARM_SWITCH_REG; \
asm volatile( \
- ARM_SWITCH_TO_ARM \
+ ASM_ARM_MODE \
ARM_CP14_INSTR(mrc, val, _CRn, _CRm, _opc2) \
- ARM_SWITCH_BACK \
- : [val] "=&r" (_val) ARM_SWITCH_ADDITIONAL_OUTPUT); \
+ ASM_THUMB_MODE \
+ : ARM_SWITCH_REG_ASM, \
+ [val] "=&r" (_val)); \
} while (0)
static int
@@ -557,19 +607,6 @@ target_exception(CPU_Exception_frame* frame)
}
/**
- * If thumb build of code switch the asm to thumb as required.
- */
-#ifdef __thumb__
- #define ASM_ARM_MODE ".align 2\nbx pc\n.arm\n"
- #define ASM_THUMB_MODE "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
- #define ARM_SWITCH_REG uint32_t arm_switch_reg
-#else
- #define ASM_ARM_MODE
- #define ASM_THUMB_MODE
- #define ARM_SWITCH_REG
-#endif
-
-/**
* Exception stack frame size.
*
* The size is the exception stack frame plus the CPSR from the exception. We
@@ -607,7 +644,7 @@ target_exception(CPU_Exception_frame* frame)
"sub sp, #4\n" \
"str lr, [sp]\n" /* save the link reg */ \
ASM_THUMB_MODE \
- : [arm_switch_reg] "=&r" (arm_switch_reg) \
+ : ARM_SWITCH_REG_ASM \
: [frame_size] "i" (EXCEPTION_FRAME_SIZE) \
: "memory")
@@ -682,7 +719,7 @@ target_exception(CPU_Exception_frame* frame)
EXCEPTION_ENTRY_FPU(frame_fpu_size) \
"msr cpsr, r1\n" /* restore the irq mask */ \
ASM_THUMB_MODE \
- : [arm_switch_reg] "=&r" (arm_switch_reg), \
+ : ARM_SWITCH_REG_ASM, \
[o_frame] "=r" (_frame) \
: [psr_t] "i" (ARM_PSR_T), \
[psr_i] "i" (ARM_PSR_I), \
@@ -755,7 +792,7 @@ target_exception(CPU_Exception_frame* frame)
"mov lr, r5\n" /* get the PC */ \
"str lr, [sp]\n" /* save the link reg */ \
ASM_THUMB_MODE \
- : [arm_switch_reg] "=&r" (arm_switch_reg) \
+ : ARM_SWITCH_REG_ASM \
: [psr_i] "i" (ARM_PSR_I), \
[r0_r12_size] "i" (13 * sizeof(uint32_t)), \
[frame_cpsr] "i" (EXCEPTION_FRAME_SIZE - sizeof(uint32_t)), \
@@ -821,10 +858,14 @@ target_exception_prefetch_abort(void)
EXCEPTION_ENTRY_EXC();
arm_debug_break_unload();
EXCEPTION_ENTRY_THREAD(frame);
+#if ARM_CP15
if ((arm_cp15_get_instruction_fault_status() & 0x1f) == 0x02)
frame->vector = 2;
else
frame->vector = 3;
+#else
+ frame->vector = 3;
+#endif
target_exception(frame);
EXCEPTION_EXIT_THREAD(frame);
arm_debug_break_load();
@@ -846,18 +887,19 @@ target_exception_data_abort(void)
EXCEPTION_EXIT_EXC();
}
-int
-rtems_debugger_target_enable(void)
+#if ARM_CP15
+/**
+ * The init value for the text section.
+ */
+static uint32_t text_section_flags;
+
+static void
+rtems_debugger_target_set_vectors(void)
{
- rtems_interrupt_lock_context lock_context;
- void* text_begin;
- void* text_end;
- debug_session_active = true;
+ void* text_begin;
+ void* text_end;
text_begin = &bsp_section_text_begin[0];
text_end = &bsp_section_text_end[0];
- rtems_interrupt_lock_acquire(&target_lock, &lock_context);
- arm_debug_break_unload();
- arm_debug_break_clear();
text_section_flags =
arm_cp15_set_translation_table_entries(text_begin,
text_end,
@@ -870,6 +912,34 @@ rtems_debugger_target_enable(void)
target_exception_prefetch_abort);
arm_cp15_set_exception_handler(ARM_EXCEPTION_DATA_ABORT,
target_exception_data_abort);
+}
+#else
+static void
+rtems_debugger_target_set_vectors(void)
+{
+ /*
+ * Dummy, please add support for your ARM variant.
+ */
+ void* ui = target_exception_undefined_instruction;
+ void* sc = target_exception_supervisor_call;
+ void* pa = target_exception_prefetch_abort;
+ void* da = target_exception_data_abort;
+ (void) ui;
+ (void) sc;
+ (void) pa;
+ (void) da;
+}
+#endif
+
+int
+rtems_debugger_target_enable(void)
+{
+ rtems_interrupt_lock_context lock_context;
+ debug_session_active = true;
+ rtems_interrupt_lock_acquire(&target_lock, &lock_context);
+ arm_debug_break_unload();
+ arm_debug_break_clear();
+ rtems_debugger_target_set_vectors();
rtems_interrupt_lock_release(&target_lock, &lock_context);
return 0;
}
@@ -1121,6 +1191,7 @@ rtems_debugger_target_thread_stepping(rtems_debugger_thread* thread)
/*
* Save the interrupt state before stepping if set.
*/
+#if ARM_PSR_HAS_INT_MASK
if ((FRAME_SR & CPSR_INTS_MASK) != 0) {
uint32_t int_state;
int_state =
@@ -1131,6 +1202,7 @@ rtems_debugger_target_thread_stepping(rtems_debugger_thread* thread)
* Mask the interrupt when stepping.
*/
FRAME_SR |= CPSR_INTS_MASK;
+#endif
break;
}
}
@@ -1142,6 +1214,7 @@ int
rtems_debugger_target_exception_to_signal(CPU_Exception_frame* frame)
{
int sig = RTEMS_DEBUGGER_SIGNAL_HUP;
+#if defined(ARM_EXCEPTION_RESET)
switch (frame->vector) {
case ARM_EXCEPTION_RESET:
case ARM_EXCEPTION_SWI:
@@ -1164,6 +1237,7 @@ rtems_debugger_target_exception_to_signal(CPU_Exception_frame* frame)
default:
break;
}
+#endif
return sig;
}