summaryrefslogtreecommitdiffstats
path: root/spec/build/bsps/arm/xilinx-zynqmp
diff options
context:
space:
mode:
Diffstat (limited to 'spec/build/bsps/arm/xilinx-zynqmp')
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/abi.yml16
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml13
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml2
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml2
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml16
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml16
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml16
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml11
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml8
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml8
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml8
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml8
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml8
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml8
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml13
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optramori.yml8
-rw-r--r--spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml8
17 files changed, 86 insertions, 83 deletions
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/abi.yml b/spec/build/bsps/arm/xilinx-zynqmp/abi.yml
index 09f7d50a20..3945b46365 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/abi.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/abi.yml
@@ -5,15 +5,15 @@ actions:
- env-append: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
-- -march=armv7-a
-- -mthumb
-- -mfpu=neon
-- -mfloat-abi=hard
-- -mtune=cortex-a53
-default-by-family: []
-default-by-variant: []
+- enabled-by: true
+ value:
+ - -march=armv7-a
+ - -mthumb
+ - -mfpu=neon
+ - -mfloat-abi=hard
+ - -mtune=cortex-a53
description: |
ABI flags
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
index 21a21f3812..d947123247 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml
@@ -4,7 +4,7 @@ bsp: xilinx_zynqmp_ultra96
build-type: bsp
cflags: []
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
cppflags: []
enabled-by: true
family: xilinx-zynqmp
@@ -13,7 +13,6 @@ install:
- destination: ${BSP_INCLUDEDIR}
source:
- bsps/arm/xilinx-zynqmp/include/bsp.h
- - bsps/arm/xilinx-zynqmp/include/tm27.h
- destination: ${BSP_INCLUDEDIR}/bsp
source:
- bsps/arm/xilinx-zynqmp/include/bsp/irq.h
@@ -44,8 +43,6 @@ links:
- role: build-dependency
uid: optconirq
- role: build-dependency
- uid: ../../optconminor
-- role: build-dependency
uid: optint0len
- role: build-dependency
uid: optint0ori
@@ -74,6 +71,8 @@ links:
- role: build-dependency
uid: ../../objdevspixil
- role: build-dependency
+ uid: ../../objmem
+- role: build-dependency
uid: ../../opto2
- role: build-dependency
uid: linkcmds
@@ -81,23 +80,25 @@ links:
uid: ../../bspopts
source:
- bsps/arm/shared/cache/cache-cp15.c
+- bsps/arm/shared/cache/cache-v7ar-disable-data.S
- bsps/arm/shared/clock/arm-generic-timer-aarch32.c
- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
- bsps/arm/shared/start/bsp-start-memcpy.S
+- bsps/arm/shared/start/bspstarthook0-empty.c
- bsps/arm/xilinx-zynqmp/console/console-config.c
- bsps/arm/xilinx-zynqmp/start/bspreset.c
- bsps/arm/xilinx-zynqmp/start/bspstart.c
- bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
- bsps/arm/xilinx-zynqmp/start/bspstartmmu.c
-- bsps/shared/dev/btimer/btimer-stub.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
- bsps/shared/dev/clock/arm-generic-timer.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c
- bsps/shared/dev/irq/arm-gicv2.c
+- bsps/shared/dev/irq/arm-gicv2-zynqmp.c
- bsps/shared/dev/serial/console-termios.c
- bsps/shared/irq/irq-default-handler.c
- bsps/shared/start/bspfatal-default.c
-- bsps/shared/start/bspgetworkarea-default.c
- bsps/shared/start/gettargethash-default.c
- bsps/shared/start/sbrk.c
- bsps/shared/start/stackalloc.c
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml b/spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml
index 77bd5fb763..f23369b1de 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/linkcmds.yml
@@ -38,7 +38,7 @@ content: |
INCLUDE linkcmds.armv4
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
enabled-by: true
install-path: ${BSP_LIBDIR}
links: []
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml b/spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml
index e8b954b5cb..8ae414e9b6 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/objsmp.yml
@@ -2,7 +2,7 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
build-type: objects
cflags: []
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
cppflags: []
cxxflags: []
enabled-by:
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml b/spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml
index ec036ec2dd..01b4959995 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optcachedata.yml
@@ -4,13 +4,15 @@ actions:
- define-condition: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-family: []
-default-by-variant:
-- value: false
- variants:
- - arm/.*qemu
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+ - arm/lm3s6965_qemu
+ - arm/realview_pbx_a9_qemu
+ - arm/xilinx_zynq_a9_qemu
+ value: false
+- enabled-by: true
+ value: true
description: |
enable data cache
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml b/spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml
index 88c541abf0..62607fb235 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optcacheinst.yml
@@ -4,13 +4,15 @@ actions:
- define-condition: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-family: []
-default-by-variant:
-- value: false
- variants:
- - arm/.*qemu
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+ - arm/lm3s6965_qemu
+ - arm/realview_pbx_a9_qemu
+ - arm/xilinx_zynq_a9_qemu
+ value: false
+- enabled-by: true
+ value: true
description: |
enable instruction cache
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml b/spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml
index 661d94afe3..f0b83e1402 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optclkfastidle.yml
@@ -4,13 +4,15 @@ actions:
- define-condition: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: false
-default-by-family: []
-default-by-variant:
-- value: true
- variants:
- - arm/.*qemu
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+ - arm/lm3s6965_qemu
+ - arm/realview_pbx_a9_qemu
+ - arm/xilinx_zynq_a9_qemu
+ value: true
+- enabled-by: true
+ value: false
description: |
This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times.
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml b/spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml
index fc066c3540..4ee4e63dbb 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optclkuart.yml
@@ -4,13 +4,10 @@ actions:
- define: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 100000000
-default-by-family: []
-default-by-variant:
-- value: 100000000
- variants:
- - arm/xilinx_zynqmp_ultra96.*
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 100000000
description: |
Zynq UART clock frequency in Hz
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml b/spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml
index 130065723c..e9bc6bedc6 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optconirq.yml
@@ -4,10 +4,10 @@ actions:
- define-condition: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-family: []
-default-by-variant: []
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: true
description: |
use interrupt driven mode for console devices (used by default)
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml b/spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml
index 4fdd2c8b0b..dacb8d2541 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optint0len.yml
@@ -6,10 +6,10 @@ actions:
- format-and-define: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 196608
-default-by-family: []
-default-by-variant: []
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x00030000
description: ''
enabled-by: true
format: '{:#010x}'
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml b/spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml
index d0c96913a8..8f83ceeb07 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optint0ori.yml
@@ -6,10 +6,10 @@ actions:
- format-and-define: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 0
-default-by-family: []
-default-by-variant: []
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x00000000
description: ''
enabled-by: true
format: '{:#010x}'
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml b/spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml
index 1e3cc21159..6d0576bb24 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optint1len.yml
@@ -6,10 +6,10 @@ actions:
- format-and-define: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 65024
-default-by-family: []
-default-by-variant: []
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x0000fe00
description: ''
enabled-by: true
format: '{:#010x}'
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml b/spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml
index 3bf7c4875d..04c44dedff 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optint1ori.yml
@@ -6,10 +6,10 @@ actions:
- format-and-define: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 4294901760
-default-by-family: []
-default-by-variant: []
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0xffff0000
description: ''
enabled-by: true
format: '{:#010x}'
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml b/spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml
index cc665477e4..b82dfa7410 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optnocachelen.yml
@@ -6,10 +6,10 @@ actions:
- format-and-define: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 1048576
-default-by-family: []
-default-by-variant: []
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x00100000
description: |
length of nocache RAM region
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml b/spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml
index 263a421582..1cdb31d4d7 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optramlen.yml
@@ -6,13 +6,12 @@ actions:
- format-and-define: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 268435456
-default-by-family: []
-default-by-variant:
-- value: 2147483648
- variants:
- - arm/xilinx_zynqmp_ultra96
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: arm/xilinx_zynqmp_ultra96
+ value: 0x80000000
+- enabled-by: true
+ value: 0x10000000
description: |
override a BSP's default RAM length
enabled-by: true
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optramori.yml b/spec/build/bsps/arm/xilinx-zynqmp/optramori.yml
index 359019bd69..082be7e826 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optramori.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optramori.yml
@@ -7,10 +7,10 @@ actions:
- format-and-define: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 1048576
-default-by-family: []
-default-by-variant: []
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: 0x00100000
description: ''
enabled-by: true
format: '{:#010x}'
diff --git a/spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml b/spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml
index 52f469c2d9..206a6f2801 100644
--- a/spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml
+++ b/spec/build/bsps/arm/xilinx-zynqmp/optresetvec.yml
@@ -4,10 +4,10 @@ actions:
- define-condition: null
build-type: option
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: false
-default-by-family: []
-default-by-variant: []
+- Copyright (C) 2020 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+ value: false
description: |
reset vector address for BSP start
enabled-by: true