diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S index 3165d6b625..dd6f694cc8 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S @@ -78,14 +78,14 @@ ppc_exc_wrap_async_normal: mr FRAME_REGISTER, r1 /* Load ISR nest level and thread dispatch disable level */ - PPC_EXC_GPR_STORE ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) + PPC_GPR_STORE ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) lis ISR_NEST_HADDR_REGISTER, ISR_NEST_LEVEL@ha - PPC_EXC_GPR_STORE ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) + PPC_GPR_STORE ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) lwz ISR_NEST_REGISTER, ISR_NEST_LEVEL@l(ISR_NEST_HADDR_REGISTER) - PPC_EXC_GPR_STORE DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) + PPC_GPR_STORE DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) lwz DISPATCH_LEVEL_REGISTER, _Thread_Dispatch_disable_level@sdarel(r13) - PPC_EXC_GPR_STORE SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) + PPC_GPR_STORE SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) #ifdef __SPE__ /* @@ -96,7 +96,7 @@ ppc_exc_wrap_async_normal: stw SCRATCH_0_REGISTER, VECTOR_OFFSET(r1) #endif - PPC_EXC_GPR_STORE HANDLER_REGISTER, HANDLER_OFFSET(r1) + PPC_GPR_STORE HANDLER_REGISTER, HANDLER_OFFSET(r1) /* * Load the handler address. Get the handler table index from the @@ -109,11 +109,11 @@ ppc_exc_wrap_async_normal: ori HANDLER_REGISTER, HANDLER_REGISTER, ppc_exc_handler_table@l lwzx HANDLER_REGISTER, HANDLER_REGISTER, SCRATCH_0_REGISTER - PPC_EXC_GPR_STORE SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) - PPC_EXC_GPR_STORE SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) - PPC_EXC_GPR_STORE SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) - PPC_EXC_GPR_STORE SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) - PPC_EXC_GPR_STORE SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) + PPC_GPR_STORE SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) + PPC_GPR_STORE SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) + PPC_GPR_STORE SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) + PPC_GPR_STORE SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) + PPC_GPR_STORE SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) /* Save SRR0, SRR1, CR, CTR, XER, and LR */ mfsrr0 SCRATCH_0_REGISTER @@ -197,35 +197,35 @@ thread_dispatching_done: lwz SCRATCH_4_REGISTER, EXC_XER_OFFSET(r1) lwz SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) - PPC_EXC_GPR_LOAD VECTOR_REGISTER, VECTOR_OFFSET(r1) - PPC_EXC_GPR_LOAD ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) - PPC_EXC_GPR_LOAD ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) + PPC_GPR_LOAD VECTOR_REGISTER, VECTOR_OFFSET(r1) + PPC_GPR_LOAD ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) + PPC_GPR_LOAD ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) #ifdef __SPE__ /* Restore SPEFSCR */ mtspr FSL_EIS_SPEFSCR, DISPATCH_LEVEL_REGISTER #endif - PPC_EXC_GPR_LOAD DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) + PPC_GPR_LOAD DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) #ifdef __SPE__ /* Restore ACC */ evmra HANDLER_REGISTER, HANDLER_REGISTER #endif - PPC_EXC_GPR_LOAD HANDLER_REGISTER, HANDLER_OFFSET(r1) + PPC_GPR_LOAD HANDLER_REGISTER, HANDLER_OFFSET(r1) /* Restore SRR0, SRR1, CR, CTR, XER, and LR */ mtsrr0 SCRATCH_0_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) mtsrr1 SCRATCH_1_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) mtcr SCRATCH_2_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) mtctr SCRATCH_3_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) mtxer SCRATCH_4_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) mtlr SCRATCH_5_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) /* Pop stack */ addi r1, r1, PPC_EXC_MINIMAL_FRAME_SIZE |