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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-05-18 15:47:23 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2012-06-04 09:54:31 +0200 |
| commit | 1869bb7101de25205f325287419aaa25a13143c7 (patch) | |
| tree | 99dd5d871ed47673a9e95a9ba5f8d5ff791e31a3 /c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S | |
| parent | Fix C files which had two semi-colons at EOL (diff) | |
| download | rtems-1869bb7101de25205f325287419aaa25a13143c7.tar.bz2 | |
powerpc: Simplify context switch
PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers. The SPE context switch code has been merged
with the standard context switch code. The context switch may use cache
operations to increase the performance. It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This
increases the overall memory size of the context area in the thread
control block slightly. The general-purpose registers GPR2 and GPR13
are no longer part of the context. The BSP must initialize these
registers during startup (usually initialized by the __eabi() function).
The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.
The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch. This should be not
necessary in most cases.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S index 3165d6b625..dd6f694cc8 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S @@ -78,14 +78,14 @@ ppc_exc_wrap_async_normal: mr FRAME_REGISTER, r1 /* Load ISR nest level and thread dispatch disable level */ - PPC_EXC_GPR_STORE ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) + PPC_GPR_STORE ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) lis ISR_NEST_HADDR_REGISTER, ISR_NEST_LEVEL@ha - PPC_EXC_GPR_STORE ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) + PPC_GPR_STORE ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) lwz ISR_NEST_REGISTER, ISR_NEST_LEVEL@l(ISR_NEST_HADDR_REGISTER) - PPC_EXC_GPR_STORE DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) + PPC_GPR_STORE DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) lwz DISPATCH_LEVEL_REGISTER, _Thread_Dispatch_disable_level@sdarel(r13) - PPC_EXC_GPR_STORE SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) + PPC_GPR_STORE SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) #ifdef __SPE__ /* @@ -96,7 +96,7 @@ ppc_exc_wrap_async_normal: stw SCRATCH_0_REGISTER, VECTOR_OFFSET(r1) #endif - PPC_EXC_GPR_STORE HANDLER_REGISTER, HANDLER_OFFSET(r1) + PPC_GPR_STORE HANDLER_REGISTER, HANDLER_OFFSET(r1) /* * Load the handler address. Get the handler table index from the @@ -109,11 +109,11 @@ ppc_exc_wrap_async_normal: ori HANDLER_REGISTER, HANDLER_REGISTER, ppc_exc_handler_table@l lwzx HANDLER_REGISTER, HANDLER_REGISTER, SCRATCH_0_REGISTER - PPC_EXC_GPR_STORE SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) - PPC_EXC_GPR_STORE SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) - PPC_EXC_GPR_STORE SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) - PPC_EXC_GPR_STORE SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) - PPC_EXC_GPR_STORE SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) + PPC_GPR_STORE SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) + PPC_GPR_STORE SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) + PPC_GPR_STORE SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) + PPC_GPR_STORE SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) + PPC_GPR_STORE SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) /* Save SRR0, SRR1, CR, CTR, XER, and LR */ mfsrr0 SCRATCH_0_REGISTER @@ -197,35 +197,35 @@ thread_dispatching_done: lwz SCRATCH_4_REGISTER, EXC_XER_OFFSET(r1) lwz SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) - PPC_EXC_GPR_LOAD VECTOR_REGISTER, VECTOR_OFFSET(r1) - PPC_EXC_GPR_LOAD ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) - PPC_EXC_GPR_LOAD ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) + PPC_GPR_LOAD VECTOR_REGISTER, VECTOR_OFFSET(r1) + PPC_GPR_LOAD ISR_NEST_HADDR_REGISTER, ISR_NEST_HADDR_OFFSET(r1) + PPC_GPR_LOAD ISR_NEST_REGISTER, ISR_NEST_OFFSET(r1) #ifdef __SPE__ /* Restore SPEFSCR */ mtspr FSL_EIS_SPEFSCR, DISPATCH_LEVEL_REGISTER #endif - PPC_EXC_GPR_LOAD DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) + PPC_GPR_LOAD DISPATCH_LEVEL_REGISTER, DISPATCH_LEVEL_OFFSET(r1) #ifdef __SPE__ /* Restore ACC */ evmra HANDLER_REGISTER, HANDLER_REGISTER #endif - PPC_EXC_GPR_LOAD HANDLER_REGISTER, HANDLER_OFFSET(r1) + PPC_GPR_LOAD HANDLER_REGISTER, HANDLER_OFFSET(r1) /* Restore SRR0, SRR1, CR, CTR, XER, and LR */ mtsrr0 SCRATCH_0_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) mtsrr1 SCRATCH_1_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) mtcr SCRATCH_2_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) mtctr SCRATCH_3_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) mtxer SCRATCH_4_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) mtlr SCRATCH_5_REGISTER - PPC_EXC_GPR_LOAD SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) + PPC_GPR_LOAD SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) /* Pop stack */ addi r1, r1, PPC_EXC_MINIMAL_FRAME_SIZE |