diff options
Diffstat (limited to 'c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S')
| -rw-r--r-- | c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S b/c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S index 425faac9ab..7fde4078b3 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S @@ -6,11 +6,11 @@ // Do_func performs the unimplemented operation. The operation // to be performed is determined from the lower 7 bits of the // extension word (except in the case of fmovecr and fsincos). -// The opcode and tag bits form an index into a jump table in -// tbldo.sa. Cases of zero, infinity and NaN are handled in +// The opcode and tag bits form an index into a jump table in +// tbldo.sa. Cases of zero, infinity and NaN are handled in // do_func by forcing the default result. Normalized and // denormalized (there are no unnormalized numbers at this -// point) are passed onto the emulation code. +// point) are passed onto the emulation code. // // CMDREG1B and STAG are extracted from the fsave frame // and combined to form the table index. The function called @@ -24,8 +24,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. DO_FUNC: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -70,7 +70,7 @@ do_func: // directly. // bfextu CMDREG1B(%a6){#0:#6},%d0 //get opclass and src fields - cmpil #0x17,%d0 //if op class and size fields are $17, + cmpil #0x17,%d0 //if op class and size fields are $17, // ;it is FMOVECR; if not, continue bnes not_fmovecr jmp smovcr //fmovecr; jmp directly to emulation @@ -78,7 +78,7 @@ do_func: not_fmovecr: movew CMDREG1B(%a6),%d0 andl #0x7F,%d0 - cmpil #0x38,%d0 //if the extension is >= $38, + cmpil #0x38,%d0 //if the extension is >= $38, bge serror //it is illegal bfextu STAG(%a6){#0:#3},%d1 lsll #3,%d0 //make room for STAG @@ -113,7 +113,7 @@ ld_mzinx: bsr ld_mzero //if neg, load neg zero, return here bra t_inx2 //now, set the inx for the next inst // -// Load a signed zero to fp0; do not set inex2/ainex +// Load a signed zero to fp0; do not set inex2/ainex // .global szero szero: @@ -121,7 +121,7 @@ szero: bne ld_mzero //if neg, load neg zero bra ld_pzero //load positive zero // -// Load a signed infinity to fp0; do not set inex2/ainex +// Load a signed infinity to fp0; do not set inex2/ainex // .global sinf sinf: @@ -129,7 +129,7 @@ sinf: bne ld_minf //if negative branch bra ld_pinf // -// Load a signed one to fp0; do not set inex2/ainex +// Load a signed one to fp0; do not set inex2/ainex // .global sone sone: @@ -137,7 +137,7 @@ sone: bne ld_mone bra ld_pone // -// Load a signed pi/2 to fp0; do not set inex2/ainex +// Load a signed pi/2 to fp0; do not set inex2/ainex // .global spi_2 spi_2: @@ -162,13 +162,13 @@ sopr_inf: bne t_operr bra ld_pinf // -// FLOGNP1 +// FLOGNP1 // .global sslognp1 sslognp1: fmovemx (%a0),%fp0-%fp0 fcmpb #-1,%fp0 - fbgt slognp1 + fbgt slognp1 fbeq t_dz2 //if = -1, divide by zero exception fmovel #0,%FPSR //clr N flag bra t_operr //take care of operands < -1 @@ -188,7 +188,7 @@ setoxm1i: // .global sslogn sslogn: - btstb #sign_bit,LOCAL_EX(%a0) + btstb #sign_bit,LOCAL_EX(%a0) bne t_operr //take care of operands < 0 cmpiw #0x3fff,LOCAL_EX(%a0) //test for 1.0 input bne slogn @@ -201,7 +201,7 @@ sslogn: .global sslognd sslognd: - btstb #sign_bit,LOCAL_EX(%a0) + btstb #sign_bit,LOCAL_EX(%a0) beq slognd bra t_operr //take care of operands < 0 @@ -223,7 +223,7 @@ sslog10: .global sslog10d sslog10d: - btstb #sign_bit,LOCAL_EX(%a0) + btstb #sign_bit,LOCAL_EX(%a0) beq slog10d bra t_operr //take care of operands < 0 @@ -245,7 +245,7 @@ sslog2: .global sslog2d sslog2d: - btstb #sign_bit,LOCAL_EX(%a0) + btstb #sign_bit,LOCAL_EX(%a0) beq slog2d bra t_operr //take care of operands < 0 @@ -312,7 +312,7 @@ smod_zsn: btstl #7,%d0 //test if + or - beq ld_pzero //if pos then load +0 bra ld_mzero //else neg load -0 - + smod_fpn: moveb ETEMP(%a6),%d1 //get sign of src op moveb FPTEMP(%a6),%d0 //get sign of dst op @@ -329,7 +329,7 @@ smod_nrm: fmovel USER_FPCR(%a6),%fpcr //use user's rmode and precision fmovex FPTEMP(%a6),%fp0 //return dest to fp0 rts - + // // FREM // @@ -374,7 +374,7 @@ prem: lea premt,%a1 movel (%a1,%d1.w*4),%a1 jmp (%a1) - + srem_snan: bra src_nan srem_dnan: @@ -392,7 +392,7 @@ srem_zsn: btstl #7,%d0 //test if + or - beq ld_pzero //if pos then load +0 bra ld_mzero //else neg load -0 - + srem_fpn: moveb ETEMP(%a6),%d1 //get sign of src op moveb FPTEMP(%a6),%d0 //get sign of dst op @@ -500,7 +500,7 @@ ssincosnan: bsr sto_cos bra src_nan // -// This code forces default values for the zero, inf, and nan cases +// This code forces default values for the zero, inf, and nan cases // in the transcendentals code. The CC bits must be set in the // stacked FPSR to be correctly reported. // |