diff options
Diffstat (limited to 'c/src/lib/libbsp/sparc')
91 files changed, 27 insertions, 13251 deletions
diff --git a/c/src/lib/libbsp/sparc/Makefile.am b/c/src/lib/libbsp/sparc/Makefile.am index 30ea8497b5..7a23cbb3a8 100644 --- a/c/src/lib/libbsp/sparc/Makefile.am +++ b/c/src/lib/libbsp/sparc/Makefile.am @@ -191,3 +191,4 @@ EXTRA_DIST += shared/include/l4stat.h include $(top_srcdir)/../../../automake/subdirs.am include $(top_srcdir)/../../../automake/local.am +include $(srcdir)/../../../../../bsps/sparc/headers.am diff --git a/c/src/lib/libbsp/sparc/configure.ac b/c/src/lib/libbsp/sparc/configure.ac index a3adc185e0..29b7f8408d 100644 --- a/c/src/lib/libbsp/sparc/configure.ac +++ b/c/src/lib/libbsp/sparc/configure.ac @@ -5,6 +5,8 @@ AC_INIT([rtems-c-src-lib-libbsp-sparc], [_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([shared]) RTEMS_TOP(../../../../..) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP RTEMS_CANONICAL_TARGET_CPU AM_INIT_AUTOMAKE([no-define foreign 1.12.2]) @@ -12,6 +14,8 @@ AM_MAINTAINER_MODE RTEMS_ENV_RTEMSBSP RTEMS_PROJECT_ROOT +AC_SUBST(RTEMS_CPU) +AC_SUBST(RTEMS_BSP_FAMILIY) RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY]) diff --git a/c/src/lib/libbsp/sparc/erc32/Makefile.am b/c/src/lib/libbsp/sparc/erc32/Makefile.am index cf019faa95..cf499de0d5 100644 --- a/c/src/lib/libbsp/sparc/erc32/Makefile.am +++ b/c/src/lib/libbsp/sparc/erc32/Makefile.am @@ -4,27 +4,20 @@ EXTRA_DIST = include $(top_srcdir)/../../../../automake/compile.am include $(top_srcdir)/../../bsp.am -include_bspdir = $(includedir)/bsp +dist_project_lib_DATA = startup/bsp_specs -dist_project_lib_DATA = bsp_specs - -include_HEADERS = include/bsp.h -include_HEADERS += include/tm27.h - -nodist_include_HEADERS = include/bspopts.h -nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h DISTCLEANFILES = include/bspopts.h noinst_PROGRAMS = -include_HEADERS += include/erc32.h EXTRA_DIST += ../../sparc/shared/start/start.S start.$(OBJEXT): ../../sparc/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -dist_project_lib_DATA += startup/linkcmds ../shared/startup/linkcmds.base +project_lib_DATA += linkcmds +dist_project_lib_DATA += ../shared/startup/linkcmds.base noinst_LIBRARIES = libbsp.a libbsp_a_SOURCES = @@ -51,7 +44,6 @@ libbsp_a_SOURCES += ../../sparc/shared/cpu.c libbsp_a_SOURCES += ../../sparc/shared/irq_asm.S # gnatsupp libbsp_a_SOURCES += gnatsupp/gnatsupp.c ../../sparc/shared/gnatcommon.c -include_bsp_HEADERS = ../shared/include/gnatcommon.h # console libbsp_a_SOURCES += console/erc32_console.c ../../shared/console.c \ ../../shared/console_select.c ../../shared/console_control.c \ @@ -65,10 +57,6 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h libbsp_a_SOURCES += timer/timer.c # IRQ -include_bsp_HEADERS += \ - ../../shared/include/irq-generic.h \ - ../../shared/include/irq-info.h \ - include/bsp/irq.h libbsp_a_SOURCES += \ ../../sparc/shared/irq/irq-shared.c \ ../../sparc/shared/irq/bsp_isr_handler.c \ @@ -103,5 +91,5 @@ endif EXTRA_DIST += times -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../../automake/local.am +include $(srcdir)/../../../../../../bsps/sparc/erc32/headers.am diff --git a/c/src/lib/libbsp/sparc/erc32/configure.ac b/c/src/lib/libbsp/sparc/erc32/configure.ac index 566a959b10..6e58139f95 100644 --- a/c/src/lib/libbsp/sparc/erc32/configure.ac +++ b/c/src/lib/libbsp/sparc/erc32/configure.ac @@ -5,6 +5,9 @@ AC_INIT([rtems-c-src-lib-libbsp-sparc-erc32], [_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([make/custom/erc32.cfg]) RTEMS_TOP(../../../../../..) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP +RTEMS_BSP_LINKCMDS RTEMS_CANONICAL_TARGET_CPU AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp.h b/c/src/lib/libbsp/sparc/erc32/include/bsp.h deleted file mode 100644 index 71719f9cf3..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/include/bsp.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * @file - * - * @ingroup sparc_erc32 - * - * @brief Global BSP Definitions. - */ - -/* - * COPYRIGHT (c) 1989-2007. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef LIBBSP_SPARC_ERC32_BSP_H -#define LIBBSP_SPARC_ERC32_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <erc32.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup sparc_erc32 ERC32 Support - * - * @ingroup bsp_sparc - * - * @brief ERC32 Support Package - */ - -/* - * BSP provides its own Idle thread body - */ -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_erc32_sonic_driver_attach( - struct rtems_bsdnet_ifconfig *config -); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "sonic1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_erc32_sonic_driver_attach - -/* Constants */ - -/* - * Information placed in the linkcmds file. - */ - -extern int RAM_START; -extern int RAM_END; -extern int RAM_SIZE; - -extern int PROM_START; -extern int PROM_END; -extern int PROM_SIZE; - -extern int CLOCK_SPEED; - -extern int end; /* last address in the program */ - -/* functions */ - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -void BSP_fatal_exit(uint32_t error); - -void bsp_spurious_initialize( void ); - -/* Interrupt Service Routine (ISR) pointer */ -typedef void (*bsp_shared_isr)(void *arg); - -/* Initializes the Shared System Interrupt service */ -extern void BSP_shared_interrupt_init(void); - -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ -void bsp_isr_handler(rtems_vector_number vector); - -/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple - * interrupt handlers may use the same IRQ number, all ISRs will be called - * when an interrupt on that line is fired. - * - * Arguments - * irq System IRQ number - * info Optional Name of IRQ source - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_register - ( - int irq, - const char *info, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_install(irq, info, - RTEMS_INTERRUPT_SHARED, isr, arg); -} - -/* Unregister previously registered shared IRQ handler. - * - * Arguments - * irq System IRQ number - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_unregister - ( - int irq, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_remove(irq, isr, arg); -} - -/* Clear interrupt pending on IRQ controller, this is typically done on a - * level triggered interrupt source such as PCI to avoid taking double IRQs. - * In such a case the interrupt source must be cleared first on LEON, before - * acknowledging the IRQ with this function. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_clear(int irq); - -/* Enable Interrupt. This function will unmask the IRQ at the interrupt - * controller. This is normally done by _register(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_unmask(int irq); - -/* Disable Interrupt. This function will mask one IRQ at the interrupt - * controller. This is normally done by _unregister(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_mask(int irq); - -/* - * Delay for the specified number of microseconds. - */ -void rtems_bsp_delay(int usecs); - -/* - * Prototypes for methods used across file boundaries - */ -void console_outbyte_polled(int port, unsigned char ch); -int console_inbyte_nonblocking(int port); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp/irq.h b/c/src/lib/libbsp/sparc/erc32/include/bsp/irq.h deleted file mode 100644 index 7789c9f57d..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/include/bsp/irq.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * @file - * @ingroup sparc_erc32 - * @brief ERC32 generic shared IRQ setup - * - * Based on libbsp/shared/include/irq.h. - */ - -/* - * Copyright (c) 2012. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ERC32_IRQ_CONFIG_H -#define LIBBSP_ERC32_IRQ_CONFIG_H - -#include <rtems/score/processormask.h> - -#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_STD - -/* No extra check is needed */ -#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR - -RTEMS_INLINE_ROUTINE void bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -) -{ - (void) vector; - (void) affinity; -} - -RTEMS_INLINE_ROUTINE void bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -) -{ - (void) vector; - _Processor_mask_From_index( affinity, 0 ); -} - -#endif /* LIBBSP_ERC32_IRQ_CONFIG_H */ diff --git a/c/src/lib/libbsp/sparc/erc32/include/erc32.h b/c/src/lib/libbsp/sparc/erc32/include/erc32.h deleted file mode 100644 index 7db4a6c91b..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/include/erc32.h +++ /dev/null @@ -1,549 +0,0 @@ -/** - * @file - * @ingroup sparc_erc32 - * @brief Contains information pertaining to the ERC32 - */ - -/* erc32.h - * - * This include file contains information pertaining to the ERC32. - * The ERC32 is a custom SPARC V7 implementation based on the Cypress - * 601/602 chipset. This CPU has a number of on-board peripherals and - * was developed by the European Space Agency to target space applications. - * - * NOTE: Other than where absolutely required, this version currently - * supports only the peripherals and bits used by the basic board - * support package. This includes at least significant pieces of - * the following items: - * - * + UART Channels A and B - * + General Purpose Timer - * + Real Time Clock - * + Watchdog Timer (so it can be disabled) - * + Control Register (so powerdown mode can be enabled) - * + Memory Control Register - * + Interrupt Control - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef _INCLUDE_ERC32_h -#define _INCLUDE_ERC32_h - -#include <rtems/score/sparc.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Interrupt Sources - * - * The interrupt source numbers directly map to the trap type and to - * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - */ - -#define ERC32_INTERRUPT_MASKED_ERRORS 1 -#define ERC32_INTERRUPT_EXTERNAL_1 2 -#define ERC32_INTERRUPT_EXTERNAL_2 3 -#define ERC32_INTERRUPT_UART_A_RX_TX 4 -#define ERC32_INTERRUPT_UART_B_RX_TX 5 -#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6 -#define ERC32_INTERRUPT_UART_ERROR 7 -#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8 -#define ERC32_INTERRUPT_DMA_TIMEOUT 9 -#define ERC32_INTERRUPT_EXTERNAL_3 10 -#define ERC32_INTERRUPT_EXTERNAL_4 11 -#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12 -#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13 -#define ERC32_INTERRUPT_EXTERNAL_5 14 -#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15 - -#ifndef ASM - -/* - * Trap Types for on-chip peripherals - * - * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments - * - * NOTE: The priority level for each source corresponds to the least - * significant nibble of the trap type. - */ - -#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) - -#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10) - -#define ERC32_Is_MEC_Trap( _trap ) \ - ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \ - (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) ) - -/* - * Structure for ERC32 memory mapped registers. - * - * Source: Section 3.25.2 - Register Address Map - * - * NOTE: There is only one of these structures per CPU, its base address - * is 0x01f80000, and the variable MEC is placed there by the - * linkcmds file. - */ - -typedef struct { - volatile uint32_t Control; /* offset 0x00 */ - volatile uint32_t Software_Reset; /* offset 0x04 */ - volatile uint32_t Power_Down; /* offset 0x08 */ - volatile uint32_t Unimplemented_0; /* offset 0x0c */ - volatile uint32_t Memory_Configuration; /* offset 0x10 */ - volatile uint32_t IO_Configuration; /* offset 0x14 */ - volatile uint32_t Wait_State_Configuration; /* offset 0x18 */ - volatile uint32_t Unimplemented_1; /* offset 0x1c */ - volatile uint32_t Memory_Access_0; /* offset 0x20 */ - volatile uint32_t Memory_Access_1; /* offset 0x24 */ - volatile uint32_t Unimplemented_2[ 7 ]; /* offset 0x28 */ - volatile uint32_t Interrupt_Shape; /* offset 0x44 */ - volatile uint32_t Interrupt_Pending; /* offset 0x48 */ - volatile uint32_t Interrupt_Mask; /* offset 0x4c */ - volatile uint32_t Interrupt_Clear; /* offset 0x50 */ - volatile uint32_t Interrupt_Force; /* offset 0x54 */ - volatile uint32_t Unimplemented_3[ 2 ]; /* offset 0x58 */ - /* offset 0x60 */ - volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge; - volatile uint32_t Watchdog_Trap_Door_Set; /* offset 0x64 */ - volatile uint32_t Unimplemented_4[ 6 ]; /* offset 0x68 */ - volatile uint32_t Real_Time_Clock_Counter; /* offset 0x80 */ - volatile uint32_t Real_Time_Clock_Scalar; /* offset 0x84 */ - volatile uint32_t General_Purpose_Timer_Counter; /* offset 0x88 */ - volatile uint32_t General_Purpose_Timer_Scalar; /* offset 0x8c */ - volatile uint32_t Unimplemented_5[ 2 ]; /* offset 0x90 */ - volatile uint32_t Timer_Control; /* offset 0x98 */ - volatile uint32_t Unimplemented_6; /* offset 0x9c */ - volatile uint32_t System_Fault_Status; /* offset 0xa0 */ - volatile uint32_t First_Failing_Address; /* offset 0xa4 */ - volatile uint32_t First_Failing_Data; /* offset 0xa8 */ - volatile uint32_t First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */ - volatile uint32_t Error_and_Reset_Status; /* offset 0xb0 */ - volatile uint32_t Error_Mask; /* offset 0xb4 */ - volatile uint32_t Unimplemented_7[ 2 ]; /* offset 0xb8 */ - volatile uint32_t Debug_Control; /* offset 0xc0 */ - volatile uint32_t Breakpoint; /* offset 0xc4 */ - volatile uint32_t Watchpoint; /* offset 0xc8 */ - volatile uint32_t Unimplemented_8; /* offset 0xcc */ - volatile uint32_t Test_Control; /* offset 0xd0 */ - volatile uint32_t Test_Data; /* offset 0xd4 */ - volatile uint32_t Unimplemented_9[ 2 ]; /* offset 0xd8 */ - volatile uint32_t UART_Channel_A; /* offset 0xe0 */ - volatile uint32_t UART_Channel_B; /* offset 0xe4 */ - volatile uint32_t UART_Status; /* offset 0xe8 */ -} ERC32_Register_Map; - -#endif - -/* - * The following constants are intended to be used ONLY in assembly - * language files. - * - * NOTE: The intended style of usage is to load the address of MEC - * into a register and then use these as displacements from - * that register. - */ - -#ifdef ASM - -#define ERC32_MEC_CONTROL_OFFSET 0x00 -#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04 -#define ERC32_MEC_POWER_DOWN_OFFSET 0x08 -#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C -#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10 -#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14 -#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18 -#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C -#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20 -#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24 -#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28 -#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44 -#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48 -#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C -#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50 -#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54 -#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58 -#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60 -#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64 -#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C -#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80 -#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84 -#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88 -#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C -#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90 -#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98 -#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C -#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0 -#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4 -#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8 -#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC -#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0 -#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4 -#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8 -#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0 -#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4 -#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8 -#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC -#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0 -#define ERC32_MEC_TEST_DATA_OFFSET 0xD4 -#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8 -#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0 -#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4 -#define ERC32_MEC_UART_STATUS_OFFSET 0xE8 - -#endif - -/* - * The following defines the bits in the Configuration Register. - */ - -#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001 -#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001 -#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002 -#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002 -#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004 -#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004 -#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008 -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008 -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000 - -/* - * The following defines the bits in the Memory Configuration Register. - */ - -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00 -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 ) - -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000 -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 ) - -/* - * The following defines the bits in the Timer Control Register. - */ - -#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ - /* 0 = no function */ -#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start*/ - /* 0 = no function */ - -#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ - /* 0 = no function */ -#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/ - /* 0 = no function */ - -/* - * The following defines the bits in the UART Control Registers. - * - */ - -#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ - -/* - * The following defines the bits in the MEC UART Control Registers. - */ - -#define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */ -#define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ -#define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ -#define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */ -#define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */ -#define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */ -#define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */ -#define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */ -#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */ -#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */ -#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */ -#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */ - -#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0) -#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0) -#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0) -#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0) -#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0) -#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0) -#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0) -#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0) - -#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16) -#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16) -#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16) -#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16) -#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16) -#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16) -#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16) -#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16) - -#ifndef ASM - -/* - * This is used to manipulate the on-chip registers. - * - * The following symbol must be defined in the linkcmds file and point - * to the correct location. - */ - -extern ERC32_Register_Map ERC32_MEC; - -static __inline__ int bsp_irq_fixup(int irq) -{ - return irq; -} - -/* - * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - * - * NOTE: For operations which are not atomic, this code disables interrupts - * to guarantee there are no intervening accesses to the same register. - * The operations which read the register, modify the value and then - * store the result back are vulnerable. - */ - -#define ERC32_Clear_interrupt( _source ) \ - do { \ - ERC32_MEC.Interrupt_Clear = (1 << (_source)); \ - } while (0) - -#define ERC32_Force_interrupt( _source ) \ - do { \ - uint32_t _level; \ - \ - _level = sparc_disable_interrupts(); \ - ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \ - ERC32_MEC.Interrupt_Force = (1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Is_interrupt_pending( _source ) \ - (ERC32_MEC.Interrupt_Pending & (1 << (_source))) - -#define ERC32_Is_interrupt_masked( _source ) \ - (ERC32_MEC.Interrupt_Mask & (1 << (_source))) - -#define ERC32_Mask_interrupt( _source ) \ - do { \ - uint32_t _level; \ - \ - _level = sparc_disable_interrupts(); \ - ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Unmask_interrupt( _source ) \ - do { \ - uint32_t _level; \ - \ - _level = sparc_disable_interrupts(); \ - ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Disable_interrupt( _source, _previous ) \ - do { \ - uint32_t _level; \ - uint32_t _mask = 1 << (_source); \ - \ - _level = sparc_disable_interrupts(); \ - (_previous) = ERC32_MEC.Interrupt_Mask; \ - ERC32_MEC.Interrupt_Mask = _previous | _mask; \ - sparc_enable_interrupts( _level ); \ - (_previous) &= _mask; \ - } while (0) - -#define ERC32_Restore_interrupt( _source, _previous ) \ - do { \ - uint32_t _level; \ - uint32_t _mask = 1 << (_source); \ - \ - _level = sparc_disable_interrupts(); \ - ERC32_MEC.Interrupt_Mask = \ - (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -/* Make all SPARC BSPs have common macros for interrupt handling on local CPU */ -#define BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source) -#define BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source) -#define BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source) -#define BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source) -#define BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source) -#define BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source) -#define BSP_Disable_interrupt(_source, _previous) \ - ERC32_Disable_interrupt(_source, _prev) -#define BSP_Restore_interrupt(_source, _previous) \ - ERC32_Restore_interrupt(_source, _previous) - -/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ -#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ - BSP_Is_interrupt_masked(_source) -#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ - BSP_Unmask_interrupt(_source) -#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ - BSP_Mask_interrupt(_source) -#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ - BSP_Disable_interrupt(_source, _prev) -#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ - BSP_Cpu_Restore_interrupt(_source, _previous) - -/* - * The following macros attempt to hide the fact that the General Purpose - * Timer and Real Time Clock Timer share the Timer Control Register. Because - * the Timer Control Register is write only, we must mirror it in software - * and insure that writes to one timer do not alter the current settings - * and status of the other timer. - * - * This code promotes the view that the two timers are completely independent. - * By exclusively using the routines below to access the Timer Control - * Register, the application can view the system as having a General Purpose - * Timer Control Register and a Real Time Clock Timer Control Register - * rather than the single shared value. - * - * Each logical timer control register is organized as follows: - * - * D0 - Counter Reload - * 1 = reload counter at zero and restart - * 0 = stop counter at zero - * - * D1 - Counter Load - * 1 = load counter with preset value and restart - * 0 = no function - * - * D2 - Enable - * 1 = enable counting - * 0 = hold scaler and counter - * - * D3 - Scaler Load - * 1 = load scalar with preset value and restart - * 0 = no function - * - * To insure the management of the mirror is atomic, we disable interrupts - * around updates. - */ - -#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001 -#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 - -#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002 - -#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004 -#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 - -#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008 - -#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001 -#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004 - -#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F -#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005 - -extern uint32_t _ERC32_MEC_Timer_Control_Mirror; - -/* - * This macros manipulate the General Purpose Timer portion of the - * Timer Control register and promote the view that there are actually - * two independent Timer Control Registers. - */ - -#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \ - do { \ - uint32_t _level; \ - uint32_t _control; \ - uint32_t __value; \ - \ - __value = ((_value) & 0x0f); \ - _level = sparc_disable_interrupts(); \ - _control = _ERC32_MEC_Timer_Control_Mirror; \ - _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \ - _ERC32_MEC_Timer_Control_Mirror = _control | _value; \ - _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \ - _control |= __value; \ - /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ - ERC32_MEC.Timer_Control = _control; \ - sparc_enable_interrupts( _level ); \ - } while ( 0 ) - -#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \ - do { \ - (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \ - } while ( 0 ) - -/* - * This macros manipulate the Real Timer Clock Timer portion of the - * Timer Control register and promote the view that there are actually - * two independent Timer Control Registers. - */ - -#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \ - do { \ - uint32_t _level; \ - uint32_t _control; \ - uint32_t __value; \ - \ - __value = ((_value) & 0x0f) << 8; \ - _level = sparc_disable_interrupts(); \ - _control = _ERC32_MEC_Timer_Control_Mirror; \ - _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \ - _ERC32_MEC_Timer_Control_Mirror = _control | __value; \ - _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \ - _control |= __value; \ - /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ - ERC32_MEC.Timer_Control = _control; \ - sparc_enable_interrupts( _level ); \ - } while ( 0 ) - -#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \ - do { \ - (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \ - } while ( 0 ) - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* !_INCLUDE_ERC32_h */ diff --git a/c/src/lib/libbsp/sparc/erc32/include/tm27.h b/c/src/lib/libbsp/sparc/erc32/include/tm27.h deleted file mode 100644 index 958036fbf0..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/include/tm27.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * @file - * @ingroup sparc_erc32 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * COPYRIGHT (c) 2006. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Since the interrupt code for the SPARC supports both synchronous - * and asynchronous trap handlers, support for testing with both - * is included. - */ - -#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0 - -/* - * The synchronous trap is an arbitrarily chosen software trap. - */ - -#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1) - -#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); - -#define Cause_tm27_intr() \ - __asm__ volatile( "ta 0x10; nop " ); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/* - * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. - */ - -#else /* use a regular asynchronous trap */ - -#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1 -#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1) -#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) -#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); \ - set_vector( (handler), TEST_VECTOR2, 1 ); - -#define Cause_tm27_intr() \ - do { \ - ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \ - nop(); \ - nop(); \ - nop(); \ - } while (0) - -#define Clear_tm27_intr() \ - ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE ) - -#define Lower_tm27_intr() /* empty */ - -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/erc32/preinstall.am b/c/src/lib/libbsp/sparc/erc32/preinstall.am deleted file mode 100644 index 831c8e4169..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/preinstall.am +++ /dev/null @@ -1,87 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - -$(PROJECT_LIB)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_LIB) - @: > $(PROJECT_LIB)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs -PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs - -$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h - -$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h - -$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h - -$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h - -$(PROJECT_INCLUDE)/erc32.h: include/erc32.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/erc32.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/erc32.h - -$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) -TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) - -$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds -PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds - -$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base -PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base - -$(PROJECT_INCLUDE)/bsp/gnatcommon.h: ../shared/include/gnatcommon.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gnatcommon.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gnatcommon.h - -$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h - -$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h - -$(PROJECT_INCLUDE)/bsp/irq.h: include/bsp/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h - diff --git a/c/src/lib/libbsp/sparc/erc32/bsp_specs b/c/src/lib/libbsp/sparc/erc32/startup/bsp_specs index 87638cc027..87638cc027 100644 --- a/c/src/lib/libbsp/sparc/erc32/bsp_specs +++ b/c/src/lib/libbsp/sparc/erc32/startup/bsp_specs diff --git a/c/src/lib/libbsp/sparc/leon2/Makefile.am b/c/src/lib/libbsp/sparc/leon2/Makefile.am index 3a5845c8c9..1914c6956f 100644 --- a/c/src/lib/libbsp/sparc/leon2/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon2/Makefile.am @@ -4,31 +4,22 @@ EXTRA_DIST = include $(top_srcdir)/../../../../automake/compile.am include $(top_srcdir)/../../bsp.am -include_bspdir = $(includedir)/bsp +dist_project_lib_DATA = startup/bsp_specs -dist_project_lib_DATA = bsp_specs - -include_HEADERS = include/bsp.h -include_HEADERS += include/tm27.h -include_bsp_HEADERS = ../../sparc/shared/include/debug_defs.h - -nodist_include_HEADERS = include/bspopts.h -nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h DISTCLEANFILES = include/bspopts.h noinst_PROGRAMS = -include_HEADERS += include/leon.h EXTRA_DIST += ../../sparc/shared/start/start.S start.$(OBJEXT): ../../sparc/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) +project_lib_DATA += linkcmds dist_project_lib_DATA += ../shared/startup/linkcmds.base -dist_project_lib_DATA += startup/linkcmds -dist_project_lib_DATA += startup/linkcmds.leon2 dist_project_lib_DATA += startup/linkcmds.at697f +dist_project_lib_DATA += startup/linkcmds.leon2 noinst_LIBRARIES = libbsp.a libbsp_a_SOURCES = @@ -54,19 +45,13 @@ libbsp_a_SOURCES += ../../sparc/shared/cpu.c libbsp_a_SOURCES += ../../sparc/shared/irq_asm.S # gnatsupp libbsp_a_SOURCES += gnatsupp/gnatsupp.c ../../sparc/shared/gnatcommon.c -include_bsp_HEADERS += ../shared/include/gnatcommon.h # console libbsp_a_SOURCES += console/console.c console/debugputs.c # clock libbsp_a_SOURCES += clock/ckinit.c libbsp_a_SOURCES += ../../shared/clockdrv_shell.h # IRQ -include_bsp_HEADERS += ../../sparc/shared/include/genirq.h libbsp_a_SOURCES += ../../sparc/shared/irq/genirq.c -include_bsp_HEADERS += \ - ../../shared/include/irq-generic.h \ - ../../shared/include/irq-info.h \ - include/bsp/irq.h libbsp_a_SOURCES += \ ../../sparc/shared/irq/irq-shared.c \ ../../sparc/shared/irq/bsp_isr_handler.c \ @@ -78,10 +63,6 @@ libbsp_a_SOURCES += \ ../../shared/src/irq-shell.c # AMBA bus -include_HEADERS += ../../sparc/shared/include/ambapp.h -include_HEADERS += ../../sparc/shared/include/ambapp_ids.h -include_HEADERS += ../../sparc/shared/include/grlib.h -include_bsp_HEADERS += ../../sparc/shared/include/ahbstat.h libbsp_a_SOURCES += ../../sparc/shared/amba/ambapp.c libbsp_a_SOURCES += ../../sparc/shared/amba/ambapp_alloc.c libbsp_a_SOURCES += ../../sparc/shared/amba/ambapp_count.c @@ -95,17 +76,10 @@ libbsp_a_SOURCES += ../../sparc/shared/amba/ambapp_show.c libbsp_a_SOURCES += ../../sparc/shared/amba/ahbstat.c # Clock Driver and Timer Library -include_bsp_HEADERS += ../../sparc/shared/include/gptimer.h -include_bsp_HEADERS += ../../sparc/shared/include/tlib.h libbsp_a_SOURCES += ../../sparc/shared/timer/gptimer.c libbsp_a_SOURCES += ../../sparc/shared/timer/tlib.c # PCI -include_bsp_HEADERS += ../../sparc/shared/include/grpci.h -include_bsp_HEADERS += ../../sparc/shared/include/grpci2.h -include_bsp_HEADERS += ../../sparc/shared/include/grpci2dma.h -include_bsp_HEADERS += ../../sparc/shared/include/pcif.h -include_bsp_HEADERS += include/at697_pci.h libbsp_a_SOURCES += ../../sparc/shared/pci/grpci2.c libbsp_a_SOURCES += ../../sparc/shared/pci/grpci2dma.c libbsp_a_SOURCES += ../../sparc/shared/pci/grpci.c @@ -115,13 +89,6 @@ libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_be.c libbsp_a_SOURCES += pci/at697_pci.c # PCI target devices -include_bsp_HEADERS += ../../sparc/shared/include/gr_701.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_rasta_adcdac.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_rasta_io.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_rasta_spw_router.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_rasta_tmtc.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_leon4_n2x.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_cpci_gr740.h libbsp_a_SOURCES += ../../sparc/shared/pci/gr_701.c libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_adcdac.c libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_io.c @@ -131,104 +98,66 @@ libbsp_a_SOURCES += ../../sparc/shared/pci/gr_leon4_n2x.c libbsp_a_SOURCES += ../../sparc/shared/pci/gr_cpci_gr740.c # B1553BRM -include_bsp_HEADERS += ../../sparc/shared/include/b1553brm.h -include_bsp_HEADERS += ../../sparc/shared/include/b1553rt.h libbsp_a_SOURCES += ../../sparc/shared/1553/b1553brm.c libbsp_a_SOURCES += ../../sparc/shared/1553/b1553rt.c # GR1553B -include_bsp_HEADERS += ../../sparc/shared/include/gr1553b.h -include_bsp_HEADERS += ../../sparc/shared/include/gr1553bc.h -include_bsp_HEADERS += ../../sparc/shared/include/gr1553bc_list.h -include_bsp_HEADERS += ../../sparc/shared/include/gr1553bm.h -include_bsp_HEADERS += ../../sparc/shared/include/gr1553rt.h libbsp_a_SOURCES += ../../sparc/shared/1553/gr1553b.c libbsp_a_SOURCES += ../../sparc/shared/1553/gr1553bc.c libbsp_a_SOURCES += ../../sparc/shared/1553/gr1553bm.c libbsp_a_SOURCES += ../../sparc/shared/1553/gr1553rt.c # CAN -include_bsp_HEADERS += ../../sparc/shared/include/occan.h -include_bsp_HEADERS += ../../sparc/shared/include/grcan.h libbsp_a_SOURCES += ../../sparc/shared/can/occan.c \ ../../sparc/shared/can/grcan.c # SpaceWire if !HAS_SMP -include_bsp_HEADERS += ../../sparc/shared/include/grspw.h libbsp_a_SOURCES += ../../sparc/shared/spw/grspw.c endif -include_bsp_HEADERS += ../../sparc/shared/include/grspw_pkt.h -include_bsp_HEADERS += ../../sparc/shared/include/grspw_router.h libbsp_a_SOURCES += ../../sparc/shared/spw/grspw_pkt.c libbsp_a_SOURCES += ../../sparc/shared/spw/grspw_router.c # UART (RAW) -include_bsp_HEADERS += ../../sparc/shared/include/apbuart.h - # I2CMST -include_bsp_HEADERS += ../../sparc/shared/include/i2cmst.h libbsp_a_SOURCES += ../../sparc/shared/i2c/i2cmst.c # SPI -include_bsp_HEADERS += ../../sparc/shared/include/spictrl.h libbsp_a_SOURCES += ../../sparc/shared/spi/spictrl.c # TIME -include_bsp_HEADERS += ../../sparc/shared/include/spwcuc.h -include_bsp_HEADERS += ../../sparc/shared/include/grctm.h libbsp_a_SOURCES += ../../sparc/shared/time/spwcuc.c libbsp_a_SOURCES += ../../sparc/shared/time/grctm.c # GPIO -include_bsp_HEADERS += ../../sparc/shared/include/grgpio.h -include_bsp_HEADERS += ../../sparc/shared/include/gpiolib.h libbsp_a_SOURCES += ../../sparc/shared/gpio/grgpio.c libbsp_a_SOURCES += ../../sparc/shared/gpio/gpiolib.c # PWM -include_bsp_HEADERS += ../../sparc/shared/include/grpwm.h libbsp_a_SOURCES += ../../sparc/shared/pwm/grpwm.c # ADC and DAC -include_bsp_HEADERS += ../../sparc/shared/include/gradcdac.h libbsp_a_SOURCES += ../../sparc/shared/analog/gradcdac.c # Memory controllers libbsp_a_SOURCES += ../../sparc/shared/mem/mctrl.c -include_bsp_HEADERS += ../../sparc/shared/include/mctrl.h - # l2cache libbsp_a_SOURCES += ../../sparc/shared/l2c/l2c.c -include_bsp_HEADERS += ../../sparc/shared/include/l2c.h - # griommu libbsp_a_SOURCES += ../../sparc/shared/iommu/griommu.c -include_bsp_HEADERS += ../../sparc/shared/include/griommu.h - # timer libbsp_a_SOURCES += timer/timer.c # TM/TC -include_bsp_HEADERS += ../../sparc/shared/include/grtc.h -include_bsp_HEADERS += ../../sparc/shared/include/grtm.h libbsp_a_SOURCES += ../../sparc/shared/tmtc/grtc.c libbsp_a_SOURCES += ../../sparc/shared/tmtc/grtm.c # MEMSCRUB libbsp_a_SOURCES += ../../sparc/shared/scrub/memscrub.c -include_bsp_HEADERS += ../../sparc/shared/include/memscrub.h - # L4STAT libbsp_a_SOURCES += ../../sparc/shared/stat/l4stat.c -include_bsp_HEADERS += ../../sparc/shared/include/l4stat.h - # Driver Manager -include_drvmgrdir = $(includedir)/drvmgr -include_drvmgr_HEADERS = ../../sparc/shared/include/drvmgr/ambapp_bus.h -include_drvmgr_HEADERS += ../../sparc/shared/include/drvmgr/leon2_amba_bus.h -include_drvmgr_HEADERS += ../../sparc/shared/include/drvmgr/bspcommon.h libbsp_a_SOURCES += ../../sparc/shared/drvmgr/ambapp_bus.c libbsp_a_SOURCES += ../../sparc/shared/drvmgr/ambapp_bus_leon2.c libbsp_a_SOURCES += ../../sparc/shared/drvmgr/leon2_amba_bus.c @@ -258,13 +187,11 @@ endif if HAS_NETWORKING noinst_PROGRAMS += leon_greth.rel leon_greth_rel_SOURCES = ../../sparc/shared/net/greth.c -include_bsp_HEADERS += ../../sparc/shared/include/greth.h leon_greth_rel_CPPFLAGS = $(AM_CPPFLAGS) leon_greth_rel_CPPFLAGS += -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ leon_greth_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) # BSP Network configuration -include_bsp_HEADERS += ../../sparc/shared/include/network_interface_add.h libbsp_a_SOURCES += ../../sparc/shared/net/network_interface_add.c endif @@ -282,5 +209,5 @@ endif EXTRA_DIST += times -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../../automake/local.am +include $(srcdir)/../../../../../../bsps/sparc/leon2/headers.am diff --git a/c/src/lib/libbsp/sparc/leon2/configure.ac b/c/src/lib/libbsp/sparc/leon2/configure.ac index 5ca4a1353a..cb12706219 100644 --- a/c/src/lib/libbsp/sparc/leon2/configure.ac +++ b/c/src/lib/libbsp/sparc/leon2/configure.ac @@ -5,6 +5,9 @@ AC_INIT([rtems-c-src-lib-libbsp-sparc-leon2], [_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([make/custom/leon2.cfg]) RTEMS_TOP(../../../../../..) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP +RTEMS_BSP_LINKCMDS RTEMS_CANONICAL_TARGET_CPU AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) @@ -36,7 +39,6 @@ RTEMS_BSPOPTS_HELP([BSP_POWER_DOWN_AT_FATAL_HALT], error which will hand over to debugger, simulator, etc.]) RTEMS_BSP_CLEANUP_OPTIONS -RTEMS_BSP_LINKCMDS # Explicitly list all Makefiles here AC_CONFIG_FILES([Makefile]) diff --git a/c/src/lib/libbsp/sparc/leon2/include/at697_pci.h b/c/src/lib/libbsp/sparc/leon2/include/at697_pci.h deleted file mode 100644 index 9a511ec6f9..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/at697_pci.h +++ /dev/null @@ -1,26 +0,0 @@ -/* AT697 PCI host bridge driver - * - * COPYRIGHT (c) 2015. - * Cobham Gaisler. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef __AT697PCI_H__ -#define __AT697PCI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Register AT697 PCI host bridge driver to Driver Manager */ -void at697pci_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon2/include/bsp.h b/c/src/lib/libbsp/sparc/leon2/include/bsp.h deleted file mode 100644 index 2028ba0db3..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/bsp.h +++ /dev/null @@ -1,220 +0,0 @@ -/** - * @file - * - * @ingroup sparc_leon2 - * - * @brief Global BSP Definitions. - */ - -/* bsp.h - * - * This include file contains all SPARC simulator definitions. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef LIBBSP_SPARC_LEON2_BSP_H -#define LIBBSP_SPARC_LEON2_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <leon.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup sparc_leon2 LEON2 Support - * - * @ingroup bsp_sparc - * - * @brief LEON2 Support Package - * - */ - -/* SPARC CPU variant: LEON2 */ -#define LEON2 1 - -/* - * BSP provides its own Idle thread body - */ -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_leon_open_eth_driver_attach( - struct rtems_bsdnet_ifconfig *config -); -extern int rtems_smc91111_driver_attach_leon2( - struct rtems_bsdnet_ifconfig *config -); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "open_eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH \ - rtems_leon_open_eth_driver_attach -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \ - rtems_smc91111_driver_attach_leon2 - -#define HAS_SMC91111 - -/* Configure GRETH driver */ -#define GRETH_SUPPORTED -#define GRETH_MEM_LOAD(addr) leon_r32_no_cache((uintptr_t) addr) - -/* - * The synchronous trap is an arbitrarily chosen software trap. - */ - -extern int CPU_SPARC_HAS_SNOOPING; - -/* Constants */ - -/* - * Information placed in the linkcmds file. - */ - -extern int RAM_START; -extern int RAM_END; -extern int RAM_SIZE; - -extern int PROM_START; -extern int PROM_END; -extern int PROM_SIZE; - -extern int CLOCK_SPEED; - -extern int end; /* last address in the program */ - -/* miscellaneous stuff assumed to exist */ - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -void BSP_fatal_exit(uint32_t error); - -void bsp_spurious_initialize( void ); - -/* Interrupt Service Routine (ISR) pointer */ -typedef void (*bsp_shared_isr)(void *arg); - -/* Initializes the Shared System Interrupt service */ -extern void BSP_shared_interrupt_init(void); - -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ -void bsp_isr_handler(rtems_vector_number vector); - -/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple - * interrupt handlers may use the same IRQ number, all ISRs will be called - * when an interrupt on that line is fired. - * - * Arguments - * irq System IRQ number - * info Optional Name of IRQ source - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_register - ( - int irq, - const char *info, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_install(irq, info, - RTEMS_INTERRUPT_SHARED, isr, arg); -} - -/* Unregister previously registered shared IRQ handler. - * - * Arguments - * irq System IRQ number - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_unregister - ( - int irq, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_remove(irq, isr, arg); -} - -/* Clear interrupt pending on IRQ controller, this is typically done on a - * level triggered interrupt source such as PCI to avoid taking double IRQs. - * In such a case the interrupt source must be cleared first on LEON, before - * acknowledging the IRQ with this function. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_clear(int irq); - -/* Enable Interrupt. This function will unmask the IRQ at the interrupt - * controller. This is normally done by _register(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_unmask(int irq); - -/* Disable Interrupt. This function will mask one IRQ at the interrupt - * controller. This is normally done by _unregister(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_mask(int irq); - -/* - * Delay method - */ -void rtems_bsp_delay(int usecs); - -/* - * Prototypes for BSP methods that are used across file boundaries - */ -int cchip1_register(void); - -/* AT697 has PCI defined as big endian */ -#define BSP_PCI_BIG_ENDIAN - -/* Common driver build-time configurations. On small systems undefine - * [DRIVER]_INFO_AVAIL to avoid info routines get dragged in. It is good - * for debugging and printing information about the system, but makes the - * image bigger. - */ -#define AMBAPPBUS_INFO_AVAIL /* AMBAPP Bus driver */ -#define GPTIMER_INFO_AVAIL /* GPTIMER Timer driver */ -#define GRETH_INFO_AVAIL /* GRETH Ethernet driver */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon2/include/bsp/irq.h b/c/src/lib/libbsp/sparc/leon2/include/bsp/irq.h deleted file mode 100644 index 086bf253c4..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/bsp/irq.h +++ /dev/null @@ -1,28 +0,0 @@ -/** - * @file - * @ingroup sparc_leon2 - * @brief Interrupts definitions - * - * Based on libbsp/shared/include/irq.h. - */ - -/* - * Copyright (c) 2012. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_LEON2_IRQ_CONFIG_H -#define LIBBSP_LEON2_IRQ_CONFIG_H - -#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_STD - -/* No extra check is needed */ -#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR - -#endif /* LIBBSP_LEON2_IRQ_CONFIG_H */ diff --git a/c/src/lib/libbsp/sparc/leon2/include/leon.h b/c/src/lib/libbsp/sparc/leon2/include/leon.h deleted file mode 100644 index 7ec6b1dcf9..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/leon.h +++ /dev/null @@ -1,423 +0,0 @@ -/** - * @defgroup leon1 Leon-1 Handler - * @ingroup sparc_leon2 - * - * @file - * @ingroup leon1 - * @brief Handlers Leon-1 - * - * This include file contains information pertaining to the LEON-1. - * The LEON-1 is a custom SPARC V7 implementation. - * This CPU has a number of on-board peripherals and - * was developed by the European Space Agency to target space applications. - * - * NOTE: Other than where absolutely required, this version currently - * supports only the peripherals and bits used by the basic board - * support package. This includes at least significant pieces of - * the following items: - * - * + UART Channels A and B - * + Real Time Clock - * + Memory Control Register - * + Interrupt Control - * - */ - -/* - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to LEON implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef _INCLUDE_LEON_h -#define _INCLUDE_LEON_h - -#include <rtems/score/sparc.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Interrupt Sources - * - * The interrupt source numbers directly map to the trap type and to - * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - */ - -#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1 -#define LEON_INTERRUPT_UART_2_RX_TX 2 -#define LEON_INTERRUPT_UART_1_RX_TX 3 -#define LEON_INTERRUPT_EXTERNAL_0 4 -#define LEON_INTERRUPT_EXTERNAL_1 5 -#define LEON_INTERRUPT_EXTERNAL_2 6 -#define LEON_INTERRUPT_EXTERNAL_3 7 -#define LEON_INTERRUPT_TIMER1 8 -#define LEON_INTERRUPT_TIMER2 9 -#define LEON_INTERRUPT_EMPTY1 10 -#define LEON_INTERRUPT_EMPTY2 11 -#define LEON_INTERRUPT_EMPTY3 12 -#define LEON_INTERRUPT_EMPTY4 13 -#define LEON_INTERRUPT_EMPTY5 14 -#define LEON_INTERRUPT_EMPTY6 15 - -#ifndef ASM - -/* - * Trap Types for on-chip peripherals - * - * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments - * - * NOTE: The priority level for each source corresponds to the least - * significant nibble of the trap type. - */ - -#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) - -#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) - -#define LEON_INT_TRAP( _trap ) \ - ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \ - (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) ) - -/* - * Structure for LEON memory mapped registers. - * - * Source: Section 6.1 - On-chip registers - * - * NOTE: There is only one of these structures per CPU, its base address - * is 0x80000000, and the variable LEON_REG is placed there by the - * linkcmds file. - */ - -typedef struct { - volatile unsigned int Memory_Config_1; - volatile unsigned int Memory_Config_2; - volatile unsigned int Edac_Control; - volatile unsigned int Failed_Address; - volatile unsigned int Memory_Status; - volatile unsigned int Cache_Control; - volatile unsigned int Power_Down; - volatile unsigned int Write_Protection_1; - volatile unsigned int Write_Protection_2; - volatile unsigned int Leon_Configuration; - volatile unsigned int dummy2; - volatile unsigned int dummy3; - volatile unsigned int dummy4; - volatile unsigned int dummy5; - volatile unsigned int dummy6; - volatile unsigned int dummy7; - volatile unsigned int Timer_Counter_1; - volatile unsigned int Timer_Reload_1; - volatile unsigned int Timer_Control_1; - volatile unsigned int Watchdog; - volatile unsigned int Timer_Counter_2; - volatile unsigned int Timer_Reload_2; - volatile unsigned int Timer_Control_2; - volatile unsigned int dummy8; - volatile unsigned int Scaler_Counter; - volatile unsigned int Scaler_Reload; - volatile unsigned int dummy9; - volatile unsigned int dummy10; - volatile unsigned int UART_Channel_1; - volatile unsigned int UART_Status_1; - volatile unsigned int UART_Control_1; - volatile unsigned int UART_Scaler_1; - volatile unsigned int UART_Channel_2; - volatile unsigned int UART_Status_2; - volatile unsigned int UART_Control_2; - volatile unsigned int UART_Scaler_2; - volatile unsigned int Interrupt_Mask; - volatile unsigned int Interrupt_Pending; - volatile unsigned int Interrupt_Force; - volatile unsigned int Interrupt_Clear; - volatile unsigned int PIO_Data; - volatile unsigned int PIO_Direction; - volatile unsigned int PIO_Interrupt; -} LEON_Register_Map; - -#endif - -/* - * The following constants are intended to be used ONLY in assembly - * language files. - * - * NOTE: The intended style of usage is to load the address of LEON REGS - * into a register and then use these as displacements from - * that register. - */ - -#ifdef ASM - -#define LEON_REG_MEMCFG1_OFFSET 0x00 -#define LEON_REG_MEMCFG2_OFFSET 0x04 -#define LEON_REG_EDACCTRL_OFFSET 0x08 -#define LEON_REG_FAILADDR_OFFSET 0x0C -#define LEON_REG_MEMSTATUS_OFFSET 0x10 -#define LEON_REG_CACHECTRL_OFFSET 0x14 -#define LEON_REG_POWERDOWN_OFFSET 0x18 -#define LEON_REG_WRITEPROT1_OFFSET 0x1C -#define LEON_REG_WRITEPROT2_OFFSET 0x20 -#define LEON_REG_LEONCONF_OFFSET 0x24 -#define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28 -#define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C -#define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30 -#define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34 -#define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38 -#define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C -#define LEON_REG_TIMERCNT1_OFFSET 0x40 -#define LEON_REG_TIMERLOAD1_OFFSET 0x44 -#define LEON_REG_TIMERCTRL1_OFFSET 0x48 -#define LEON_REG_WDOG_OFFSET 0x4C -#define LEON_REG_TIMERCNT2_OFFSET 0x50 -#define LEON_REG_TIMERLOAD2_OFFSET 0x54 -#define LEON_REG_TIMERCTRL2_OFFSET 0x58 -#define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C -#define LEON_REG_SCALERCNT_OFFSET 0x60 -#define LEON_REG_SCALER_LOAD_OFFSET 0x64 -#define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68 -#define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C -#define LEON_REG_UARTDATA1_OFFSET 0x70 -#define LEON_REG_UARTSTATUS1_OFFSET 0x74 -#define LEON_REG_UARTCTRL1_OFFSET 0x78 -#define LEON_REG_UARTSCALER1_OFFSET 0x7C -#define LEON_REG_UARTDATA2_OFFSET 0x80 -#define LEON_REG_UARTSTATUS2_OFFSET 0x84 -#define LEON_REG_UARTCTRL2_OFFSET 0x88 -#define LEON_REG_UARTSCALER2_OFFSET 0x8C -#define LEON_REG_IRQMASK_OFFSET 0x90 -#define LEON_REG_IRQPEND_OFFSET 0x94 -#define LEON_REG_IRQFORCE_OFFSET 0x98 -#define LEON_REG_IRQCLEAR_OFFSET 0x9C -#define LEON_REG_PIODATA_OFFSET 0xA0 -#define LEON_REG_PIODIR_OFFSET 0xA4 -#define LEON_REG_PIOIRQ_OFFSET 0xA8 -#define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4 -#define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8 - -#endif - -/* - * The following defines the bits in Memory Configuration Register 1. - */ - -#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 - -/* - * The following defines the bits in Memory Configuration Register 1. - */ - -#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 - - -/* - * The following defines the bits in the Timer Control Register. - */ - -#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ - /* 0 = no function */ - -/* - * The following defines the bits in the UART Control Registers. - * - */ - -#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ - -/* - * The following defines the bits in the LEON UART Status Registers. - */ - -#define LEON_REG_UART_STATUS_CLR 0x00000000 /* Clear all status bits */ -#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ -#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ -#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ -#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ -#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ -#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ -#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ -#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ - - -/* - * The following defines the bits in the LEON UART Status Registers. - */ - -#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ -#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ -#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ -#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ -#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ -#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ -#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ -#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ - -#ifndef ASM - -/* - * This is used to manipulate the on-chip registers. - * - * The following symbol must be defined in the linkcmds file and point - * to the correct location. - */ - -extern LEON_Register_Map LEON_REG; - -static __inline__ int bsp_irq_fixup(int irq) -{ - return irq; -} - -/* - * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - * - * NOTE: For operations which are not atomic, this code disables interrupts - * to guarantee there are no intervening accesses to the same register. - * The operations which read the register, modify the value and then - * store the result back are vulnerable. - */ - -#define LEON_Clear_interrupt( _source ) \ - do { \ - LEON_REG.Interrupt_Clear = (1 << (_source)); \ - } while (0) - -#define LEON_Force_interrupt( _source ) \ - do { \ - LEON_REG.Interrupt_Force = (1 << (_source)); \ - } while (0) - -#define LEON_Is_interrupt_pending( _source ) \ - (LEON_REG.Interrupt_Pending & (1 << (_source))) - -#define LEON_Is_interrupt_masked( _source ) \ - (!(LEON_REG.Interrupt_Mask & (1 << (_source)))) - -#define LEON_Mask_interrupt( _source ) \ - do { \ - uint32_t _level; \ - \ - _level = sparc_disable_interrupts(); \ - LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define LEON_Unmask_interrupt( _source ) \ - do { \ - uint32_t _level; \ - \ - _level = sparc_disable_interrupts(); \ - LEON_REG.Interrupt_Mask |= (1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define LEON_Disable_interrupt( _source, _previous ) \ - do { \ - uint32_t _level; \ - uint32_t _mask = 1 << (_source); \ - \ - _level = sparc_disable_interrupts(); \ - (_previous) = LEON_REG.Interrupt_Mask; \ - LEON_REG.Interrupt_Mask = _previous & ~_mask; \ - sparc_enable_interrupts( _level ); \ - (_previous) &= _mask; \ - } while (0) - -#define LEON_Restore_interrupt( _source, _previous ) \ - do { \ - uint32_t _level; \ - uint32_t _mask = 1 << (_source); \ - \ - _level = sparc_disable_interrupts(); \ - LEON_REG.Interrupt_Mask = \ - (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -/* Make all SPARC BSPs have common macros for interrupt handling */ -#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) -#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) -#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) -#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) -#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) -#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) -#define BSP_Disable_interrupt(_source, _previous) \ - LEON_Disable_interrupt(_source, _prev) -#define BSP_Restore_interrupt(_source, _previous) \ - LEON_Restore_interrupt(_source, _previous) - -/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ -#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ - BSP_Is_interrupt_masked(_source) -#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ - BSP_Unmask_interrupt(_source) -#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ - BSP_Mask_interrupt(_source) -#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ - BSP_Disable_interrupt(_source, _prev) -#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ - BSP_Cpu_Restore_interrupt(_source, _previous) - -/* - * Each timer control register is organized as follows: - * - * D0 - Enable - * 1 = enable counting - * 0 = hold scaler and counter - * - * D1 - Counter Reload - * 1 = reload counter at zero and restart - * 0 = stop counter at zero - * - * D2 - Counter Load - * 1 = load counter with preset value - * 0 = no function - * - */ - -#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 -#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 - -#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 - -#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 -#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 - -#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 -#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 - -#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 -#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 - -/* Load 32-bit word by forcing a cache-miss */ -static inline unsigned int leon_r32_no_cache(uintptr_t addr) -{ - unsigned int tmp; - __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); - return tmp; -} - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* !_INCLUDE_LEON_h */ - diff --git a/c/src/lib/libbsp/sparc/leon2/include/tm27.h b/c/src/lib/libbsp/sparc/leon2/include/tm27.h deleted file mode 100644 index 0d28641b9b..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/tm27.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * @ingroup sparc_leon2 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * COPYRIGHT (c) 2006. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Since the interrupt code for the SPARC supports both synchronous - * and asynchronous trap handlers, support for testing with both - * is included. - */ - -#define SIS_USE_SYNCHRONOUS_TRAP 0 - -/* - * The synchronous trap is an arbitrarily chosen software trap. - */ - -#if (SIS_USE_SYNCHRONOUS_TRAP == 1) - -#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); - -#define Cause_tm27_intr() \ - __asm__ volatile( "ta 0x10; nop " ); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/* - * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. - */ - -#else /* use a regular asynchronous trap */ - -#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1 -#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) -#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 -#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); \ - set_vector( (handler), TEST_VECTOR2, 1 ); - -#define Cause_tm27_intr() \ - do { \ - LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \ - nop(); \ - nop(); \ - nop(); \ - } while (0) - -#define Clear_tm27_intr() \ - LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE ) - -#define Lower_tm27_intr() /* empty */ - -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon2/preinstall.am b/c/src/lib/libbsp/sparc/leon2/preinstall.am deleted file mode 100644 index 7f44269d58..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/preinstall.am +++ /dev/null @@ -1,314 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - -$(PROJECT_LIB)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_LIB) - @: > $(PROJECT_LIB)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs -PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs - 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-$(PROJECT_INCLUDE)/bsp/at697_pci.h: include/at697_pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/at697_pci.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/at697_pci.h - -$(PROJECT_INCLUDE)/bsp/gr_701.h: ../../sparc/shared/include/gr_701.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr_701.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr_701.h - -$(PROJECT_INCLUDE)/bsp/gr_rasta_adcdac.h: ../../sparc/shared/include/gr_rasta_adcdac.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr_rasta_adcdac.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr_rasta_adcdac.h - -$(PROJECT_INCLUDE)/bsp/gr_rasta_io.h: ../../sparc/shared/include/gr_rasta_io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr_rasta_io.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr_rasta_io.h - -$(PROJECT_INCLUDE)/bsp/gr_rasta_spw_router.h: ../../sparc/shared/include/gr_rasta_spw_router.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr_rasta_spw_router.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr_rasta_spw_router.h - -$(PROJECT_INCLUDE)/bsp/gr_rasta_tmtc.h: ../../sparc/shared/include/gr_rasta_tmtc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr_rasta_tmtc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr_rasta_tmtc.h - -$(PROJECT_INCLUDE)/bsp/gr_leon4_n2x.h: ../../sparc/shared/include/gr_leon4_n2x.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr_leon4_n2x.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr_leon4_n2x.h - -$(PROJECT_INCLUDE)/bsp/gr_cpci_gr740.h: ../../sparc/shared/include/gr_cpci_gr740.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr_cpci_gr740.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr_cpci_gr740.h - -$(PROJECT_INCLUDE)/bsp/b1553brm.h: ../../sparc/shared/include/b1553brm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/b1553brm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/b1553brm.h - -$(PROJECT_INCLUDE)/bsp/b1553rt.h: ../../sparc/shared/include/b1553rt.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/b1553rt.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/b1553rt.h - -$(PROJECT_INCLUDE)/bsp/gr1553b.h: ../../sparc/shared/include/gr1553b.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr1553b.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr1553b.h - -$(PROJECT_INCLUDE)/bsp/gr1553bc.h: ../../sparc/shared/include/gr1553bc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr1553bc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr1553bc.h - -$(PROJECT_INCLUDE)/bsp/gr1553bc_list.h: ../../sparc/shared/include/gr1553bc_list.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr1553bc_list.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr1553bc_list.h - -$(PROJECT_INCLUDE)/bsp/gr1553bm.h: ../../sparc/shared/include/gr1553bm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr1553bm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr1553bm.h - -$(PROJECT_INCLUDE)/bsp/gr1553rt.h: ../../sparc/shared/include/gr1553rt.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gr1553rt.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gr1553rt.h - -$(PROJECT_INCLUDE)/bsp/occan.h: ../../sparc/shared/include/occan.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/occan.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/occan.h - -$(PROJECT_INCLUDE)/bsp/grcan.h: ../../sparc/shared/include/grcan.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grcan.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grcan.h - -if !HAS_SMP -$(PROJECT_INCLUDE)/bsp/grspw.h: ../../sparc/shared/include/grspw.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grspw.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grspw.h -endif -$(PROJECT_INCLUDE)/bsp/grspw_pkt.h: ../../sparc/shared/include/grspw_pkt.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grspw_pkt.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grspw_pkt.h - -$(PROJECT_INCLUDE)/bsp/grspw_router.h: ../../sparc/shared/include/grspw_router.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grspw_router.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grspw_router.h - -$(PROJECT_INCLUDE)/bsp/apbuart.h: ../../sparc/shared/include/apbuart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/apbuart.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/apbuart.h - -$(PROJECT_INCLUDE)/bsp/i2cmst.h: ../../sparc/shared/include/i2cmst.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2cmst.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2cmst.h - -$(PROJECT_INCLUDE)/bsp/spictrl.h: ../../sparc/shared/include/spictrl.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/spictrl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/spictrl.h - -$(PROJECT_INCLUDE)/bsp/spwcuc.h: ../../sparc/shared/include/spwcuc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/spwcuc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/spwcuc.h - -$(PROJECT_INCLUDE)/bsp/grctm.h: ../../sparc/shared/include/grctm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grctm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grctm.h - -$(PROJECT_INCLUDE)/bsp/grgpio.h: ../../sparc/shared/include/grgpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grgpio.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grgpio.h - -$(PROJECT_INCLUDE)/bsp/gpiolib.h: ../../sparc/shared/include/gpiolib.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gpiolib.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gpiolib.h - -$(PROJECT_INCLUDE)/bsp/grpwm.h: ../../sparc/shared/include/grpwm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grpwm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grpwm.h - -$(PROJECT_INCLUDE)/bsp/gradcdac.h: ../../sparc/shared/include/gradcdac.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/gradcdac.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/gradcdac.h - -$(PROJECT_INCLUDE)/bsp/mctrl.h: ../../sparc/shared/include/mctrl.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mctrl.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mctrl.h - -$(PROJECT_INCLUDE)/bsp/l2c.h: ../../sparc/shared/include/l2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/l2c.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/l2c.h - -$(PROJECT_INCLUDE)/bsp/griommu.h: ../../sparc/shared/include/griommu.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/griommu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/griommu.h - -$(PROJECT_INCLUDE)/bsp/grtc.h: ../../sparc/shared/include/grtc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grtc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grtc.h - -$(PROJECT_INCLUDE)/bsp/grtm.h: ../../sparc/shared/include/grtm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/grtm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/grtm.h - -$(PROJECT_INCLUDE)/bsp/memscrub.h: ../../sparc/shared/include/memscrub.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/memscrub.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/memscrub.h - -$(PROJECT_INCLUDE)/bsp/l4stat.h: ../../sparc/shared/include/l4stat.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/l4stat.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/l4stat.h - -$(PROJECT_INCLUDE)/drvmgr/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/drvmgr - @: > $(PROJECT_INCLUDE)/drvmgr/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/drvmgr/$(dirstamp) - -$(PROJECT_INCLUDE)/drvmgr/ambapp_bus.h: ../../sparc/shared/include/drvmgr/ambapp_bus.h $(PROJECT_INCLUDE)/drvmgr/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/drvmgr/ambapp_bus.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/drvmgr/ambapp_bus.h - -$(PROJECT_INCLUDE)/drvmgr/leon2_amba_bus.h: ../../sparc/shared/include/drvmgr/leon2_amba_bus.h $(PROJECT_INCLUDE)/drvmgr/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/drvmgr/leon2_amba_bus.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/drvmgr/leon2_amba_bus.h - -$(PROJECT_INCLUDE)/drvmgr/bspcommon.h: ../../sparc/shared/include/drvmgr/bspcommon.h $(PROJECT_INCLUDE)/drvmgr/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/drvmgr/bspcommon.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/drvmgr/bspcommon.h - -if HAS_NETWORKING -$(PROJECT_INCLUDE)/bsp/greth.h: ../../sparc/shared/include/greth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/greth.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/greth.h - -$(PROJECT_INCLUDE)/bsp/network_interface_add.h: ../../sparc/shared/include/network_interface_add.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/network_interface_add.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/network_interface_add.h -endif diff --git a/c/src/lib/libbsp/sparc/leon2/bsp_specs b/c/src/lib/libbsp/sparc/leon2/startup/bsp_specs index 87638cc027..87638cc027 100644 --- a/c/src/lib/libbsp/sparc/leon2/bsp_specs +++ b/c/src/lib/libbsp/sparc/leon2/startup/bsp_specs diff --git a/c/src/lib/libbsp/sparc/leon3/Makefile.am b/c/src/lib/libbsp/sparc/leon3/Makefile.am index b73569d222..60e2a9044a 100644 --- a/c/src/lib/libbsp/sparc/leon3/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon3/Makefile.am @@ -4,34 +4,25 @@ EXTRA_DIST = include $(top_srcdir)/../../../../automake/compile.am include $(top_srcdir)/../../bsp.am -include_bspdir = $(includedir)/bsp +dist_project_lib_DATA = startup/bsp_specs -dist_project_lib_DATA = bsp_specs - -include_HEADERS = include/bsp.h -include_HEADERS += include/tm27.h -include_bsp_HEADERS = ../../sparc/shared/include/debug_defs.h - -nodist_include_HEADERS = include/bspopts.h -nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h DISTCLEANFILES = include/bspopts.h noinst_PROGRAMS = -include_HEADERS += include/leon.h EXTRA_DIST += ../../sparc/shared/start/start.S start.$(OBJEXT): ../../sparc/shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) +project_lib_DATA += linkcmds dist_project_lib_DATA += ../shared/startup/linkcmds.base -dist_project_lib_DATA += startup/linkcmds +dist_project_lib_DATA += startup/linkcmds.gr712rc +dist_project_lib_DATA += startup/linkcmds.gr740 dist_project_lib_DATA += startup/linkcmds.leon3 dist_project_lib_DATA += startup/linkcmds.ut699 -dist_project_lib_DATA += startup/linkcmds.gr712rc dist_project_lib_DATA += startup/linkcmds.ut700 -dist_project_lib_DATA += startup/linkcmds.gr740 noinst_LIBRARIES = libbsp.a libbsp_a_SOURCES = @@ -55,13 +46,7 @@ libbsp_a_SOURCES += ../../sparc/shared/cpu.c libbsp_a_SOURCES += ../../sparc/shared/irq_asm.S # gnatsupp libbsp_a_SOURCES += gnatsupp/gnatsupp.c ../../sparc/shared/gnatcommon.c -include_bsp_HEADERS += ../shared/include/gnatcommon.h # AMBA bus -include_HEADERS += include/amba.h -include_HEADERS += ../../sparc/shared/include/ambapp.h -include_HEADERS += ../../sparc/shared/include/ambapp_ids.h -include_HEADERS += ../../sparc/shared/include/grlib.h -include_bsp_HEADERS += ../../sparc/shared/include/ahbstat.h libbsp_a_SOURCES += amba/amba.c libbsp_a_SOURCES += ../../sparc/shared/amba/ambapp.c libbsp_a_SOURCES += ../../sparc/shared/amba/ambapp_alloc.c @@ -76,8 +61,6 @@ libbsp_a_SOURCES += ../../sparc/shared/amba/ambapp_show.c libbsp_a_SOURCES += ../../sparc/shared/amba/ahbstat.c # Clock Driver and Timer Library -include_bsp_HEADERS += ../../sparc/shared/include/gptimer.h -include_bsp_HEADERS += ../../sparc/shared/include/tlib.h libbsp_a_SOURCES += ../../sparc/shared/timer/gptimer.c libbsp_a_SOURCES += ../../sparc/shared/timer/tlib.c libbsp_a_SOURCES += ../../sparc/shared/timer/tlib_ckinit.c @@ -90,17 +73,10 @@ libbsp_a_SOURCES += ../../shared/console-termios.c libbsp_a_SOURCES += console/console.c libbsp_a_SOURCES += ../../sparc/shared/uart/cons.c libbsp_a_SOURCES += ../../sparc/shared/uart/apbuart_cons.c -include_bsp_HEADERS += ../../sparc/shared/include/cons.h -include_bsp_HEADERS += ../../sparc/shared/include/apbuart_cons.h # debugio libbsp_a_SOURCES += console/printk_support.c # IRQ -include_bsp_HEADERS += ../../sparc/shared/include/genirq.h -include_bsp_HEADERS += \ - ../../shared/include/irq-generic.h \ - ../../shared/include/irq-info.h \ - include/bsp/irq.h libbsp_a_SOURCES += \ startup/eirq.c \ ../../sparc/shared/irq/genirq.c \ @@ -114,10 +90,6 @@ libbsp_a_SOURCES += \ ../../shared/src/irq-shell.c # PCI -include_bsp_HEADERS += ../../sparc/shared/include/grpci.h -include_bsp_HEADERS += ../../sparc/shared/include/grpci2.h -include_bsp_HEADERS += ../../sparc/shared/include/grpci2dma.h -include_bsp_HEADERS += ../../sparc/shared/include/pcif.h libbsp_a_SOURCES += ../../sparc/shared/pci/grpci.c libbsp_a_SOURCES += ../../sparc/shared/pci/grpci2.c libbsp_a_SOURCES += ../../sparc/shared/pci/grpci2dma.c @@ -126,14 +98,6 @@ libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_le.c libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_be.c # PCI target devices -include_bsp_HEADERS += ../../sparc/shared/include/gr_701.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_rasta_adcdac.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_rasta_io.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_rasta_spw_router.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_rasta_tmtc.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_tmtc_1553.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_leon4_n2x.h -include_bsp_HEADERS += ../../sparc/shared/include/gr_cpci_gr740.h libbsp_a_SOURCES += ../../sparc/shared/pci/gr_701.c libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_adcdac.c libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_io.c @@ -144,122 +108,78 @@ libbsp_a_SOURCES += ../../sparc/shared/pci/gr_leon4_n2x.c libbsp_a_SOURCES += ../../sparc/shared/pci/gr_cpci_gr740.c # B1553BRM -include_bsp_HEADERS += ../../sparc/shared/include/b1553brm.h -include_bsp_HEADERS += ../../sparc/shared/include/b1553rt.h libbsp_a_SOURCES += ../../sparc/shared/1553/b1553brm.c libbsp_a_SOURCES += ../../sparc/shared/1553/b1553rt.c # GR1553B -include_bsp_HEADERS += ../../sparc/shared/include/gr1553b.h -include_bsp_HEADERS += ../../sparc/shared/include/gr1553bc.h -include_bsp_HEADERS += ../../sparc/shared/include/gr1553bc_list.h -include_bsp_HEADERS += ../../sparc/shared/include/gr1553bm.h -include_bsp_HEADERS += ../../sparc/shared/include/gr1553rt.h libbsp_a_SOURCES += ../../sparc/shared/1553/gr1553b.c libbsp_a_SOURCES += ../../sparc/shared/1553/gr1553bc.c libbsp_a_SOURCES += ../../sparc/shared/1553/gr1553bm.c libbsp_a_SOURCES += ../../sparc/shared/1553/gr1553rt.c # CAN -include_bsp_HEADERS += ../../sparc/shared/include/occan.h \ - ../../sparc/shared/include/grcan.h libbsp_a_SOURCES += ../../sparc/shared/can/occan.c \ ../../sparc/shared/can/grcan.c # SpaceWire if !HAS_SMP -include_bsp_HEADERS += ../../sparc/shared/include/grspw.h libbsp_a_SOURCES += ../../sparc/shared/spw/grspw.c endif -include_bsp_HEADERS += ../../sparc/shared/include/grspw_pkt.h -include_bsp_HEADERS += ../../sparc/shared/include/grspw_router.h libbsp_a_SOURCES += ../../sparc/shared/spw/grspw_pkt.c libbsp_a_SOURCES += ../../sparc/shared/spw/grspw_router.c # UART -include_bsp_HEADERS += ../../sparc/shared/include/apbuart.h \ - ../../sparc/shared/include/apbuart_termios.h libbsp_a_SOURCES += ../../sparc/shared/uart/apbuart_termios.c # I2CMST -include_bsp_HEADERS += ../../sparc/shared/include/i2cmst.h libbsp_a_SOURCES += ../../sparc/shared/i2c/i2cmst.c # SPI -include_bsp_HEADERS += ../../sparc/shared/include/spictrl.h libbsp_a_SOURCES += ../../sparc/shared/spi/spictrl.c # TIME -include_bsp_HEADERS += ../../sparc/shared/include/spwcuc.h -include_bsp_HEADERS += ../../sparc/shared/include/grctm.h libbsp_a_SOURCES += ../../sparc/shared/time/spwcuc.c libbsp_a_SOURCES += ../../sparc/shared/time/grctm.c # GPIO -include_bsp_HEADERS += ../../sparc/shared/include/grgpio.h -include_bsp_HEADERS += ../../sparc/shared/include/gpiolib.h libbsp_a_SOURCES += ../../sparc/shared/gpio/grgpio.c libbsp_a_SOURCES += ../../sparc/shared/gpio/gpiolib.c # PWM -include_bsp_HEADERS += ../../sparc/shared/include/grpwm.h libbsp_a_SOURCES += ../../sparc/shared/pwm/grpwm.c # ADC and DAC -include_bsp_HEADERS += ../../sparc/shared/include/gradcdac.h libbsp_a_SOURCES += ../../sparc/shared/analog/gradcdac.c # Memory controllers libbsp_a_SOURCES += ../../sparc/shared/mem/mctrl.c -include_bsp_HEADERS += ../../sparc/shared/include/mctrl.h - # l2cache libbsp_a_SOURCES += ../../sparc/shared/l2c/l2c.c -include_bsp_HEADERS += ../../sparc/shared/include/l2c.h - # griommu libbsp_a_SOURCES += ../../sparc/shared/iommu/griommu.c -include_bsp_HEADERS += ../../sparc/shared/include/griommu.h - # timer libbsp_a_SOURCES += timer/timer.c libbsp_a_SOURCES += timer/watchdog.c -include_bsp_HEADERS += include/watchdog.h - # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c libbsp_a_SOURCES += include/cache_.h libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/include # GR712 -include_bsp_HEADERS += ../../sparc/shared/include/grascs.h -include_bsp_HEADERS += ../../sparc/shared/include/satcan.h -include_bsp_HEADERS += ../../sparc/shared/include/canmux.h -include_bsp_HEADERS += ../../sparc/shared/include/grslink.h libbsp_a_SOURCES += ../../sparc/shared/ascs/grascs.c libbsp_a_SOURCES += ../../sparc/shared/can/satcan.c libbsp_a_SOURCES += ../../sparc/shared/can/canmux.c libbsp_a_SOURCES += ../../sparc/shared/slink/grslink.c # TM/TC -include_bsp_HEADERS += ../../sparc/shared/include/grtc.h -include_bsp_HEADERS += ../../sparc/shared/include/grtm.h libbsp_a_SOURCES += ../../sparc/shared/tmtc/grtc.c libbsp_a_SOURCES += ../../sparc/shared/tmtc/grtm.c # MEMSCRUB libbsp_a_SOURCES += ../../sparc/shared/scrub/memscrub.c -include_bsp_HEADERS += ../../sparc/shared/include/memscrub.h - # L4STAT libbsp_a_SOURCES += ../../sparc/shared/stat/l4stat.c -include_bsp_HEADERS += ../../sparc/shared/include/l4stat.h - # Driver Manager -include_drvmgrdir = $(includedir)/drvmgr -include_drvmgr_HEADERS = ../../sparc/shared/include/drvmgr/ambapp_bus_grlib.h -include_drvmgr_HEADERS += ../../sparc/shared/include/drvmgr/ambapp_bus.h -include_drvmgr_HEADERS += ../../sparc/shared/include/drvmgr/bspcommon.h libbsp_a_SOURCES += ../../sparc/shared/drvmgr/ambapp_bus.c libbsp_a_SOURCES += ../../sparc/shared/drvmgr/ambapp_bus_grlib.c libbsp_a_SOURCES += ../../sparc/shared/drvmgr/get_resarray_count.c @@ -290,7 +210,6 @@ if !HAS_SMP libbsp_a_SOURCES += leon_greth/leon_greth.c endif leon_greth_rel_SOURCES = ../../sparc/shared/net/greth.c -include_bsp_HEADERS += ../../sparc/shared/include/greth.h leon_greth_rel_CPPFLAGS = $(AM_CPPFLAGS) leon_greth_rel_CPPFLAGS += -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ leon_greth_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) @@ -298,7 +217,6 @@ endif # BSP Network configuration if HAS_NETWORKING -include_bsp_HEADERS += ../../sparc/shared/include/network_interface_add.h libbsp_a_SOURCES += ../../sparc/shared/net/network_interface_add.c endif @@ -322,5 +240,5 @@ endif EXTRA_DIST += times -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../../automake/local.am +include $(srcdir)/../../../../../../bsps/sparc/leon3/headers.am diff --git a/c/src/lib/libbsp/sparc/leon3/configure.ac b/c/src/lib/libbsp/sparc/leon3/configure.ac index 83e754688c..c972868a8d 100644 --- a/c/src/lib/libbsp/sparc/leon3/configure.ac +++ b/c/src/lib/libbsp/sparc/leon3/configure.ac @@ -5,6 +5,9 @@ AC_INIT([rtems-c-src-lib-libbsp-sparc-leon3], [_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([make/custom/leon3.cfg]) RTEMS_TOP(../../../../../..) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP +RTEMS_BSP_LINKCMDS RTEMS_CANONICAL_TARGET_CPU AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) @@ -38,7 +41,6 @@ RTEMS_BSPOPTS_HELP([BSP_POWER_DOWN_AT_FATAL_HALT], error which will hand over to debugger, simulator, etc.]) RTEMS_BSP_CLEANUP_OPTIONS -RTEMS_BSP_LINKCMDS # Explicitly list all Makefiles here AC_CONFIG_FILES([Makefile]) diff --git a/c/src/lib/libbsp/sparc/leon3/include/amba.h b/c/src/lib/libbsp/sparc/leon3/include/amba.h deleted file mode 100644 index 059b28ca07..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/amba.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * @file - * @defgroup amba AMBA Driver Handler - * @ingroup sparc_leon3 - * @brief AMBA Plag & Play Bus Driver Macros - */ - -/* - * AMBA Plag & Play Bus Driver Macros - * - * Macros used for AMBA Plug & Play bus scanning - * - * COPYRIGHT (c) 2004. - * Gaisler Research - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __AMBA_H__ -#define __AMBA_H__ - -#define LEON3_IO_AREA 0xfff00000 -#define LEON3_CONF_AREA 0xff000 -#define LEON3_AHB_SLAVE_CONF_AREA (1 << 11) - -#define LEON3_AHB_CONF_WORDS 8 -#define LEON3_APB_CONF_WORDS 2 -#define LEON3_AHB_MASTERS 64 -#define LEON3_AHB_SLAVES 64 -#define LEON3_APB_SLAVES 16 - -#include <ambapp.h> -#include <grlib.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* The AMBA Plug&Play info of the bus that the LEON3 sits on */ -extern struct ambapp_bus ambapp_plb; - -#ifdef __cplusplus -} -#endif - -#endif /* __AMBA_H__ */ diff --git a/c/src/lib/libbsp/sparc/leon3/include/bsp.h b/c/src/lib/libbsp/sparc/leon3/include/bsp.h deleted file mode 100644 index 3fda4edc66..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/bsp.h +++ /dev/null @@ -1,250 +0,0 @@ -/** - * @file - * - * @ingroup sparc_leon3 - * - * @brief Global BSP Definitions. - */ - -/* bsp.h - * - * This include file contains all SPARC simulator definitions. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef LIBBSP_SPARC_LEON3_BSP_H -#define LIBBSP_SPARC_LEON3_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <leon.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup sparc_leon3 LEON3 Support - * - * @ingroup bsp_sparc - * - * @brief LEON3 support package - * - */ - -/* SPARC CPU variant: LEON3 */ -#define LEON3 1 - -/* - * BSP provides its own Idle thread body - */ -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* Maximum supported APBUARTs by BSP */ -#define BSP_NUMBER_OF_TERMIOS_PORTS 8 - -/* Make sure maximum number of consoles fit in filesystem */ -#define BSP_MAXIMUM_DEVICES 8 - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_leon_open_eth_driver_attach( - struct rtems_bsdnet_ifconfig *config, - int attach -); -extern int rtems_smc91111_driver_attach_leon3( - struct rtems_bsdnet_ifconfig *config, - int attach -); -extern int rtems_leon_greth_driver_attach( - struct rtems_bsdnet_ifconfig *config, - int attach -); - -#define RTEMS_BSP_NETWORK_DRIVER_NAME_OPENETH "open_eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH \ - rtems_leon_open_eth_driver_attach -#define RTEMS_BSP_NETWORK_DRIVER_NAME_SMC91111 "smc_eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \ - rtems_smc91111_driver_attach_leon3 -#define RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH "gr_eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH \ - rtems_leon_greth_driver_attach - -#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME -#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH -#endif - -#define HAS_SMC91111 - -/* Configure GRETH driver */ -#define GRETH_SUPPORTED -#define GRETH_MEM_LOAD(addr) leon_r32_no_cache((uintptr_t)addr) - -extern int CPU_SPARC_HAS_SNOOPING; - -/* Constants */ - -/* - * Information placed in the linkcmds file. - */ - -extern int RAM_START; -extern int RAM_END; -extern int RAM_SIZE; - -extern int PROM_START; -extern int PROM_END; -extern int PROM_SIZE; - -extern int CLOCK_SPEED; - -extern int end; /* last address in the program */ - -/* miscellaneous stuff assumed to exist */ - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -void BSP_fatal_exit(uint32_t error); - -void bsp_spurious_initialize( void ); - -/* - * Delay for the specified number of microseconds. - */ -void rtems_bsp_delay(int usecs); - -/* Interrupt Service Routine (ISR) pointer */ -typedef void (*bsp_shared_isr)(void *arg); - -/* Initializes the Shared System Interrupt service */ -extern void BSP_shared_interrupt_init(void); - -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ -void bsp_isr_handler(rtems_vector_number vector); - -/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple - * interrupt handlers may use the same IRQ number, all ISRs will be called - * when an interrupt on that line is fired. - * - * Arguments - * irq System IRQ number - * info Optional Name of IRQ source - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_register - ( - int irq, - const char *info, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_install(irq, info, - RTEMS_INTERRUPT_SHARED, isr, arg); -} - -/* Unregister previously registered shared IRQ handler. - * - * Arguments - * irq System IRQ number - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_unregister - ( - int irq, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_remove(irq, isr, arg); -} - -/* Clear interrupt pending on IRQ controller, this is typically done on a - * level triggered interrupt source such as PCI to avoid taking double IRQs. - * In such a case the interrupt source must be cleared first on LEON, before - * acknowledging the IRQ with this function. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_clear(int irq); - -/* Enable Interrupt. This function will unmask the IRQ at the interrupt - * controller. This is normally done by _register(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_unmask(int irq); - -/* Disable Interrupt. This function will mask one IRQ at the interrupt - * controller. This is normally done by _unregister(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_mask(int irq); - -#if defined(RTEMS_SMP) || defined(RTEMS_MULTIPROCESSING) -/* Irq used by the shared memory driver and for inter-processor interrupts. - * The variable is weakly linked. Redefine the variable in your application - * to override the BSP default. - */ -extern const unsigned char LEON3_mp_irq; -#endif - -#ifdef RTEMS_SMP -/* Weak table used to implement static interrupt CPU affinity in a SMP - * configuration. The array index is the interrupt to be looked up, and - * the array[INTERRUPT] content is the CPU number relative to boot CPU - * index that will be servicing the interrupts from the IRQ source. The - * default is to let the first CPU (the boot cpu) to handle all - * interrupts (all zeros). - */ -extern const unsigned char LEON3_irq_to_cpu[32]; -#endif - -/* Common driver build-time configurations. On small systems undefine - * [DRIVER]_INFO_AVAIL to avoid info routines get dragged in. It is good - * for debugging and printing information about the system, but makes the - * image bigger. - */ -#define AMBAPPBUS_INFO_AVAIL /* AMBAPP Bus driver */ -#define APBUART_INFO_AVAIL /* APBUART Console driver */ -#define GPTIMER_INFO_AVAIL /* GPTIMER Timer driver */ -#define GRETH_INFO_AVAIL /* GRETH Ethernet driver */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon3/include/bsp/irq.h b/c/src/lib/libbsp/sparc/leon3/include/bsp/irq.h deleted file mode 100644 index c3e7959139..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/bsp/irq.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * @file - * @ingroup sparc_leon3 - * @brief LEON3 generic shared IRQ setup - * - * Based on libbsp/shared/include/irq.h. - */ - -/* - * Copyright (c) 2012. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_LEON3_IRQ_CONFIG_H -#define LIBBSP_LEON3_IRQ_CONFIG_H - -#include <leon.h> -#include <rtems/score/processormask.h> - -#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ -#define BSP_INTERRUPT_VECTOR_MAX_EXT 31 /* Extended IRQ controller */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_EXT - -/* The check is different depending on IRQ controller, runtime detected */ -#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR - -/** - * @brief Returns true if the interrupt vector with number @a vector is valid. - */ -static inline bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) -{ - return (rtems_vector_number) BSP_INTERRUPT_VECTOR_MIN <= vector - && ((vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX_STD && - LEON3_IrqCtrl_EIrq == 0) || - (vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX_EXT && - LEON3_IrqCtrl_EIrq != 0)); -} - -void bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -void bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - -#endif /* LIBBSP_LEON3_IRQ_CONFIG_H */ diff --git a/c/src/lib/libbsp/sparc/leon3/include/leon.h b/c/src/lib/libbsp/sparc/leon3/include/leon.h deleted file mode 100644 index 758b760b0b..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/leon.h +++ /dev/null @@ -1,511 +0,0 @@ -/** - * @file - * @ingroup sparc_leon3 - * @brief LEON3 BSP data types and macros - */ - -/* leon.h - * - * LEON3 BSP data types and macros. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * Modified for LEON3 BSP. - * COPYRIGHT (c) 2004. - * Gaisler Research. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _INCLUDE_LEON_h -#define _INCLUDE_LEON_h - -#include <rtems.h> -#include <amba.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define LEON_INTERRUPT_EXTERNAL_1 5 - -#ifndef ASM -/* - * Trap Types for on-chip peripherals - * - * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments - * - * NOTE: The priority level for each source corresponds to the least - * significant nibble of the trap type. - */ - -#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) - -#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) - -#define LEON_INT_TRAP( _trap ) \ - ( (_trap) >= 0x11 && \ - (_trap) <= 0x1F ) - -/* /\* */ -/* * This is used to manipulate the on-chip registers. */ -/* * */ -/* * The following symbol must be defined in the linkcmds file and point */ -/* * to the correct location. */ -/* *\/ */ -/* Leon uses dynamic register mapping using amba configuration records */ -/* LEON_Register_Map is obsolete */ -/* extern LEON_Register_Map LEON_REG; */ - -#endif - -/* - * The following defines the bits in Memory Configuration Register 1. - */ - -#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 - -/* - * The following defines the bits in Memory Configuration Register 1. - */ - -#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 - - -/* - * The following defines the bits in the Timer Control Register. - */ - -#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ - /* 0 = no function */ - -/* - * The following defines the bits in the UART Control Registers. - */ - -#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ - -/* - * The following defines the bits in the LEON UART Status Register. - */ - -#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ -#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ -#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ -#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ -#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ -#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ -#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ -#define LEON_REG_UART_STATUS_TF 0x00000200 /* FIFO Full */ -#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ - -/* - * The following defines the bits in the LEON UART Control Register. - */ - -#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ -#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ -#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ -#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ -#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ -#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ -#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ -#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ -#define LEON_REG_UART_CTRL_DB 0x00000800 /* Debug FIFO enable */ -#define LEON_REG_UART_CTRL_SI 0x00004000 /* TX shift register empty IRQ enable */ -#define LEON_REG_UART_CTRL_FA 0x80000000 /* FIFO Available */ -#define LEON_REG_UART_CTRL_FA_BIT 31 - -/* - * The following defines the bits in the LEON Cache Control Register. - */ -#define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ -#define LEON3_REG_CACHE_CTRL_DS 0x00800000 /* Data cache snooping */ - -/* LEON3 Interrupt Controller */ -extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; -extern struct ambapp_dev *LEON3_IrqCtrl_Adev; - -/* LEON3 GP Timer */ -extern volatile struct gptimer_regs *LEON3_Timer_Regs; -extern struct ambapp_dev *LEON3_Timer_Adev; - -/* LEON3 CPU Index of boot CPU */ -extern uint32_t LEON3_Cpu_Index; - -/* The external IRQ number, -1 if not external interrupts */ -extern int LEON3_IrqCtrl_EIrq; - -static __inline__ int bsp_irq_fixup(int irq) -{ - int eirq, cpu; - - if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { - /* Get interrupt number from IRQ controller */ - cpu = _LEON3_Get_current_processor(); - eirq = LEON3_IrqCtrl_Regs->intid[cpu] & 0x1f; - if (eirq & 0x10) - irq = eirq; - } - - return irq; -} - -/* Macros used for manipulating bits in LEON3 GP Timer Control Register */ - -#define LEON3_IRQMPSTATUS_CPUNR 28 -#define LEON3_IRQMPSTATUS_BROADCAST 27 - - -#ifndef ASM - -/* - * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - * - * NOTE: For operations which are not atomic, this code disables interrupts - * to guarantee there are no intervening accesses to the same register. - * The operations which read the register, modify the value and then - * store the result back are vulnerable. - */ - -extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; - -#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ - rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) - -#define LEON3_IRQCTRL_RELEASE( _lock_context ) \ - rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) - -#define LEON_Clear_interrupt( _source ) \ - do { \ - LEON3_IrqCtrl_Regs->iclear = (1U << (_source)); \ - } while (0) - -#define LEON_Force_interrupt( _source ) \ - do { \ - LEON3_IrqCtrl_Regs->iforce = (1U << (_source)); \ - } while (0) - -#define LEON_Enable_interrupt_broadcast( _source ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - uint32_t _mask = 1U << ( _source ); \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->bcast |= _mask; \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - } while (0) - -#define LEON_Disable_interrupt_broadcast( _source ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - uint32_t _mask = 1U << ( _source ); \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->bcast &= ~_mask; \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - } while (0) - -#define LEON_Is_interrupt_pending( _source ) \ - (LEON3_IrqCtrl_Regs->ipend & (1U << (_source))) - -#define LEON_Cpu_Is_interrupt_masked( _source, _cpu ) \ - (!(LEON3_IrqCtrl_Regs->mask[_cpu] & (1U << (_source)))) - -#define LEON_Cpu_Mask_interrupt( _source, _cpu ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] &= ~(1U << (_source)); \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - } while (0) - -#define LEON_Cpu_Unmask_interrupt( _source, _cpu ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] |= (1U << (_source)); \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - } while (0) - -#define LEON_Cpu_Disable_interrupt( _source, _previous, _cpu ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - uint32_t _mask = 1U << (_source); \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - (_previous) = LEON3_IrqCtrl_Regs->mask[_cpu]; \ - LEON3_IrqCtrl_Regs->mask[_cpu] = _previous & ~_mask; \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - (_previous) &= _mask; \ - } while (0) - -#define LEON_Cpu_Restore_interrupt( _source, _previous, _cpu ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - uint32_t _mask = 1U << (_source); \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] = \ - (LEON3_IrqCtrl_Regs->mask[_cpu] & ~_mask) | (_previous); \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - } while (0) - -/* Map single-cpu operations to local CPU */ -#define LEON_Is_interrupt_masked( _source ) \ - LEON_Cpu_Is_interrupt_masked(_source, _LEON3_Get_current_processor()) - -#define LEON_Mask_interrupt(_source) \ - LEON_Cpu_Mask_interrupt(_source, _LEON3_Get_current_processor()) - -#define LEON_Unmask_interrupt(_source) \ - LEON_Cpu_Unmask_interrupt(_source, _LEON3_Get_current_processor()) - -#define LEON_Disable_interrupt(_source, _previous) \ - LEON_Cpu_Disable_interrupt(_source, _previous, _LEON3_Get_current_processor()) - -#define LEON_Restore_interrupt(_source, _previous) \ - LEON_Cpu_Restore_interrupt(_source, _previous, _LEON3_Get_current_processor()) - -/* Make all SPARC BSPs have common macros for interrupt handling */ -#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) -#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) -#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) -#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) -#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) -#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) -#define BSP_Disable_interrupt(_source, _previous) \ - LEON_Disable_interrupt(_source, _prev) -#define BSP_Restore_interrupt(_source, _previous) \ - LEON_Restore_interrupt(_source, _previous) - -/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ -#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ - LEON_Cpu_Is_interrupt_masked(_source, _cpu) -#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ - LEON_Cpu_Unmask_interrupt(_source, _cpu) -#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ - LEON_Cpu_Mask_interrupt(_source, _cpu) -#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ - LEON_Cpu_Disable_interrupt(_source, _prev, _cpu) -#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ - LEON_Cpu_Restore_interrupt(_source, _previous, _cpu) - -/* - * Each timer control register is organized as follows: - * - * D0 - Enable - * 1 = enable counting - * 0 = hold scaler and counter - * - * D1 - Counter Reload - * 1 = reload counter at zero and restart - * 0 = stop counter at zero - * - * D2 - Counter Load - * 1 = load counter with preset value - * 0 = no function - * - */ - -#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 -#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 - -#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 - -#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 -#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 - -#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 -#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 - -#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 -#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 - -#if defined(RTEMS_MULTIPROCESSING) - #define LEON3_CLOCK_INDEX \ - (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0) -#else - #define LEON3_CLOCK_INDEX 0 -#endif - -/* - * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to - * run with 1MHz. This is used to determine all clock frequencies of the PnP - * devices. See also ambapp_freq_init() and ambapp_freq_get(). - */ -#define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 - -/* Load 32-bit word by forcing a cache-miss */ -static inline unsigned int leon_r32_no_cache(uintptr_t addr) -{ - unsigned int tmp; - __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); - return tmp; -} - -/* Let user override which on-chip APBUART will be debug UART - * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... - * 1 = APBUART[0] - * 2 = APBUART[1] - * 3 = APBUART[2] - * ... - */ -extern int syscon_uart_index; - -/* Let user override which on-chip APBUART will be debug UART - * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... - * 1 = APBUART[0] - * 2 = APBUART[1] - * 3 = APBUART[2] - * ... - */ -extern int leon3_debug_uart_index; - -/* Let user override which on-chip TIMER core will be used for system clock - * timer. This controls which timer core will be accociated with - * LEON3_Timer_Regs registers base address. This value will by destroyed during - * initialization. - * 0 = Default configuration. GPTIMER[0] - * 1 = GPTIMER[1] - * 2 = GPTIMER[2] - * ... - */ -extern int leon3_timer_core_index; - -/* Let user override system clock timer prescaler. This affects all timer - * instances on the system clock timer core determined by - * leon3_timer_core_index. - * 0 = Default configuration. Use bootloader configured value. - * N = Prescaler is set to N. N must not be less that number of timers. - * 8 = Prescaler is set to 8 (the fastest prescaler possible on all HW) - * ... - */ -extern unsigned int leon3_timer_prescaler; - -/* GRLIB extended IRQ controller register */ -void leon3_ext_irq_init(void); - -void leon3_power_down_loop(void) RTEMS_NO_RETURN; - -static inline uint32_t leon3_get_cpu_count( - volatile struct irqmp_regs *irqmp -) -{ - uint32_t mpstat = irqmp->mpstat; - - return ((mpstat >> LEON3_IRQMPSTATUS_CPUNR) & 0xf) + 1; -} - -static inline void leon3_set_system_register(uint32_t addr, uint32_t val) -{ - __asm__ volatile( - "sta %1, [%0] 2" - : - : "r" (addr), "r" (val) - ); -} - -static inline uint32_t leon3_get_system_register(uint32_t addr) -{ - uint32_t val; - - __asm__ volatile( - "lda [%1] 2, %0" - : "=r" (val) - : "r" (addr) - ); - - return val; -} - -static inline void leon3_set_cache_control_register(uint32_t val) -{ - leon3_set_system_register(0x0, val); -} - -static inline uint32_t leon3_get_cache_control_register(void) -{ - return leon3_get_system_register(0x0); -} - -static inline bool leon3_data_cache_snooping_enabled(void) -{ - return leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS; -} - -static inline uint32_t leon3_get_inst_cache_config_register(void) -{ - return leon3_get_system_register(0x8); -} - -static inline uint32_t leon3_get_data_cache_config_register(void) -{ - return leon3_get_system_register(0xc); -} - -static inline bool leon3_irqmp_has_timestamp( - volatile struct irqmp_timestamp_regs *irqmp_ts -) -{ - return (irqmp_ts->control >> 27) > 0; -} - -static inline uint32_t leon3_up_counter_low(void) -{ - uint32_t asr23; - - __asm__ volatile ( - "mov %%asr23, %0" - : "=&r" (asr23) - ); - - return asr23; -} - -static inline uint32_t leon3_up_counter_high(void) -{ - uint32_t asr22; - - __asm__ volatile ( - "mov %%asr22, %0" - : "=&r" (asr22) - ); - - return asr22; -} - -static inline void leon3_up_counter_enable(void) -{ - __asm__ volatile ( - "mov %g0, %asr22" - ); -} - -static inline bool leon3_up_counter_is_available(void) -{ - return leon3_up_counter_low() != leon3_up_counter_low(); -} - -static inline uint32_t leon3_up_counter_frequency(void) -{ - /* - * For simplicity, assume that the interrupt controller uses the processor - * clock. This is at least true on the GR740. - */ - return ambapp_freq_get(&ambapp_plb, LEON3_IrqCtrl_Adev); -} - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* !_INCLUDE_LEON_h */ -/* end of include file */ - diff --git a/c/src/lib/libbsp/sparc/leon3/include/tm27.h b/c/src/lib/libbsp/sparc/leon3/include/tm27.h deleted file mode 100644 index 00921d4880..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/tm27.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * @ingroup sparc_leon3 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * COPYRIGHT (c) 2006. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Since the interrupt code for the SPARC supports both synchronous - * and asynchronous trap handlers, support for testing with both - * is included. - */ - -#define SIS_USE_SYNCHRONOUS_TRAP 0 - -/* - * The synchronous trap is an arbitrarily chosen software trap. - */ - -#if (SIS_USE_SYNCHRONOUS_TRAP == 1) - -#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); - -#define Cause_tm27_intr() \ - __asm__ volatile( "ta 0x10; nop " ); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/* - * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. - */ - -#else /* use a regular asynchronous trap */ - -#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1 -#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) -#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 -#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); \ - set_vector( (handler), TEST_VECTOR2, 1 ); - -#define Cause_tm27_intr() \ - do { \ - LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \ - nop(); \ - nop(); \ - nop(); \ - } while (0) - -#define Clear_tm27_intr() \ - LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE ) - -#define Lower_tm27_intr() /* empty */ - -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon3/include/watchdog.h b/c/src/lib/libbsp/sparc/leon3/include/watchdog.h deleted file mode 100644 index 3c63be2a8f..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/watchdog.h +++ /dev/null @@ -1,49 +0,0 @@ -/* watchdog.h - * - * The LEON3 BSP timer watch-dog interface - * - * COPYRIGHT (c) 2012. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Initialize BSP watchdog routines. Returns number of watchdog timers found. - * Currently only one is supported. - */ -int bsp_watchdog_init(void); - -/* Reload watchdog (last timer on the first GPTIMER core), all systems does not - * feature a watchdog, it is expected that if this function is called the - * user knows that there is a watchdog available. - * - * The prescaler is normally set to number of MHz of system, this is to - * make the system clock tick be stable. - * - * Arguments - * watchdog - Always 0 for now - * reload_value - Number of timer clocks (after prescaler) to count before - * watchdog is woken. - */ -void bsp_watchdog_reload(int watchdog, unsigned int reload_value); - -/* Stop watchdog timer */ -void bsp_watchdog_stop(int watchdog); - -/* Use watchdog0 timer to reset the system */ -void bsp_watchdog_system_reset(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon3/preinstall.am b/c/src/lib/libbsp/sparc/leon3/preinstall.am deleted file mode 100644 index 4d00a43c18..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/preinstall.am +++ /dev/null @@ -1,363 +0,0 @@ -## Automatically generated by ampolish3 - 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-$(PROJECT_INCLUDE)/drvmgr/ambapp_bus_grlib.h: ../../sparc/shared/include/drvmgr/ambapp_bus_grlib.h $(PROJECT_INCLUDE)/drvmgr/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/drvmgr/ambapp_bus_grlib.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/drvmgr/ambapp_bus_grlib.h - -$(PROJECT_INCLUDE)/drvmgr/ambapp_bus.h: ../../sparc/shared/include/drvmgr/ambapp_bus.h $(PROJECT_INCLUDE)/drvmgr/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/drvmgr/ambapp_bus.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/drvmgr/ambapp_bus.h - -$(PROJECT_INCLUDE)/drvmgr/bspcommon.h: ../../sparc/shared/include/drvmgr/bspcommon.h $(PROJECT_INCLUDE)/drvmgr/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/drvmgr/bspcommon.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/drvmgr/bspcommon.h - -if HAS_NETWORKING -$(PROJECT_INCLUDE)/bsp/greth.h: ../../sparc/shared/include/greth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/greth.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/greth.h -endif -if HAS_NETWORKING -$(PROJECT_INCLUDE)/bsp/network_interface_add.h: ../../sparc/shared/include/network_interface_add.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/network_interface_add.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/network_interface_add.h -endif diff --git a/c/src/lib/libbsp/sparc/leon3/bsp_specs b/c/src/lib/libbsp/sparc/leon3/startup/bsp_specs index 87638cc027..87638cc027 100644 --- a/c/src/lib/libbsp/sparc/leon3/bsp_specs +++ b/c/src/lib/libbsp/sparc/leon3/startup/bsp_specs diff --git a/c/src/lib/libbsp/sparc/shared/include/ahbstat.h b/c/src/lib/libbsp/sparc/shared/include/ahbstat.h deleted file mode 100644 index 71e2330f69..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/ahbstat.h +++ /dev/null @@ -1,76 +0,0 @@ -/* AHBSTAT driver interface - * - * COPYRIGHT (c) 2011. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __AHBSTAT_H__ -#define __AHBSTAT_H__ - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* AHBSTAT Registers layout */ -struct ahbstat_regs { - volatile uint32_t status; - volatile uint32_t failing; -}; - -/* AHB fail interrupt callback to user. This function is declared weak so that - * the user can define a function pointer variable containing the address - * responsible for handling errors - * - * minor Index of AHBSTAT hardware - * regs Register address of AHBSTAT - * status AHBSTAT status register at IRQ - * failing_address AHBSTAT Failing address register at IRQ - * - * * User return - * 0: print error onto terminal with printk and reenable AHBSTAT - * 1: just re-enable AHBSTAT - * 2: just print error - * 3: do nothing, let user do custom handling - */ -extern int (*ahbstat_error)( - int minor, - struct ahbstat_regs *regs, - uint32_t status, - uint32_t failing_address); - -/* Get Last received AHB Error - * - * \param minor Index used to indentify a specific AHBSTAT core - * \param status Status register at time of error IRQ was recevied - * \param address Failing address register at time of error IRQ - * - * Return - * 0: No error received - * 1: Error Received, last status and address stored into argument pointers - * -1: No such AHBSTAT device - */ -extern int ahbstat_last_error(int minor, uint32_t *status, uint32_t *address); - -/* Get AHBSTAT registers address from minor. Can also be used to check if - * AHBSTAT hardware is present. - * - * Return - * NULL returned if no such device - * non-zero Address to AHBSTAT register - */ -extern struct ahbstat_regs *ahbstat_get_regs(int minor); - -/* Registers the AHBSTAT driver to the Driver Manager */ -void ahbstat_register_drv (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/ambapp.h b/c/src/lib/libbsp/sparc/shared/include/ambapp.h deleted file mode 100644 index 338602e83d..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/ambapp.h +++ /dev/null @@ -1,376 +0,0 @@ -/** - * @file - * @ingroup sparc_bsp - * @defgroup amba AMBA - * @ingroup amba - * @brief AMBA Plug &Play routines - */ - -/* - * COPYRIGHT (c) 2009. - * Aeroflex Gaisler. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __AMBAPP_H__ -#define __AMBAPP_H__ - -/* Include VENDOR and DEVICE definitions */ -#include <ambapp_ids.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Max supported AHB buses */ -#define AHB_BUS_MAX 6 - -struct ambapp_dev; -struct ambapp_core; -struct ambapp_apb_info; -struct ambapp_ahb_info; - -struct ambapp_dev { - struct ambapp_dev *next; /* Next */ - struct ambapp_dev *prev; /* Previous Device. If (this == - * rev->child) prev is bus bridge */ - struct ambapp_dev *children; /* Points to first device on sub-bus */ - void *owner; /* Owner of this AMBA device */ - unsigned char dev_type; /* AHB MST, AHB SLV or APB SLV*/ - unsigned char vendor; /* Vendor ID */ - unsigned short device; /* Device ID */ - int devinfo[0]; /* Device info (APB/AHB dep. on type) */ -}; - -#define AMBAPP_FLAG_FFACT_DIR 0x100 /* Frequency factor direction, 0=down, 1=up */ -#define AMBAPP_FLAG_FFACT 0x0f0 /* Frequency factor against top bus */ -#define AMBAPP_FLAG_MBUS 0x00c -#define AMBAPP_FLAG_SBUS 0x003 - -/* Get APB or AHB information from a AMBA device */ -#define DEV_TO_APB(adev) ((struct ambapp_apb_info *)((adev)->devinfo)) -#define DEV_TO_AHB(adev) ((struct ambapp_ahb_info *)((adev)->devinfo)) -#define DEV_TO_COMMON(adev) ((struct ambapp_common_info *)((adev)->devinfo)) -/* Convert address of ambapp_apb_info/ambapp_ahb_info into ambapp_dev */ -#define APB_TO_DEV(apb_info) ((struct ambapp_dev *)(unsigned int(apb_info) - \ - offsetof(struct ambapp_dev, devinfo))) -#define AHB_TO_DEV(ahb_info) ((struct ambapp_dev *)(unsigned int(ahb_info) - \ - offsetof(struct ambapp_dev, devinfo))) - -struct ambapp_common_info { - unsigned char irq; - unsigned char ver; - unsigned char ahbidx; /* AHB Bus Index */ -}; - -struct ambapp_apb_info { - /* COMMON */ - unsigned char irq; - unsigned char ver; - unsigned char ahbidx; /* AHB Bus Index */ - - /* APB SPECIFIC */ - unsigned int start; - unsigned int mask; -}; - -struct ambapp_ahb_info { - /* COMMON */ - unsigned char irq; - unsigned char ver; - unsigned char ahbidx; /* AHB Bus Index */ - - /* AHB SPECIFIC */ - unsigned int start[4]; - unsigned int mask[4]; - char type[4]; /* type[N] Determine type of start[N]-mask[N], - * 2=AHB Memory Space, 3=AHB I/O Space */ - unsigned int custom[3]; -}; - -/* Describes a complete AMBA Core. Each device may consist of 3 interfaces */ -struct ambapp_core { - char irq; /* irq=-1 indicate no IRQ */ - unsigned char vendor; - unsigned short device; - int index; /* Core index */ - struct ambapp_ahb_info *ahb_mst; - struct ambapp_ahb_info *ahb_slv; - struct ambapp_apb_info *apb_slv; -}; - -struct ambapp_ahb_bus { - unsigned int ioarea; /* AHB Bus IOAREA */ - unsigned int freq_hz; /* Frequency of AHB Bus */ - struct ambapp_dev *bridge;/* Bridge Device on Parent AHB Bus */ - struct ambapp_dev *dev; /* First Device on AHB Bus */ -}; - -struct ambapp_mmap { - unsigned int size; - unsigned int local_adr; - unsigned int remote_adr; -}; - -/* Complete AMBA PnP information */ -struct ambapp_bus { - struct ambapp_dev *root; /* AHB/APB Device Tree*/ - struct ambapp_mmap *mmaps; /* Memory MAP Array */ - struct ambapp_ahb_bus ahbs[AHB_BUS_MAX]; /* AHB Buses */ -}; - -/* - * Return values - * 0 - continue - * 1 - stop scanning - */ -typedef int (*ambapp_func_t)(struct ambapp_dev *dev, int index, void *arg); - -#define DEV_IS_FREE(dev) (dev->owner == NULL) -#define DEV_IS_ALLOCATED(dev) (dev->owner != NULL) - -/* Options to ambapp_for_each */ -#define OPTIONS_AHB_MSTS 0x00000001 -#define OPTIONS_AHB_SLVS 0x00000002 -#define OPTIONS_APB_SLVS 0x00000004 -#define OPTIONS_ALL_DEVS (OPTIONS_AHB_MSTS|OPTIONS_AHB_SLVS|OPTIONS_APB_SLVS) - -#define OPTIONS_FREE 0x00000010 -#define OPTIONS_ALLOCATED 0x00000020 -#define OPTIONS_ALL (OPTIONS_FREE|OPTIONS_ALLOCATED) - -/* Depth first search, Defualt is breath first search. */ -#define OPTIONS_DEPTH_FIRST 0x00000100 - -#define DEV_AHB_NONE 0 -#define DEV_AHB_MST 1 -#define DEV_AHB_SLV 2 -#define DEV_APB_SLV 3 - -/* Structures used to access Plug&Play information directly */ -struct ambapp_pnp_ahb { - const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ - const unsigned int custom[3]; - const unsigned int mbar[4]; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */ -}; - -struct ambapp_pnp_apb { - const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */ - const unsigned int iobar; /* MASK, ADDRESS, TYPE, CACHABLE/PREFETCHABLE */ -}; - -#define ambapp_pnp_vendor(id) (((id) >> 24) & 0xff) -#define ambapp_pnp_device(id) (((id) >> 12) & 0xfff) -#define ambapp_pnp_ver(id) (((id)>>5) & 0x1f) -#define ambapp_pnp_irq(id) ((id) & 0x1f) - -#define ambapp_pnp_start(mbar) (((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16)) -#define ambapp_pnp_mbar_mask(mbar) (((mbar)>>4) & 0xfff) -#define ambapp_pnp_mbar_type(mbar) ((mbar) & 0xf) - -#define ambapp_pnp_apb_start(iobar, base) ((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)) ) -#define ambapp_pnp_apb_mask(iobar) ((~(ambapp_pnp_mbar_mask(iobar)<<8) & 0x000fffff) + 1) - -#define AMBA_TYPE_AHBIO_ADDR(addr,base_ioarea) ((unsigned int)(base_ioarea) | ((addr) >> 12)) - -#define AMBA_TYPE_APBIO 0x1 -#define AMBA_TYPE_MEM 0x2 -#define AMBA_TYPE_AHBIO 0x3 - -/* Copy Data from AMBA PnP I/O Area */ -typedef void *(*ambapp_memcpy_t)( - void *dest, /* Destination RAM copy */ - const void *src, /* Source AMBA PnP Address to copy from */ - int n, /* Number of bytes to be copied */ - struct ambapp_bus *abus /* Optional AMBA Bus pointer */ - ); - -/* Scan a AMBA Plug & Play bus and create all device structures describing the - * the devices. The devices will form a tree, where every node describes one - * interface. The resulting tree is placed in the location pointed to by root. - * - * Since it the tree is located in RAM it is easier to work with AMBA buses - * that is located over PCI and SpaceWire etc. - * - * \param ioarea The IO-AREA where Plug & Play information can be found. - * \param parent Used internally when recursing down a bridge. Set to NULL. - * \param mmaps Is used to perform address translation if needed. - * \param root Resulting device node tree root is stored here. - * - */ -extern int ambapp_scan( - struct ambapp_bus *abus, - unsigned int ioarea, - ambapp_memcpy_t memfunc, - struct ambapp_mmap *mmaps - ); - -/* Initialize the frequency [Hz] of all AHB Buses from knowing the frequency - * of one particular APB/AHB Device. - */ -extern void ambapp_freq_init( - struct ambapp_bus *abus, - struct ambapp_dev *dev, - unsigned int freq); - -/* Returns the frequency [Hz] of a AHB/APB device */ -extern unsigned int ambapp_freq_get( - struct ambapp_bus *abus, - struct ambapp_dev *dev); - -/* Iterates through all AMBA devices previously found, it calls func - * once for every device that match the search arguments. - * - * SEARCH OPTIONS - * All search options must be fulfilled, type of devices searched (options) - * and AMBA Plug&Play ID [VENDOR,DEVICE], before func() is called. The options - * can be use to search only for AMBA APB or AHB Slaves or AHB Masters for - * example. Note that when VENDOR=-1 or DEVICE=-1 it will match any vendor or - * device ID, this means setting both VENDOR and DEVICE to -1 will result in - * calling all devices matches the options argument. - * - * \param abus AMBAPP Bus to search - * \param options Search options, see OPTIONS_* above - * \param vendor AMBAPP VENDOR ID to search for - * \param device AMBAPP DEVICE ID to search for - * \param func Function called for every device matching search options - * \param arg Optional argument passed on to func - * - * func return value affects the search, returning a non-zero value will - * stop the search and ambapp_for_each will return immediately returning the - * same non-zero value. - * - * Return Values - * 0 - all devices was scanned - * non-zero - stopped by user function returning the non-zero value - */ -extern int ambapp_for_each( - struct ambapp_bus *abus, - unsigned int options, - int vendor, - int device, - ambapp_func_t func, - void *arg); - -/* Helper function for ambapp_for_each(), find a device by index. If pcount - * is NULL the first device is returned, else pcount is interpreted as index - * by decrementing the value until zero is reaced: *count=0 first device, - * *count=1 second device etc. - * - * The matching device is returned, which will stop the ambapp_for_each search. - * If zero is returned from ambapp_for_each no device matching the index was - * found - */ -extern int ambapp_find_by_idx(struct ambapp_dev *dev, int index, void *pcount); - -/* Get number of devices matching the options/vendor/device arguments, the - * arguments are passed onto ambapp_for_each(). - */ -extern int ambapp_dev_count(struct ambapp_bus *abus, unsigned int options, - int vendor, int device); - -/* Print short information about devices on the AMBA bus onto the console */ -extern void ambapp_print(struct ambapp_bus *abus, int show_depth); - -/* Mark a device taken (allocate), Owner field is set with owner Data. Returns - * -1 if device has already been allocated. - */ -extern int ambapp_alloc_dev(struct ambapp_dev *dev, void *owner); - -/* Owner field is cleared, which indicates that device is not allocated */ -extern void ambapp_free_dev(struct ambapp_dev *dev); - -/* Find AHB/APB Bridge or AHB/AHB Bridge Parent */ -extern struct ambapp_dev *ambapp_find_parent(struct ambapp_dev *dev); - -/* Returns bus depth (number of sub AHB buses) of device from root bus */ -extern int ambapp_depth(struct ambapp_dev *dev); - -/* Get Device Name from AMBA PnP name database */ -extern char *ambapp_device_id2str(int vendor, int id); - -/* Get Vendor Name from AMBA PnP name database */ -extern char *ambapp_vendor_id2str(int vendor); - -/* Set together VENDOR_DEVICE Name from AMBA PnP name database. Return length - * of C-string stored in buf not including string termination '\0'. - */ -extern int ambapp_vendev_id2str(int vendor, int id, char *buf); - -/* Help functions for backwards compability */ - -extern int ambapp_find_apbslv( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_apb_info *dev); - -extern int ambapp_find_apbslv_next( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_apb_info *dev, - int index); - -extern int ambapp_find_apbslvs_next( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_apb_info *dev, - int index, - int maxno); - -extern int ambapp_find_apbslvs( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_apb_info *dev, - int maxno); - -extern int ambapp_find_ahbslv( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_ahb_info *dev); - -extern int ambapp_find_ahbslv_next( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_ahb_info *dev, - int index); - -extern int ambapp_find_ahbslvs_next( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_ahb_info *dev, - int index, - int maxno); - -extern int ambapp_find_ahbslvs( - struct ambapp_bus *abus, - int vendor, - int device, - struct ambapp_ahb_info *dev, - int maxno); - - -extern int ambapp_get_number_ahbslv_devices( - struct ambapp_bus *abus, - int vendor, - int device); - -extern int ambapp_get_number_apbslv_devices( - struct ambapp_bus *abus, - int vendor, - int device); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/ambapp_ids.h b/c/src/lib/libbsp/sparc/shared/include/ambapp_ids.h deleted file mode 100644 index c0c3547e94..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/ambapp_ids.h +++ /dev/null @@ -1,317 +0,0 @@ -/** - * @file - * @ingroup amba - * @brief AMBA Plug & Play Bus Vendor and Device IDs - */ - -/* - * COPYRIGHT (c) 2008. - * Gaisler Research - * - * This header file provide all known VENDOR and DEVICE IDs available - * in the AMBA Plug & Play information. Taken from GRLIB 3386. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef __AMBAPP_DEVS_H__ -#define __AMBAPP_DEVS_H__ - -/* Vendor codes */ -#define VENDOR_RESERVED 0x00 -#define VENDOR_GAISLER 0x01 -#define VENDOR_PENDER 0x02 -#define VENDOR_ESA 0x04 -#define VENDOR_ASTRIUM 0x06 -#define VENDOR_OPENCHIP 0x07 -#define VENDOR_OPENCORES 0x08 -#define VENDOR_CONTRIB 0x09 -#define VENDOR_DLR 0x0a -#define VENDOR_EONIC 0x0b -#define VENDOR_TELECOMPT 0x0c -#define VENDOR_DTU 0x0d -#define VENDOR_BSC 0x0e -#define VENDOR_RADIONOR 0x0f -#define VENDOR_GLEICHMANN 0x10 -#define VENDOR_MENTA 0x11 -#define VENDOR_SUN 0x13 -#define VENDOR_MOVIDIA 0x14 -#define VENDOR_ORBITA 0x17 -#define VENDOR_SIEMENS 0x1a -#define VENDOR_SYNOPSYS 0x21 -#define VENDOR_NASA 0x22 -#define VENDOR_NIIET 0x23 -#define VENDOR_S3 0x31 -#define VENDOR_ACTEL 0xac -#define VENDOR_APPLECORE 0xae -#define VENDOR_C3E 0xc3 -#define VENDOR_CBKPAN 0xc8 -#define VENDOR_CAL 0xca -#define VENDOR_CETON 0xcb -#define VENDOR_EMBEDDIT 0xea -#define VENDOR_NASA_GSFC 0xfc -#define VENDOR_AZST 0xfe - -/* Gaisler Research device id's */ -#define GAISLER_LEON2DSU 0x002 -#define GAISLER_LEON3 0x003 -#define GAISLER_LEON3DSU 0x004 -#define GAISLER_ETHAHB 0x005 -#define GAISLER_APBMST 0x006 -#define GAISLER_AHBUART 0x007 -#define GAISLER_SRCTRL 0x008 -#define GAISLER_SDCTRL 0x009 -#define GAISLER_SSRCTRL 0x00a -#define GAISLER_I2C2AHB 0x00b -#define GAISLER_APBUART 0x00c -#define GAISLER_IRQMP 0x00d -#define GAISLER_AHBRAM 0x00e -#define GAISLER_AHBDPRAM 0x00f -#define GAISLER_GRIOMMU2 0x010 -#define GAISLER_GPTIMER 0x011 -#define GAISLER_PCITRG 0x012 -#define GAISLER_PCISBRG 0x013 -#define GAISLER_PCIFBRG 0x014 -#define GAISLER_PCITRACE 0x015 -#define GAISLER_DMACTRL 0x016 -#define GAISLER_AHBTRACE 0x017 -#define GAISLER_DSUCTRL 0x018 -#define GAISLER_CANAHB 0x019 -#define GAISLER_GPIO 0x01a -#define GAISLER_AHBROM 0x01b -#define GAISLER_AHBJTAG 0x01c -#define GAISLER_ETHMAC 0x01d -#define GAISLER_SWNODE 0x01e -#define GAISLER_SPW 0x01f -#define GAISLER_AHB2AHB 0x020 -#define GAISLER_USBDC 0x021 -#define GAISLER_USB_DCL 0x022 -#define GAISLER_DDRMP 0x023 -#define GAISLER_ATACTRL 0x024 -#define GAISLER_DDRSP 0x025 -#define GAISLER_EHCI 0x026 -#define GAISLER_UHCI 0x027 -#define GAISLER_I2CMST 0x028 -#define GAISLER_SPW2 0x029 -#define GAISLER_AHBDMA 0x02a -#define GAISLER_NUHOSP3 0x02b -#define GAISLER_CLKGATE 0x02c -#define GAISLER_SPICTRL 0x02d -#define GAISLER_DDR2SP 0x02e -#define GAISLER_SLINK 0x02f -#define GAISLER_GRTM 0x030 -#define GAISLER_GRTC 0x031 -#define GAISLER_GRPW 0x032 -#define GAISLER_GRCTM 0x033 -#define GAISLER_GRHCAN 0x034 -#define GAISLER_GRFIFO 0x035 -#define GAISLER_GRADCDAC 0x036 -#define GAISLER_GRPULSE 0x037 -#define GAISLER_GRTIMER 0x038 -#define GAISLER_AHB2PP 0x039 -#define GAISLER_GRVERSION 0x03a -#define GAISLER_APB2PW 0x03b -#define GAISLER_PW2APB 0x03c -#define GAISLER_GRCAN 0x03d -#define GAISLER_I2CSLV 0x03e -#define GAISLER_U16550 0x03f -#define GAISLER_AHBMST_EM 0x040 -#define GAISLER_AHBSLV_EM 0x041 -#define GAISLER_GRTESTMOD 0x042 -#define GAISLER_ASCS 0x043 -#define GAISLER_IPMVBCTRL 0x044 -#define GAISLER_SPIMCTRL 0x045 -#define GAISLER_L4STAT 0x047 -#define GAISLER_LEON4 0x048 -#define GAISLER_LEON4DSU 0x049 -#define GAISLER_GRPWM 0x04a -#define GAISLER_PWM 0x04a -#define GAISLER_L2CACHE 0x04b -#define GAISLER_SDCTRL64 0x04c -#define GAISLER_GR1553B 0x04d -#define GAISLER_1553TST 0x04e -#define GAISLER_GRIOMMU 0x04f -#define GAISLER_FTAHBRAM 0x050 -#define GAISLER_FTSRCTRL 0x051 -#define GAISLER_AHBSTAT 0x052 -#define GAISLER_LEON3FT 0x053 -#define GAISLER_FTMCTRL 0x054 -#define GAISLER_FTSDCTRL 0x055 -#define GAISLER_FTSRCTRL8 0x056 -#define GAISLER_MEMSCRUB 0x057 -#define GAISLER_FTSDCTRL64 0x058 -#define GAISLER_NANDFCTRL 0x059 -#define GAISLER_N2DLLCTRL 0x05a -#define GAISLER_N2PLLCTRL 0x05b -#define GAISLER_SPI2AHB 0x05c -#define GAISLER_DDRSDMUX 0x05d -#define GAISLER_AHBFROM 0x05e -#define GAISLER_PCIEXP 0x05f -#define GAISLER_APBPS2 0x060 -#define GAISLER_VGACTRL 0x061 -#define GAISLER_LOGAN 0x062 -#define GAISLER_SVGACTRL 0x063 -#define GAISLER_T1AHB 0x064 -#define GAISLER_MP7WRAP 0x065 -#define GAISLER_GRSYSMON 0x066 -#define GAISLER_GRACECTRL 0x067 -#define GAISLER_ATAHBSLV 0x068 -#define GAISLER_ATAHBMST 0x069 -#define GAISLER_ATAPBSLV 0x06a -#define GAISLER_MIGDDR2 0x06b -#define GAISLER_LCDCTRL 0x06c -#define GAISLER_SWITCHOVER 0x06d -#define GAISLER_FIFOUART 0x06e -#define GAISLER_MUXCTRL 0x06f -#define GAISLER_B1553BC 0x070 -#define GAISLER_B1553RT 0x071 -#define GAISLER_B1553BRM 0x072 -#define GAISLER_GRAES 0x073 -#define GAISLER_AES 0x073 -#define GAISLER_ECC 0x074 -#define GAISLER_PCIF 0x075 -#define GAISLER_CLKMOD 0x076 -#define GAISLER_HAPSTRAK 0x077 -#define GAISLER_TEST_1X2 0x078 -#define GAISLER_WILD2AHB 0x079 -#define GAISLER_BIO1 0x07a -#define GAISLER_GRAESDMA 0x07b -#define GAISLER_AESDMA 0x07b -#define GAISLER_GRPCI2 0x07c -#define GAISLER_GRPCI2_DMA 0x07d -#define GAISLER_GRPCI2_TB 0x07e -#define GAISLER_MMA 0x07f -#define GAISLER_SATCAN 0x080 -#define GAISLER_CANMUX 0x081 -#define GAISLER_GRTMRX 0x082 -#define GAISLER_GRTCTX 0x083 -#define GAISLER_GRTMDESC 0x084 -#define GAISLER_GRTMVC 0x085 -#define GAISLER_GEFFE 0x086 -#define GAISLER_GPREG 0x087 -#define GAISLER_GRTMPAHB 0x088 -#define GAISLER_SPWCUC 0x089 -#define GAISLER_SPW2_DMA 0x08a -#define GAISLER_SPW_ROUTER 0x08b -#define GAISLER_SPWROUTER 0x08b -#define GAISLER_EDCLMST 0x08c -#define GAISLER_GRPWTX 0x08d -#define GAISLER_GRPWRX 0x08e -#define GAISLER_GPREGBANK 0x08f -#define GAISLER_MIG_7SERIES 0x090 -#define GAISLER_GRSPW2_SIST 0x091 -#define GAISLER_SGMII 0x092 -#define GAISLER_RGMII 0x093 -#define GAISLER_IRQGEN 0x094 -#define GAISLER_GRDMAC 0x095 -#define GAISLER_AHB2AVLA 0x096 -#define GAISLER_SPWTDP 0x097 -#define GAISLER_L3STAT 0x098 -#define GAISLER_GR740THS 0x099 -#define GAISLER_GRRM 0x09a -#define GAISLER_CMAP 0x09b -#define GAISLER_CPGEN 0x09c -#define GAISLER_AMBAPROT 0x09d -#define GAISLER_IGLOO2_BRIDGE 0x09e -#define GAISLER_AHB2AXI 0x09f -#define GAISLER_AXI2AHB 0x0a0 -#define GAISLER_FDIR_RSTCTRL 0x0a1 -#define GAISLER_APB3MST 0x0a2 -#define GAISLER_LRAM 0x0a3 -#define GAISLER_BOOTSEQ 0x0a4 -#define GAISLER_TCCOP 0x0a5 -#define GAISLER_SPIMASTER 0x0a6 -#define GAISLER_SPISLAVE 0x0a7 -#define GAISLER_GRSRIO 0x0a8 - -#define GAISLER_PIPEWRAPPER 0xffa -#define GAISLER_L2TIME 0xffd /* internal device: leon2 timer */ -#define GAISLER_L2C 0xffe /* internal device: leon2compat */ -#define GAISLER_PLUGPLAY 0xfff /* internal device: plug & play configarea */ - -/* European Space Agency device id's */ -#define ESA_LEON2 0x002 -#define ESA_LEON2APB 0x003 -#define ESA_IRQ 0x005 -#define ESA_TIMER 0x006 -#define ESA_UART 0x007 -#define ESA_CFG 0x008 -#define ESA_IO 0x009 -#define ESA_MCTRL 0x00f -#define ESA_PCIARB 0x010 -#define ESA_HURRICANE 0x011 -#define ESA_SPW_RMAP 0x012 -#define ESA_SPW2 0x012 -#define ESA_AHBUART 0x013 -#define ESA_SPWA 0x014 -#define ESA_BOSCHCAN 0x015 -#define ESA_IRQ2 0x016 -#define ESA_AHBSTAT 0x017 -#define ESA_WPROT 0x018 -#define ESA_WPROT2 0x019 -#define ESA_PDEC3AMBA 0x020 -#define ESA_PTME3AMBA 0x021 - -#define OPENCHIP_APBGPIO 0x001 -#define OPENCHIP_APBI2C 0x002 -#define OPENCHIP_APBSPI 0x003 -#define OPENCHIP_APBCHARLCD 0x004 -#define OPENCHIP_APBPWM 0x005 -#define OPENCHIP_APBPS2 0x006 -#define OPENCHIP_APBMMCSD 0x007 -#define OPENCHIP_APBNAND 0x008 -#define OPENCHIP_APBLPC 0x009 -#define OPENCHIP_APBCF 0x00a -#define OPENCHIP_APBSYSACE 0x00b -#define OPENCHIP_APB1WIRE 0x00c -#define OPENCHIP_APBJTAG 0x00d -#define OPENCHIP_APBSUI 0x00e - - -#define CONTRIB_CORE1 0x001 -#define CONTRIB_CORE2 0x002 - -#define GLEICHMANN_CUSTOM 0x001 -#define GLEICHMANN_GEOLCD01 0x002 -#define GLEICHMANN_DAC 0x003 -#define GLEICHMANN_HPI 0x004 -#define GLEICHMANN_SPI 0x005 -#define GLEICHMANN_HIFC 0x006 -#define GLEICHMANN_ADCDAC 0x007 -#define GLEICHMANN_SPIOC 0x008 -#define GLEICHMANN_AC97 0x009 - -#define SUN_T1 0x001 -#define SUN_S1 0x011 - -#define ORBITA_1553B 0x001 -#define ORBITA_429 0x002 -#define ORBITA_SPI 0x003 -#define ORBITA_I2C 0x004 -#define ORBITA_SMARTCARD 0x064 -#define ORBITA_SDCARD 0x065 -#define ORBITA_UART16550 0x066 -#define ORBITA_CRYPTO 0x067 -#define ORBITA_SYSIF 0x068 -#define ORBITA_PIO 0x069 -#define ORBITA_RTC 0x0c8 -#define ORBITA_COLORLCD 0x12c -#define ORBITA_PCI 0x190 -#define ORBITA_DSP 0x1f4 -#define ORBITA_USBHOST 0x258 -#define ORBITA_USBDEV 0x2bc - -#define NASA_EP32 0x001 - -#define CAL_DDRCTRL 0x188 - -#define ACTEL_COREMP7 0x001 - -/* Opencores device id's */ -#define OPENCORES_PCIBR 0x4 -#define OPENCORES_ETHMAC 0x5 - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/apbuart.h b/c/src/lib/libbsp/sparc/shared/include/apbuart.h deleted file mode 100644 index a324805d7d..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/apbuart.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * @file - * @ingroup sparc_bsp - * @defgroup uart UART - * @ingroup uart - * @brief Driver interface for APBUART - */ - -/* - * COPYRIGHT (c) 2007. - * Gaisler Research - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef __APBUART_H__ -#define __APBUART_H__ - -#include <ambapp.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define APBUART_CTRL_RE 0x1 -#define APBUART_CTRL_TE 0x2 -#define APBUART_CTRL_RI 0x4 -#define APBUART_CTRL_TI 0x8 -#define APBUART_CTRL_PS 0x10 -#define APBUART_CTRL_PE 0x20 -#define APBUART_CTRL_FL 0x40 -#define APBUART_CTRL_LB 0x80 -#define APBUART_CTRL_EC 0x100 -#define APBUART_CTRL_TF 0x200 -#define APBUART_CTRL_RF 0x400 -#define APBUART_CTRL_BI 0x1000 -#define APBUART_CTRL_DI 0x2000 -#define APBUART_CTRL_FA 0x80000000 - -#define APBUART_STATUS_DR 0x1 -#define APBUART_STATUS_TS 0x2 -#define APBUART_STATUS_TE 0x4 -#define APBUART_STATUS_BR 0x8 -#define APBUART_STATUS_OV 0x10 -#define APBUART_STATUS_PE 0x20 -#define APBUART_STATUS_FE 0x40 -#define APBUART_STATUS_ERR 0x78 -#define APBUART_STATUS_TH 0x80 -#define APBUART_STATUS_RH 0x100 -#define APBUART_STATUS_TF 0x200 -#define APBUART_STATUS_RF 0x400 - -#ifdef __cplusplus -} -#endif - -#endif /* __APBUART_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/apbuart_cons.h b/c/src/lib/libbsp/sparc/shared/include/apbuart_cons.h deleted file mode 100644 index d0ac9244af..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/apbuart_cons.h +++ /dev/null @@ -1,16 +0,0 @@ -/* APBUART Console driver interface - * - * COPYRIGHT (c) 2015. - * Cobham Gaisler. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __APBUART_CONS_H__ -#define __APBUART_CONS_H__ - -void apbuart_cons_register_drv (void); - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/apbuart_termios.h b/c/src/lib/libbsp/sparc/shared/include/apbuart_termios.h deleted file mode 100644 index 40377c1023..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/apbuart_termios.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * Modified for LEON3 BSP. - * COPYRIGHT (c) 2004. - * Gaisler Research. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef APBUART_TERMIOS_H -#define APBUART_TERMIOS_H - -#include <rtems/termiostypes.h> -#include <grlib.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -struct apbuart_context { - rtems_termios_device_context base; - struct apbuart_regs *regs; - unsigned int freq_hz; - rtems_vector_number irq; - volatile int sending; - char *buf; -}; - -const rtems_termios_device_handler apbuart_handler_interrupt; - -const rtems_termios_device_handler apbuart_handler_polled; - -/* - * apbuart_outbyte_polled - * - * This routine transmits a character using polling. - */ -void apbuart_outbyte_polled( - struct apbuart_regs *regs, - unsigned char ch, - int do_cr_on_newline, - int wait_sent -); - -/* - * apbuart_inbyte_nonblocking - * - * This routine polls for a character. - */ -int apbuart_inbyte_nonblocking(struct apbuart_regs *regs); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* APBUART_TERMIOS_H */ diff --git a/c/src/lib/libbsp/sparc/shared/include/b1553brm.h b/c/src/lib/libbsp/sparc/shared/include/b1553brm.h deleted file mode 100644 index eba0716f75..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/b1553brm.h +++ /dev/null @@ -1,178 +0,0 @@ -/** - * @file - * @ingroup sparc_bsp - * @defgroup 1553 B1553BRM - * @ingroup 1553 - * @brief B1553BRM device driver - */ - -/* - * COPYRIGHT (c) 2006. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __B1553BRM_H__ -#define __B1553BRM_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -struct brm_reg { - volatile unsigned int ctrl; /* 0x00 */ - volatile unsigned int oper; /* 0x04 */ - volatile unsigned int cur_cmd; /* 0x08 */ - volatile unsigned int imask; /* 0x0C */ - volatile unsigned int ipend; /* 0x10 */ - volatile unsigned int ipoint; /* 0x14 */ - volatile unsigned int bit_reg; /* 0x18 */ - volatile unsigned int ttag; /* 0x1C */ - volatile unsigned int dpoint; /* 0x20 */ - volatile unsigned int sw; /* 0x24 */ - volatile unsigned int initcount; /* 0x28 */ - volatile unsigned int mcpoint; /* 0x2C */ - volatile unsigned int mdpoint; /* 0x30 */ - volatile unsigned int mbc; /* 0x34 */ - volatile unsigned int mfilta; /* 0x38 */ - volatile unsigned int mfiltb; /* 0x3C */ - volatile unsigned int rt_cmd_leg[16]; /* 0x40-0x80 */ - volatile unsigned int enhanced; /* 0x84 */ - - volatile unsigned int dummy[31]; - - volatile unsigned int w_ctrl; /* 0x100 */ - volatile unsigned int w_irqctrl; /* 0x104 */ - volatile unsigned int w_ahbaddr; /* 0x108 */ -}; - -struct bm_msg { - unsigned short miw; - unsigned short cw1; - unsigned short cw2; - unsigned short sw1; - unsigned short sw2; - unsigned short time; - unsigned short data[32]; -}; - -struct rt_msg { - unsigned short miw; - unsigned short time; - unsigned short data[32]; - unsigned short desc; -}; - -/* - * rtaddr[0] and subaddr[0] : RT address and subaddress (for rt-rt receive addresses) - * rtaddr[1] and subaddr[1] : Only for RT-RT. Transmit addresses. - * - * wc : word count, or mode code if subaddress 0 or 31. - * - * ctrl, bit 0 (TR) : 1 - transmit, 0 - receive. Ignored for rt-rt - * bit 1 (RTRT) : 1 - rt to rt, 0 - normal - * bit 2 (AB) : 1 - Bus B, 0 - Bus A - * bit 4:3 (Retry) : 1 - 1, 2 - 2, 3 - 3, 0 - 4 - * bit 5 (END) : End of list - * bit 15 (BAME) : Message error. Set by BRM if protocol error is detected - * - * tsw[0] : status word - * tsw[1] : Only for rt-rt, status word 2 - * - * data : data to be transmitted, or received data - * - */ -struct bc_msg { - unsigned char rtaddr[2]; - unsigned char subaddr[2]; - unsigned short wc; - unsigned short ctrl; - unsigned short tsw[2]; - unsigned short data[32]; -}; - -/* BC control bits */ -#define BC_TR 0x0001 -#define BC_RTRT 0x0002 -#define BC_BUSA 0x0004 -#define BC_EOL 0x0020 -#define BC_SKIP 0x0040 -#define BC_BAME 0x8000 - -#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */ -#define BRM_CBA_IRQ 2 /* Command Block Accessed irq */ -#define BRM_RTF_IRQ 4 /* Retry Fail irq */ -#define BRM_ILLOP_IRQ 8 /* Illogical Opcode irq */ -#define BRM_BC_ILLCMD_IRQ 16 /* BC Illocigal Command irq */ -#define BRM_EOL_IRQ 32 /* End Of List irq */ -#define BRM_RT_ILLCMD_IRQ 128 /* RT Illegal Command irq */ -#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */ -#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */ -#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */ -#define BRM_MERR_IRQ 2048 /* Message Error irq */ -#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */ -#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */ -#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */ - - -#define BRM_SET_MODE 0 -#define BRM_SET_BUS 1 -#define BRM_SET_MSGTO 2 -#define BRM_SET_RT_ADDR 3 -#define BRM_SET_STD 4 -#define BRM_SET_BCE 5 -#define BRM_TX_BLOCK 7 -#define BRM_RX_BLOCK 8 - -#define BRM_DO_LIST 10 -#define BRM_LIST_DONE 11 - -#define BRM_CLR_STATUS 12 -#define BRM_GET_STATUS 13 -#define BRM_SET_EVENTID 14 - -#define GET_ERROR_DESCRIPTOR(event_in) (event_in>>16) - - -#define BRM_MODE_BC 0x0 -#define BRM_MODE_RT 0x1 -#define BRM_MODE_BM 0x2 -#define BRM_MODE_BM_RT 0x3 /* both RT and BM */ - -#define BRM_FREQ_12MHZ 0 -#define BRM_FREQ_16MHZ 1 -#define BRM_FREQ_20MHZ 2 -#define BRM_FREQ_24MHZ 3 -#define BRM_FREQ_MASK 0x3 - -#define CLKDIV_MASK 0xf - -#define CLKSEL_MASK 0x7 - -void b1553brm_register_drv(void); - -/* Default initialization of the RT legalization registers. The values in this - * array are written to the registers on boot driver initialization and when - * the user set the mode to RT-mode by calling ioctl(BRM_SET_MODE). Thus, - * update the array first then call ioctl(BRM_SET_MODE) for the changes to have - * an affect. Note that this affects all B1553BRM RTs in the system. - */ -extern unsigned short b1553brm_rt_cmd_legalize[16]; - -/* Print information about all BRM devices handled by this driver */ -void b1553brm_print(int options); - -/* Print information about one BRM device */ -void b1553brm_print_dev(struct drvmgr_dev *dev, int options); - -#ifdef __cplusplus -} -#endif - -#endif /* __BRM_H__ */ - diff --git a/c/src/lib/libbsp/sparc/shared/include/b1553rt.h b/c/src/lib/libbsp/sparc/shared/include/b1553rt.h deleted file mode 100644 index fbe4b706de..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/b1553rt.h +++ /dev/null @@ -1,79 +0,0 @@ -/* B1553RT driver interface - * - * COPYRIGHT (c) 2009. - * Aeroflex Gaisler AB - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __B1553RT_H__ -#define __B1553RT_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -struct rt_reg { - volatile unsigned int stat; /* 0x00 */ - volatile unsigned int ctrl; /* 0x04 */ - volatile unsigned int vword; /* 0x08 */ - volatile unsigned int irq; /* 0x0C */ - volatile unsigned int addr; /* 0x10 */ - volatile unsigned int ipm; /* 0x14 */ -}; - - -struct rt_msg { - unsigned short miw; - unsigned short time; - unsigned short data[32]; - unsigned short desc; -}; - -#define RT_FREQ_12MHZ 0 -#define RT_FREQ_16MHZ 1 -#define RT_FREQ_20MHZ 2 -#define RT_FREQ_24MHZ 3 -#define RT_FREQ_MASK 0x3 - -/* IOCTLs */ -#define RT_SET_ADDR 3 -#define RT_SET_BCE 5 -#define RT_RX_BLOCK 8 -#define RT_CLR_STATUS 12 -#define RT_GET_STATUS 13 -#define RT_SET_EVENTID 14 - -#define RT_SET_VECTORW 32 -#define RT_SET_EXTMDATA 33 - -#define RT_ILLCMD_IRQ 128 -#define RT_MERR_IRQ 2048 -#define RT_DMAF_IRQ 32768 /* DMA Fail irq */ - -#define RT_TSW_OK (1<<14) -#define RT_TSW_BUS (1<<13) -#define RT_TSW_BC (1<<12) -#define RT_TSW_LPBKERRB (1<<11) -#define RT_TSW_LPBKERRA (1<<10) -#define RT_TSW_ILL (1<<9) -#define RT_TSW_MEM (1<<8) -#define RT_TSW_MAN (1<<7) -#define RT_TSW_PAR (1<<6) -#define RT_TSW_WC (1<<5) - -void b1553rt_print_dev(struct drvmgr_dev *dev, int options); -void b1553rt_print(int options); - -void b1553rt_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __RT_H__ */ - diff --git a/c/src/lib/libbsp/sparc/shared/include/canmux.h b/c/src/lib/libbsp/sparc/shared/include/canmux.h deleted file mode 100644 index 02727f44c7..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/canmux.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Header file for RTEMS CAN_MUX driver - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __CANMUX_H__ -#define __CANMUX_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Driver interface */ -int canmux_register(void); - -/* ioctl calls */ -#define CANMUX_IOC_BUSA_SATCAN 1 -#define CANMUX_IOC_BUSA_OCCAN1 2 -#define CANMUX_IOC_BUSB_SATCAN 3 -#define CANMUX_IOC_BUSB_OCCAN2 4 - -#ifdef __cplusplus -} -#endif - -#endif /* __CANMUX_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/cons.h b/c/src/lib/libbsp/sparc/shared/include/cons.h deleted file mode 100644 index c30e41cf14..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/cons.h +++ /dev/null @@ -1,42 +0,0 @@ -/* Console driver interface to UART drivers - * - * - First console device that has System Console flag set will be - * system console. - * - If none of the registered console devices has system console set, - * the first is registered device is used, unless it has - * - * COPYRIGHT (c) 2010. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __CONS_H__ -#define __CONS_H__ - -#include <rtems/termiostypes.h> - -struct console_dev; - -#define CONSOLE_FLAG_SYSCON 0x01 -#define CONSOLE_FLAG_SYSCON_GRANT 0x02 - -struct console_dev { - rtems_termios_device_context base; - /* Set CONSOLE_FLAG_SYSCON to request this device to be system console - * and/or debug console. CONSOLE_FLAG_SYSCON_GRANT will be set on the - * device which was selected as system console. - */ - int flags; - char *fsname; /* File system prefix */ - const rtems_termios_device_handler *handler; -}; - -extern void console_dev_register(struct console_dev *dev); -#if 0 -extern void console_dev_unregister(struct console_dev *dev); -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/debug_defs.h b/c/src/lib/libbsp/sparc/shared/include/debug_defs.h deleted file mode 100644 index 58f7460f52..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/debug_defs.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * @ingroup bsp_kit - * @defgroup sparc_bsp SPARC - * @ingroup sparc_bsp - * @brief Debug Definitions - */ - -#ifndef __DEBUG_DEFS_H__ -#define __DEBUG_DEFS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#ifdef DEBUG - - #ifndef DEBUG_FLAGS - #define DEBUG_FLAGS 0 - #endif - - #define DBG(fmt, args...) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); } while(0) - #define DBG2(fmt) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__); } while(0) - #define DBGC(c,fmt, args...) do { if (DEBUG_FLAGS & c) { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); }} while(0) - -#else - - #define DBG(fmt, args...) - #define DBG2(fmt, args...) - #define DBGC(c, fmt, args...) - -#endif - -#ifdef DEBUGFUNCS - #define FUNCDBG() do { printk("%s\n\r",__FUNCTION__); } while(0) -#else - #define FUNCDBG() -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __DEBUG_DEFS_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/drvmgr/ambapp_bus.h b/c/src/lib/libbsp/sparc/shared/include/drvmgr/ambapp_bus.h deleted file mode 100644 index d034aae3a3..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/drvmgr/ambapp_bus.h +++ /dev/null @@ -1,142 +0,0 @@ -/* General part of a AMBA Plug & Play bus driver. - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * This is the general part of the different AMBA Plug & Play - * drivers. The drivers are wrappers around this driver, making - * the code size smaller for systems with multiple AMBA Plug & - * Play buses. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __AMBAPP_BUS_H__ -#define __AMBAPP_BUS_H__ - -#include <drvmgr/drvmgr.h> -#include <ambapp.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* GRLIB AMBA Plug&Play Driver ID generation */ -#define DRIVER_AMBAPP_ID(vendor, device) \ - DRIVER_ID(DRVMGR_BUS_TYPE_AMBAPP, ((((vendor) & 0xff) << 16) | ((device) & 0xfff))) - -/*** Gaisler Hardware Device Driver IDs ***/ -#define DRIVER_AMBAPP_GAISLER_AHBSTAT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_AHBSTAT) -#define DRIVER_AMBAPP_GAISLER_APBUART_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_APBUART) -#define DRIVER_AMBAPP_GAISLER_B1553BRM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_B1553BRM) -#define DRIVER_AMBAPP_GAISLER_B1553RT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_B1553RT) -#define DRIVER_AMBAPP_GAISLER_GPTIMER_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GPTIMER) -#define DRIVER_AMBAPP_GAISLER_GR1553B_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GR1553B) -#define DRIVER_AMBAPP_GAISLER_GRADCDAC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRADCDAC) -#define DRIVER_AMBAPP_GAISLER_GRAES_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRAESDMA) -#define DRIVER_AMBAPP_GAISLER_GRCAN_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRCAN) -#define DRIVER_AMBAPP_GAISLER_GRCTM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRCTM) -#define DRIVER_AMBAPP_GAISLER_GRETH_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_ETHMAC) -#define DRIVER_AMBAPP_GAISLER_GRGPIO_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GPIO) -#define DRIVER_AMBAPP_GAISLER_GRPCI2_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRPCI2) -#define DRIVER_AMBAPP_GAISLER_GRIOMMU_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRIOMMU) -#define DRIVER_AMBAPP_GAISLER_GRPCI_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCIFBRG) -#define DRIVER_AMBAPP_GAISLER_GRPWM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRPWM) -#define DRIVER_AMBAPP_GAISLER_GRPWRX_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PW2APB) -#define DRIVER_AMBAPP_GAISLER_GRSPW_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW) -#define DRIVER_AMBAPP_GAISLER_GRSPW2_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW2) -#define DRIVER_AMBAPP_GAISLER_GRTC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRTC) -#define DRIVER_AMBAPP_GAISLER_GRTM_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_GRTM) -#define DRIVER_AMBAPP_GAISLER_I2CMST_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_I2CMST) -#define DRIVER_AMBAPP_GAISLER_OCCAN_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_CANAHB) -#define DRIVER_AMBAPP_GAISLER_PCIF_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCIF) -#define DRIVER_AMBAPP_GAISLER_PCITRACE_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_PCITRACE) -#define DRIVER_AMBAPP_GAISLER_SPICTRL_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPICTRL) -#define DRIVER_AMBAPP_GAISLER_SPWCUC_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPWCUC) -#define DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_SPW_ROUTER) -#define DRIVER_AMBAPP_GAISLER_L2CACHE_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_L2CACHE) -#define DRIVER_AMBAPP_GAISLER_MEMSCRUB_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_MEMSCRUB) -#define DRIVER_AMBAPP_GAISLER_L4STAT_ID DRIVER_AMBAPP_ID(VENDOR_GAISLER, GAISLER_L4STAT) - -/*** ESA Hardware Device Driver IDs ***/ -#define DRIVER_AMBAPP_ESA_MCTRL_ID DRIVER_AMBAPP_ID(VENDOR_ESA, ESA_MCTRL) -#define DRIVER_AMBAPP_MCTRL_ID DRIVER_AMBAPP_ESA_MCTRL_ID - -struct amba_dev_id { - unsigned short vendor; - unsigned short device; - /* Version ? */ -}; - -struct amba_drv_info { - struct drvmgr_drv general; /* General bus info */ - /* AMBA specific bus information */ - struct amba_dev_id *ids; /* Supported hardware */ -}; - -struct amba_dev_info { - struct amba_dev_id id; - struct ambapp_core info; -}; - -struct ambapp_ops { - int (*int_register) - (struct drvmgr_dev *dev, int index, const char *info, drvmgr_isr isr, void *arg); - int (*int_unregister) - (struct drvmgr_dev *dev, int index, drvmgr_isr isr, void *arg); - int (*int_clear)(struct drvmgr_dev *dev, int index); - int (*int_mask)(struct drvmgr_dev *dev, int index); - int (*int_unmask)(struct drvmgr_dev *dev, int index); -#ifdef RTEMS_SMP - int (*int_set_affinity)(struct drvmgr_dev *dev, int index, - const Processor_mask *cpus); -#endif - int (*get_params) - (struct drvmgr_dev *, struct drvmgr_bus_params *); -}; - -struct ambapp_config { - struct ambapp_bus *abus; /* Prescanned AMBA PnP bus */ - struct ambapp_ops *ops; /* AMBA bus operations */ - struct drvmgr_map_entry *maps_up; /* Bus memory map up-stream towards CPU */ - struct drvmgr_map_entry *maps_down; /* Bus memory map down-stream towards HW */ - struct drvmgr_bus_res *resources; /* Driver Resources */ - int bus_type; /* Set DRVMGR_BUS_TYPE_AMBAPP_DIST if distributed AMBA Bus */ - struct drvmgr_func *funcs; /* Custom functions */ -}; - -/*** Bus operations with READ/WRITE access operations *** - * - * The functions are implemented using the standard drvmgr RW interface - */ -#define AMBAPP_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_REG) -#define AMBAPP_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_REG) -#define AMBAPP_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_REG) -#define AMBAPP_R64 DRVMGR_RWFUNC(RW_SIZE_8|RW_READ|RW_REG) -#define AMBAPP_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_REG) -#define AMBAPP_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_REG) -#define AMBAPP_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_REG) -#define AMBAPP_W64 DRVMGR_RWFUNC(RW_SIZE_8|RW_WRITE|RW_REG) -#define AMBAPP_RMEM DRVMGR_RWFUNC(RW_SIZE_ANY|RW_READ|RW_MEM) -#define AMBAPP_WMEM DRVMGR_RWFUNC(RW_SIZE_ANY|RW_WRITE|RW_MEM) -#define AMBAPP_MEMSET DRVMGR_RWFUNC(RW_SIZE_ANY|RW_SET|RW_MEM) -#define AMBAPP_RW_ARG DRVMGR_RWFUNC(RW_ARG) - -/* Register an ambapp bus on-top of a device */ -extern int ambapp_bus_register( - struct drvmgr_dev *dev, - struct ambapp_config *config - ); - -extern void ambapp_bus_freq_register( - struct drvmgr_dev *dev, - int amba_interface, - unsigned int freq_hz); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/drvmgr/ambapp_bus_grlib.h b/c/src/lib/libbsp/sparc/shared/include/drvmgr/ambapp_bus_grlib.h deleted file mode 100644 index 2def4bc2b4..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/drvmgr/ambapp_bus_grlib.h +++ /dev/null @@ -1,36 +0,0 @@ -/* LEON3 GRLIB AMBA Plug & Play bus driver interface. - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * This is driver is a wrapper for the general AMBA Plug & Play bus - * driver. This is the root bus driver for GRLIB systems. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __AMBAPP_BUS_GRLIB_H__ -#define __AMBAPP_BUS_GRLIB_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -struct grlib_config { - struct ambapp_bus *abus; - struct drvmgr_bus_res *resources; -}; - -/* Register GRLIB AMBA PnP Bus as root bus at driver manager */ -extern int ambapp_grlib_root_register(struct grlib_config *config); - -/* Register bus driver to Driver Manager */ -void ambapp_grlib_register(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/drvmgr/bspcommon.h b/c/src/lib/libbsp/sparc/shared/include/drvmgr/bspcommon.h deleted file mode 100644 index d3470009f8..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/drvmgr/bspcommon.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Common BSP/driver configuration routines. - * - * COPYRIGHT (c) 2015. - * Cobham Gaisler. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef __BSPCOMMON_H__ -#define __BSPCOMMON_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Count driver resource array length. Array must be terminated with a NULL */ -int get_resarray_count(struct drvmgr_bus_res **array); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/drvmgr/leon2_amba_bus.h b/c/src/lib/libbsp/sparc/shared/include/drvmgr/leon2_amba_bus.h deleted file mode 100644 index ebb3a08486..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/drvmgr/leon2_amba_bus.h +++ /dev/null @@ -1,95 +0,0 @@ -/* LEON2 Hardcoded bus driver interface. - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * Bus driver for a hardcoded setup. LEON2 systems have some - * cores always present, here called "Standard Cores". In - * addtion to the standard cores there are often extra cores - * that can be defined using the "Custom Cores" mechanism. - * - * A Core is described by assigning a base register and - * IRQ0..IRQ15 using the leon2_core structure. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __LEON2_AMBA_BUS_H__ -#define __LEON2_AMBA_BUS_H__ - -/*** Cores location and IRQs hardcoded ***/ - -#include <drvmgr/drvmgr.h> -#include <ambapp.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* LEON2 AMBA Driver ID generation */ -#define DRIVER_LEON2_AMBA(id) DRIVER_ID(DRVMGR_BUS_TYPE_LEON2_AMBA, id) - -/* LEON2 Cores (any unique 48-bit number will do) */ -#define LEON2_AMBA_NONE_ID 0 -#define LEON2_AMBA_TIMER_ID 1 -#define LEON2_AMBA_UART_ID 2 -#define LEON2_AMBA_GPIO_ID 3 -#define LEON2_AMBA_IRQCTRL_ID 4 - -#define LEON2_AMBA_AT697PCI_ID 100 -#define LEON2_AMBA_AMBAPP_ID 0xfff0 - -/* LEON2 driver IDs */ -#define DRIVER_LEON2_AMBA_TIMER DRIVER_LEON2_AMBA(LEON2_AMBA_TIMER_ID) -#define DRIVER_LEON2_AMBA_UART DRIVER_LEON2_AMBA(LEON2_AMBA_UART_ID) -#define DRIVER_LEON2_AMBA_AT697PCI DRIVER_LEON2_AMBA(LEON2_AMBA_AT697PCI_ID) -#define DRIVER_LEON2_AMBA_AMBAPP DRIVER_LEON2_AMBA(LEON2_AMBA_AMBAPP_ID) - -struct leon2_amba_dev_id { - unsigned short core_id; -}; - -#define EMPTY_LEON2_CORE {{LEON2_AMBA_NONE_ID}, NULL, NULL} -struct leon2_core { - struct leon2_amba_dev_id id; /* Core ID */ - char *name; /* Name of Core */ - struct drvmgr_key *keys; /* Core setup (location, IRQs) */ -}; - -struct leon2_bus { - struct leon2_core *std_cores; /* The LEON2 standard cores */ - struct leon2_core *custom_cores; /* Custom cores on the same bus */ - struct drvmgr_map_entry *maps_up; /* Memory map ip-stream */ - struct drvmgr_map_entry *maps_down; /* Memory map down-stream */ -}; - -extern struct leon2_core leon2_std_cores[]; - -/* Data structure drivers can access */ -struct leon2_amba_dev_info { - unsigned short core_id; /* Core ID */ - unsigned int reg_base; /* Register base */ - char irqs[16]; /* 16 irqs */ -}; - -struct leon2_amba_drv_info { - struct drvmgr_drv general; /* General bus info */ - /* AMBA specific bus information */ - struct leon2_amba_dev_id *ids; /* Supported hardware */ -}; - -/* Initialize LEON2 bus with a configuration - * bus_config - What cores, their location and irqs - * resources - Driver configuration for the cores specified bus_config - */ -int leon2_root_register( - struct leon2_bus *bus_config, - struct drvmgr_bus_res *resources); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/genirq.h b/c/src/lib/libbsp/sparc/shared/include/genirq.h deleted file mode 100644 index 673be173b1..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/genirq.h +++ /dev/null @@ -1,132 +0,0 @@ -/* General Shared Interrupt handling function interface - * - * The functions does not manipulate the IRQ controller or the - * interrupt level of the CPU. It simply helps the caller with - * managing shared interrupts where multiple interrupt routines - * share on interrupt vector/number. - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GENIRQ_H__ -#define __GENIRQ_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -typedef void (*genirq_handler)(void *arg); -typedef void* genirq_t; - -struct genirq_stats { - unsigned int irq_cnt; -}; - -/* Initialize the genirq interface. Must be the first function - * called. - * - * Returns zero on success, otherwise failure. - */ -extern genirq_t genirq_init(int number_of_irqs); - -/* Free the dynamically allocated memory that the genirq interface has - * allocated. Also the handlers will be freed. - * - * Returns zero on success, otherwise failure. - */ -extern void genirq_destroy(genirq_t d); - -/* Check IRQ number validity - * - * Returns zero for valid IRQ numbers, -1 of invalid IRQ numbers. - */ -extern int genirq_check(genirq_t d, int irq); - -/* Allocate one ISR handler and initialize it. Input to genirq_register(). - * - * \param isr The interrupt service routine called upon IRQ - * \param arg The argument given to isr() when called. - * - * Returns a pointer on success, on failure NULL is returned. - */ -extern void *genirq_alloc_handler(genirq_handler isr, void *arg); - -/* Free handler memory */ -#define genirq_free_handler(handler) free(handler) - -/* Register shared interrupt handler previously initialized with - * genirq_alloc_handler(). - * - * NOTE: internal list structures are accessed and needs to be protected by - * spin-locks/IRQ disable by the user to guarantee a correct behaviour. - * - * \param irq The interrupt number to register ISR on - * \param handler Install the pre- allocated and initialized handler. - * - * Return Values - * -1 = Failed - * 0 = Handler registered Successfully, first handler on this IRQ - * 1 = Handler registered Successfully, _not_ first handler on this IRQ - */ -extern int genirq_register(genirq_t d, int irq, void *handler); - -/* Unregister an previous registered interrupt handler. It is the user's - * responsibility to free the handler returned by genirq_unregister(). - * - * NOTE: internal list structures are accessed and needs to be protected by - * spin-locks/IRQ disable by the user to guarantee a correct behaviour. - * - * Return Values - * NULL = ISR not registered before or unable to unregister enabled ISR - * Pointer = ISR sucessfully unregistered. Returned is the handler pointer - * previously allocated with genirq_alloc_handler(). - */ -extern void *genirq_unregister(genirq_t d, int irq, - genirq_handler isr, void *arg); - -/* Enables IRQ only for this isr[arg] combination. Records if this - * is the first interrupt enable, only then must interrupts be enabled - * on the interrupt controller. - * - * NOTE: internal list structures are accessed and needs to be protected by - * spin-locks/IRQ disable by the user to guarantee a correct behaviour. - * - * Return values - * -1 = Failure, for example isr[arg] not registered on this irq - * 0 = IRQ must be enabled, it is the first IRQ handler to be enabled - * 1 = IRQ has already been enabled, either by isr[arg] or by another handler - */ -extern int genirq_enable(genirq_t d, int irq, genirq_handler isr, void *arg); - -/* Disables IRQ only for this isr[arg] combination. Records if this - * is the only interrupt handler that is enabled on this IRQ, only then - * must interrupts be disabled on the interrupt controller. - * - * NOTE: internal list structures are accessed and needs to be protected by - * spin-locks/IRQ disable by the user to guarantee a correct behaviour. - * - * Return values - * -1 = Failure, for example isr[arg] not registered on this irq - * 0 = IRQ must be disabled, no ISR are enabled for this IRQ - * 1 = ISR has already been disabled, or other ISRs are still enabled - */ -extern int genirq_disable(genirq_t d, int irq, genirq_handler isr, void *arg); - -/* Must be called by user when an IRQ has fired, the argument 'irq' - * is the IRQ number of the IRQ which was fired. - * - * NOTE: internal list structures are accessed and needs to be protected by - * spin-locks/IRQ disable by the user to guarantee a correct behaviour. - */ -extern void genirq_doirq(genirq_t d, int irq); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gnatcommon.h b/c/src/lib/libbsp/sparc/shared/include/gnatcommon.h deleted file mode 100644 index 1a04449293..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gnatcommon.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __GNATCOMMON_H -#define __GNATCOMMON_H - -/* - * Support for gnat/rtems interrupts and exception handling. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -void __gnat_install_handler (void); -void __gnat_install_handler_common (int t1, int t2); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gpiolib.h b/c/src/lib/libbsp/sparc/shared/include/gpiolib.h deleted file mode 100644 index f82d4fa2c2..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gpiolib.h +++ /dev/null @@ -1,94 +0,0 @@ -/* GPIO Library interface - * - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GPIOLIB_H__ -#define __GPIOLIB_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* GPIO Config of one GPIO port */ -struct gpiolib_config { - char mask; /* 0=Masked/1=Unmasked IRQ */ - char irq_level; /* Edge or Level triggered IRQ */ - char irq_polarity; /* Polarity of IRQ */ -}; - -#define GPIOLIB_IRQ_EDGE 0 -#define GPIOLIB_IRQ_LEVEL 1 - -#define GPIOLIB_IRQ_POL_LOW 0 -#define GPIOLIB_IRQ_POL_HIGH 1 - -/* Libarary initialize function must be called befor any other */ -extern int gpiolib_initialize(void); - -/*** User Interface ***/ - -extern void *gpiolib_open(int port); -extern void *gpiolib_open_by_name(char *devName); -extern void gpiolib_close(void *handle); - -/* Show the current status one or all GPIO ports in the system. - * Int port is port nunber, if port = -1 selects all ports. - * - * If port != -1, handle is used to get port. - * If port != -1, handle == NULL, then port is used as port number - */ -extern void gpiolib_show(int port, void *handle); - -extern int gpiolib_set_config(void *handle, struct gpiolib_config *cfg); -extern int gpiolib_set(void *handle, int dir, int val); -extern int gpiolib_get(void *handle, int *inval); -extern int gpiolib_irq_clear(void *handle); -extern int gpiolib_irq_enable(void *handle); -extern int gpiolib_irq_disable(void *handle); -extern int gpiolib_irq_mask(void *handle); -extern int gpiolib_irq_unmask(void *handle); -extern int gpiolib_irq_force(void *handle); -extern int gpiolib_irq_register(void *handle, void *func, void *arg); - -/*** Driver Interface ***/ - -struct gpiolib_info { - char devName[64]; -}; - -struct gpiolib_drv_ops { - int (*config)(void *handle, struct gpiolib_config *cfg); - int (*get)(void *handle, int *val); - int (*irq_opts)(void *handle, unsigned int options); - int (*irq_register)(void *handle, void *func, void *arg); - int (*open)(void *handle); - int (*set)(void *handle, int dir, int outval); - int (*show)(void *handle); - int (*get_info)(void *handle, struct gpiolib_info *pinfo); -}; - -#define GPIOLIB_IRQ_ENABLE 0x01 -#define GPIOLIB_IRQ_DISABLE 0x02 -#define GPIOLIB_IRQ_CLEAR 0x04 -#define GPIOLIB_IRQ_FORCE 0x08 -#define GPIOLIB_IRQ_MASK 0x10 -#define GPIOLIB_IRQ_UNMASK 0x20 - -struct gpiolib_drv { - struct gpiolib_drv_ops *ops; -}; - -/* Register a GPIO port */ -extern int gpiolib_drv_register(struct gpiolib_drv *drv, void *handle); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gptimer.h b/c/src/lib/libbsp/sparc/shared/include/gptimer.h deleted file mode 100644 index ee0120d2bd..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gptimer.h +++ /dev/null @@ -1,30 +0,0 @@ -/* GPTIMER and GRTIMER timer driver - * - * COPYRIGHT (c) 2015. - * Cobham Gaisler. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef __GPTIMER_H__ -#define __GPTIMER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* The GPTIMER_INFO_AVAIL define set from the BSP bsp.h configures if the - * Driver manager info interface is built. - */ - -/* Register GPTIMER and GRTIMER driver to Driver Manager */ -void gptimer_register_drv (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr1553b.h b/c/src/lib/libbsp/sparc/shared/include/gr1553b.h deleted file mode 100644 index 006417b530..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr1553b.h +++ /dev/null @@ -1,369 +0,0 @@ -/* GR1553B driver, used by BC, RT and/or BM driver - * - * COPYRIGHT (c) 2010. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * OVERVIEW - * ======== - * This driver controls the GR1553B device regardless of interfaces supported - * (BC, RT and/or BM). The device can be located at an on-chip AMBA or an - * AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM - * drivers to use. Since the different interfaces are accessed over the same - * register interface on the same core, the other drivers must share a GR1553B - * device. Any combination of interface functionality is supported, but the RT - * and BC functionality can nnot be used simultaneously due to hardware - * limitation. - * - */ - -#ifndef __GR1553B_H__ -#define __GR1553B_H__ - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* The GR1553B registers */ -struct gr1553b_regs { - /* Common Registers */ - volatile uint32_t irq; /* 0x00 IRQ register */ - volatile uint32_t imask; /* 0x04 IRQ enable mask */ - int unused0[(0x10-0x08)/4]; - volatile uint32_t hwcfg; /* 0x10 HW config register */ - - int unused1[(0x40-0x14)/4]; /* Padding */ - - /* BC Registers */ - volatile uint32_t bc_stat; /* 0x40 BC status */ - volatile uint32_t bc_ctrl; /* 0x44 BC Action register */ - volatile uint32_t bc_bd; /* 0x48 BC transfer list pointer */ - volatile uint32_t bc_abd; /* 0x4c BC async list pointer */ - volatile uint32_t bc_timer; /* 0x50 BC timer register */ - volatile uint32_t bc_wake; /* 0x54 BC wakeup control register */ - volatile uint32_t bc_irqptr; /* 0x58 BC transfer IRQ pointer */ - volatile uint32_t bc_busmsk; /* 0x5C BC per-RT bus mask register */ - - int unused2[(0x68-0x60)/4]; /* Padding */ - - volatile uint32_t bc_slot; /* 0x68 BC Current BD pointer */ - volatile uint32_t bc_aslot; /* 0x6c BC Current async BD pointer */ - - int unused3[(0x80-0x70)/4]; /* Padding */ - - /* RT Registers */ - volatile uint32_t rt_stat; /* 0x80 RT status */ - volatile uint32_t rt_cfg; /* 0x84 RT config register */ - volatile uint32_t rt_stat2; /* 0x88 RT bus status bits */ - volatile uint32_t rt_statw; /* 0x8c RT status words */ - volatile uint32_t rt_sync; /* 0x90 RT bus synchronize */ - volatile uint32_t rt_tab; /* 0x94 RT subaddress table base */ - volatile uint32_t rt_mcctrl; /* 0x98 RT valid mode code mask */ - int unused4[(0xa4-0x9c)/4]; - volatile uint32_t rt_ttag; /* 0xa4 RT time tag register */ - int unused5; /* 0xa8 RESERVED */ - volatile uint32_t rt_evsz; /* 0xac RT event log end pointer */ - volatile uint32_t rt_evlog; /* 0xb0 RT event log position */ - volatile uint32_t rt_evirq; /* 0xb4 RT event log IRQ position */ - - int unused6[(0xc0-0xb8)/4]; /* Padding */ - - /* BM Registers */ - volatile uint32_t bm_stat; /* 0xc0 BM status */ - volatile uint32_t bm_ctrl; /* 0xc4 BM control register */ - volatile uint32_t bm_adr; /* 0xc8 BM address filter */ - volatile uint32_t bm_subadr; /* 0xcc BM subaddress filter */ - volatile uint32_t bm_mc; /* 0xd0 BM mode code filter */ - volatile uint32_t bm_start; /* 0xd4 BM log start address */ - volatile uint32_t bm_end; /* 0xd8 BM log size/alignment mask */ - volatile uint32_t bm_pos; /* 0xdc BM log position */ - volatile uint32_t bm_ttag; /* 0xe0 BM time tag register */ -}; - -#define GR1553BC_KEY 0x15520000 -#define GR1553RT_KEY 0x15530000 - -/* IRQ Definitions */ -#define GR1553BC_IRQLOG_SIZE 64 -#define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t)) - -/*** IRQ Flag Register ***/ -#define GR1553B_IRQ_BCEV_BIT 0 -#define GR1553B_IRQ_BCD_BIT 1 -#define GR1553B_IRQ_BCWK_BIT 2 -#define GR1553B_IRQ_RTEV_BIT 8 -#define GR1553B_IRQ_RTD_BIT 9 -#define GR1553B_IRQ_RTTE_BIT 10 -#define GR1553B_IRQ_BMD_BIT 16 -#define GR1553B_IRQ_BMTOF_BIT 17 - -#define GR1553B_IRQ_BCEV (1<<GR1553B_IRQ_BCEV_BIT) -#define GR1553B_IRQ_BCD (1<<GR1553B_IRQ_BCD_BIT) -#define GR1553B_IRQ_BCWK (1<<GR1553B_IRQ_BCWK_BIT) -#define GR1553B_IRQ_RTEV (1<<GR1553B_IRQ_RTEV_BIT) -#define GR1553B_IRQ_RTD (1<<GR1553B_IRQ_RTD_BIT) -#define GR1553B_IRQ_RTTE (1<<GR1553B_IRQ_RTTE_BIT) -#define GR1553B_IRQ_BMD (1<<GR1553B_IRQ_BMD_BIT) -#define GR1553B_IRQ_BMTOF (1<<GR1553B_IRQ_BMTOF_BIT) - -/*** IRQ Enable Register ***/ -#define GR1553B_IRQEN_BCEVE_BIT 0 -#define GR1553B_IRQEN_BCDE_BIT 1 -#define GR1553B_IRQEN_BCWKE_BIT 2 -#define GR1553B_IRQEN_RTEVE_BIT 8 -#define GR1553B_IRQEN_RTDE_BIT 9 -#define GR1553B_IRQEN_RTTEE_BIT 10 -#define GR1553B_IRQEN_BMDE_BIT 16 -#define GR1553B_IRQEN_BMTOE_BIT 17 - -#define GR1553B_IRQEN_BCEVE (1<<GR1553B_IRQEN_BCEVE_BIT) -#define GR1553B_IRQEN_BCDE (1<<GR1553B_IRQEN_BCDE_BIT) -#define GR1553B_IRQEN_BCWKE (1<<GR1553B_IRQEN_BCWKE_BIT) -#define GR1553B_IRQEN_RTEVE (1<<GR1553B_IRQEN_RTEVE_BIT) -#define GR1553B_IRQEN_RTDE (1<<GR1553B_IRQEN_RTDE_BIT) -#define GR1553B_IRQEN_RTTEE (1<<GR1553B_IRQEN_RTTEE_BIT) -#define GR1553B_IRQEN_BMDE (1<<GR1553B_IRQEN_BMDE_BIT) -#define GR1553B_IRQEN_BMTOE (1<<GR1553B_IRQEN_BMTOE_BIT) - -/*** BC Status Register ***/ -#define GR1553B_BC_STAT_SCST_BIT 0 -#define GR1553B_BC_STAT_SCADL_BIT 3 -#define GR1553B_BC_STAT_ASST_BIT 8 -#define GR1553B_BC_STAT_ASADL_BIT 11 -#define GR1553B_BC_STAT_BCSUP_BIT 31 - -#define GR1553B_BC_STAT_SCST (0x3<<GR1553B_BC_STAT_SCST_BIT) -#define GR1553B_BC_STAT_SCADL (0x1f<<GR1553B_BC_STAT_SCADL_BIT) -#define GR1553B_BC_STAT_ASST (0x3<<GR1553B_BC_STAT_ASST_BIT) -#define GR1553B_BC_STAT_ASADL (0x1f<<GR1553B_BC_STAT_ASADL_BIT) -#define GR1553B_BC_STAT_BCSUP (1<<GR1553B_BC_STAT_BCSUP_BIT) - -/*** BC Action Register ***/ -#define GR1553B_BC_ACT_SCSRT_BIT 0 -#define GR1553B_BC_ACT_SCSUS_BIT 1 -#define GR1553B_BC_ACT_SCSTP_BIT 2 -#define GR1553B_BC_ACT_SETT_BIT 3 -#define GR1553B_BC_ACT_CLRT_BIT 4 -#define GR1553B_BC_ACT_ASSRT_BIT 8 -#define GR1553B_BC_ACT_ASSTP_BIT 9 -#define GR1553B_BC_ACT_BCKEY_BIT 16 - -#define GR1553B_BC_ACT_SCSRT (1<<GR1553B_BC_ACT_SCSRT_BIT) -#define GR1553B_BC_ACT_SCSUS (1<<GR1553B_BC_ACT_SCSUS_BIT) -#define GR1553B_BC_ACT_SCSTP (1<<GR1553B_BC_ACT_SCSTP_BIT) -#define GR1553B_BC_ACT_SETT (1<<GR1553B_BC_ACT_SETT_BIT) -#define GR1553B_BC_ACT_CLRT (1<<GR1553B_BC_ACT_CLRT_BIT) -#define GR1553B_BC_ACT_ASSRT (1<<GR1553B_BC_ACT_ASSRT_BIT) -#define GR1553B_BC_ACT_ASSTP (1<<GR1553B_BC_ACT_ASSTP_BIT) -#define GR1553B_BC_ACT_BCKEY (0xffff<<GR1553B_BC_ACT_BCKEY_BIT) - -/*** BC Timer Register ***/ -#define GR1553B_BC_TIMER_SCTM_BIT 0 - -#define GR1553B_BC_TIMER_SCTM (0xffffff<<GR1553B_BC_TIMER_SCTM_BIT) - -/*** BC Wake-up control Register ***/ -#define GR1553B_BC_WAKE_TIME_BIT 0 -#define GR1553B_BC_WAKE_WKEN_BIT 31 - -#define GR1553B_BC_WAKE_TIME (0xffffff<<GR1553B_BC_WAKE_TIME_BIT) -#define GR1553B_BC_WAKE_WKEN (1<GR1553B_BC_WAKE_WKEN_BIT) - -/*** RT status Register ***/ -#define GR1553B_RT_STAT_RUN_BIT 0 -#define GR1553B_RT_STAT_SHDB_BIT 1 -#define GR1553B_RT_STAT_SHDA_BIT 2 -#define GR1553B_RT_STAT_ACT_BIT 3 -#define GR1553B_RT_STAT_RTSUP_BIT 31 - -#define GR1553B_RT_STAT_RUN (1<<GR1553B_RT_STAT_RUN_BIT) -#define GR1553B_RT_STAT_SHDB (1<<GR1553B_RT_STAT_SHDB_BIT) -#define GR1553B_RT_STAT_SHDA (1<<GR1553B_RT_STAT_SHDA_BIT) -#define GR1553B_RT_STAT_ACT (1<<GR1553B_RT_STAT_ACT_BIT) -#define GR1553B_RT_STAT_RTSUP (1<<GR1553B_RT_STAT_RTSUP_BIT) - - -/*** RT Config Register ***/ -#define GR1553B_RT_CFG_RTEN_BIT 0 -#define GR1553B_RT_CFG_RTADDR_BIT 1 -#define GR1553B_RT_CFG_RTKEY_BIT 16 - -#define GR1553B_RT_CFG_RTEN (1<<GR1553B_RT_CFG_RTEN_BIT) -#define GR1553B_RT_CFG_RTADDR (1<<GR1553B_RT_CFG_RTADDR_BIT) -#define GR1553B_RT_CFG_RTKEY (0xffff<<GR1553B_RT_CFG_RTKEY_BIT) - -/*** RT Bus Status Register ***/ -#define GR1553B_RT_STAT2_TFLG_BIT 0 -#define GR1553B_RT_STAT2_DBCA_BIT 1 -#define GR1553B_RT_STAT2_SSF_BIT 2 -#define GR1553B_RT_STAT2_BUSY_BIT 3 -#define GR1553B_RT_STAT2_SREQ_BIT 4 -#define GR1553B_RT_STAT2_TFDE_BIT 8 - -#define GR1553B_RT_STAT2_TFLG (1<<GR1553B_RT_STAT2_TFLG_BIT) -#define GR1553B_RT_STAT2_DBCA (1<<GR1553B_RT_STAT2_DBCA_BIT) -#define GR1553B_RT_STAT2_SSF (1<<GR1553B_RT_STAT2_SSF_BIT) -#define GR1553B_RT_STAT2_BUSY (1<<GR1553B_RT_STAT2_BUSY_BIT) -#define GR1553B_RT_STAT2_SREQ (1<<GR1553B_RT_STAT2_SREQ_BIT) -#define GR1553B_RT_STAT2_TFDE (1<<GR1553B_RT_STAT2_TFDE_BIT) - -/*** RT Status Words Register ***/ -#define GR1553B_RT_STATW_VECW_BIT 0 -#define GR1553B_RT_STATW_BITW_BIT 16 - -#define GR1553B_RT_STATW_VECW (0xffff<<GR1553B_RT_STATW_VECW_BIT) -#define GR1553B_RT_STATW_BITW (0xffff<<GR1553B_RT_STATW_BITW_BIT) - -/*** RT Sync Register ***/ -#define GR1553B_RT_SYNC_SYD_BIT 0 -#define GR1553B_RT_SYNC_SYTM_BIT 16 - -#define GR1553B_RT_SYNC_SYD (0xffff<<GR1553B_RT_SYNC_SYD_BIT) -#define GR1553B_RT_SYNC_SYTM (0xffff<<GR1553B_RT_SYNC_SYTM_BIT) - -/*** RT Sub adress table Register ***/ -#define GR1553B_RT_TAB_SATB_BIT 0 - -#define GR1553B_RT_TAB_SATB (0xffff<<GR1553B_RT_TAB_SATB_BIT) - -/*** RT Mode code control Register ***/ -#define GR1553B_RT_MCCTRL_S_BIT 0 -#define GR1553B_RT_MCCTRL_SB_BIT 2 -#define GR1553B_RT_MCCTRL_SD_BIT 4 -#define GR1553B_RT_MCCTRL_SDB_BIT 6 -#define GR1553B_RT_MCCTRL_TS_BIT 8 -#define GR1553B_RT_MCCTRL_TSB_BIT 10 -#define GR1553B_RT_MCCTRL_TVW_BIT 12 -#define GR1553B_RT_MCCTRL_TBW_BIT 14 -#define GR1553B_RT_MCCTRL_DBC_BIT 16 -#define GR1553B_RT_MCCTRL_IST_BIT 18 -#define GR1553B_RT_MCCTRL_ISTB_BIT 20 -#define GR1553B_RT_MCCTRL_ITF_BIT 22 -#define GR1553B_RT_MCCTRL_ITFB_BIT 24 -#define GR1553B_RT_MCCTRL_RRT_BIT 26 -#define GR1553B_RT_MCCTRL_RRTB_BIT 28 - -#define GR1553B_RT_MCCTRL_S (1<<GR1553B_RT_MCCTRL_S_BIT) -#define GR1553B_RT_MCCTRL_SB (1<<GR1553B_RT_MCCTRL_SB_BIT) -#define GR1553B_RT_MCCTRL_SD (1<<GR1553B_RT_MCCTRL_SD_BIT) -#define GR1553B_RT_MCCTRL_SDB (1<<GR1553B_RT_MCCTRL_SDB_BIT) -#define GR1553B_RT_MCCTRL_TS (1<<GR1553B_RT_MCCTRL_TS_BIT) -#define GR1553B_RT_MCCTRL_TSB (1<<GR1553B_RT_MCCTRL_TSB_BIT) -#define GR1553B_RT_MCCTRL_TVW (1<<GR1553B_RT_MCCTRL_TVW_BIT) -#define GR1553B_RT_MCCTRL_TBW (1<<GR1553B_RT_MCCTRL_TBW_BIT) -#define GR1553B_RT_MCCTRL_DBC (1<<GR1553B_RT_MCCTRL_DBC_BIT) -#define GR1553B_RT_MCCTRL_IST (1<<GR1553B_RT_MCCTRL_IST_BIT) -#define GR1553B_RT_MCCTRL_ISTB (1<<GR1553B_RT_MCCTRL_ISTB_BIT) -#define GR1553B_RT_MCCTRL_ITF (1<<GR1553B_RT_MCCTRL_ITF_BIT) -#define GR1553B_RT_MCCTRL_ITFB (1<<GR1553B_RT_MCCTRL_ITFB_BIT) -#define GR1553B_RT_MCCTRL_RRT (1<<GR1553B_RT_MCCTRL_RRT_BIT) -#define GR1553B_RT_MCCTRL_RRTB (1<<GR1553B_RT_MCCTRL_RRTB_BIT) - -/*** RT Time Tag control Register ***/ -#define GR1553B_RT_TTAG_TVAL_BIT 0 -#define GR1553B_RT_TTAG_TRES_BIT 16 - -#define GR1553B_RT_TTAG_TVAL (0xffff<<GR1553B_RT_TTAG_TVAL_BIT) -#define GR1553B_RT_TTAG_TRES (0xffff<<GR1553B_RT_TTAG_TRES_BIT) - -/*** BM Control Register ***/ -#define GR1553B_BM_STAT_BMSUP_BIT 31 - -#define GR1553B_BM_STAT_BMSUP (1<<GR1553B_BM_STAT_BMSUP_BIT) - -/*** BM Control Register ***/ -#define GR1553B_BM_CTRL_BMEN_BIT 0 -#define GR1553B_BM_CTRL_MANL_BIT 1 -#define GR1553B_BM_CTRL_UDWL_BIT 2 -#define GR1553B_BM_CTRL_IMCL_BIT 3 - -#define GR1553B_BM_CTRL_BMEN (1<<GR1553B_BM_CTRL_BMEN_BIT) -#define GR1553B_BM_CTRL_MANL (1<<GR1553B_BM_CTRL_MANL_BIT) -#define GR1553B_BM_CTRL_UDWL (1<<GR1553B_BM_CTRL_UDWL_BIT) -#define GR1553B_BM_CTRL_IMCL (1<<GR1553B_BM_CTRL_IMCL_BIT) - -/*** BM RT Mode code filter Register ***/ -#define GR1553B_BM_MC_S_BIT 0 -#define GR1553B_BM_MC_SB_BIT 1 -#define GR1553B_BM_MC_SD_BIT 2 -#define GR1553B_BM_MC_SDB_BIT 3 -#define GR1553B_BM_MC_TS_BIT 4 -#define GR1553B_BM_MC_TSB_BIT 5 -#define GR1553B_BM_MC_TVW_BIT 6 -#define GR1553B_BM_MC_TBW_BIT 7 -#define GR1553B_BM_MC_DBC_BIT 8 -#define GR1553B_BM_MC_IST_BIT 9 -#define GR1553B_BM_MC_ISTB_BIT 10 -#define GR1553B_BM_MC_ITF_BIT 11 -#define GR1553B_BM_MC_ITFB_BIT 12 -#define GR1553B_BM_MC_RRT_BIT 13 -#define GR1553B_BM_MC_RRTB_BIT 14 -#define GR1553B_BM_MC_TSW_BIT 15 -#define GR1553B_BM_MC_TLC_BIT 16 -#define GR1553B_BM_MC_STS_BIT 17 -#define GR1553B_BM_MC_STSB_BIT 18 - -#define GR1553B_BM_MC_S (1<<GR1553B_BM_MC_S_BIT) -#define GR1553B_BM_MC_SB (1<<GR1553B_BM_MC_SB_BIT) -#define GR1553B_BM_MC_SD (1<<GR1553B_BM_MC_SD_BIT) -#define GR1553B_BM_MC_SDB (1<<GR1553B_BM_MC_SDB_BIT) -#define GR1553B_BM_MC_TS (1<<GR1553B_BM_MC_TS_BIT) -#define GR1553B_BM_MC_TSB (1<<GR1553B_BM_MC_TSB_BIT) -#define GR1553B_BM_MC_TVW (1<<GR1553B_BM_MC_TVW_BIT) -#define GR1553B_BM_MC_TBW (1<<GR1553B_BM_MC_TBW_BIT) -#define GR1553B_BM_MC_DBC (1<<GR1553B_BM_MC_DBC_BIT) -#define GR1553B_BM_MC_IST (1<<GR1553B_BM_MC_IST_BIT) -#define GR1553B_BM_MC_ISTB (1<<GR1553B_BM_MC_ISTB_BIT) -#define GR1553B_BM_MC_ITF (1<<GR1553B_BM_MC_ITF_BIT) -#define GR1553B_BM_MC_ITFB (1<<GR1553B_BM_MC_ITFB_BIT) -#define GR1553B_BM_MC_RRT (1<<GR1553B_BM_MC_RRT_BIT) -#define GR1553B_BM_MC_RRTB (1<<GR1553B_BM_MC_RRTB_BIT) -#define GR1553B_BM_MC_TSW (1<<GR1553B_BM_MC_TSW_BIT) -#define GR1553B_BM_MC_TLC (1<<GR1553B_BM_MC_TLC_BIT) -#define GR1553B_BM_MC_STS (1<<GR1553B_BM_MC_STS_BIT) -#define GR1553B_BM_MC_STSB (1<<GR1553B_BM_MC_STSB_BIT) - -/*** BM RT Mode code filter Register ***/ -#define GR1553B_BM_TTAG_VAL_BIT 0 -#define GR1553B_BM_TTAG_RES_BIT 24 - -#define GR1553B_BM_TTAG_VAL (0xffffff<<GR1553B_BM_TTAG_VAL_BIT) -#define GR1553B_BM_TTAG_RES (0xff<<GR1553B_BM_TTAG_RES_BIT) - -/* Register GR1553B driver */ -extern void gr1553_register(void); - -/*** BC Device allocation ***/ -/* Allocate a BC device. Minor is assigned to a device in the order - * they are registered to the driver. - */ -extern struct drvmgr_dev **gr1553_bc_open(int minor); -/* Free a BC device previously allocated */ -extern void gr1553_bc_close(struct drvmgr_dev **dev); - -/*** RT Device allocation ***/ -/* Allocate a BC device. Minor is assigned to a device in the order - * they are registered to the driver. - */ -extern struct drvmgr_dev **gr1553_rt_open(int minor); -/* Free a BC device previously allocated */ -extern void gr1553_rt_close(struct drvmgr_dev **dev); - -/*** BM Device allocation ***/ -/* Allocate a BC device. Minor is assigned to a device in the order - * they are registered to the driver. - */ -extern struct drvmgr_dev **gr1553_bm_open(int minor); -/* Free a BC device previously allocated */ -extern void gr1553_bm_close(struct drvmgr_dev **dev); - -#ifdef __cplusplus -} -#endif - -#endif /* __GR1553B_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/gr1553bc.h b/c/src/lib/libbsp/sparc/shared/include/gr1553bc.h deleted file mode 100644 index ec766d2147..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr1553bc.h +++ /dev/null @@ -1,250 +0,0 @@ -/* GR1553B BC driver - * - * COPYRIGHT (c) 2010. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * OVERVIEW - * ======== - * This driver controls the BC device, located at an on-chip AMBA or an - * AMBA-over-PCI bus. The driver operates the BC device and provides you - * with interrupt services and core control. The driver start execution of - * a synchronuos and/or an asynchronous BC descriptor List. The list contains - * a descriptor table and a software description to make some operations - * possible, for example translate descriptor-address into descriptor-number. - * - * BC descriptors are generated by the list API, available in gr1553bc_list.h. - * - * See gr1553bc_list.h for more information. - */ - -#ifndef __GR1553BC_H__ -#define __GR1553BC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Forward declaration */ -struct gr1553bc_list; -struct gr1553bc_major; -struct gr1553bc_minor; -struct gr1553bc_minor_cfg; -struct gr1553bc_major_cfg; - -#ifdef __cplusplus -} -#endif - -#include <stdint.h> -#include <bsp/gr1553bc_list.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Register GR1553B driver needed by BC driver */ -extern void gr1553bc_register(void); - -/* A BC descriptor accessed as is */ -struct gr1553bc_bd_raw { - volatile uint32_t words[4]; -}; - -/* A BC descriptor accessed as a transfer descriptor */ -struct gr1553bc_bd_tr { - volatile uint32_t settings[2]; - volatile uint32_t dptr; - volatile uint32_t status; -}; - -/* A BC descriptor accessed as a conditional descriptor */ -struct gr1553bc_bd_cond { - volatile uint32_t cond; - volatile uint32_t bdptr; - volatile uint32_t padding[2]; -}; - -/* A BC descriptor accessed any way */ -union gr1553bc_bd { - struct gr1553bc_bd_raw raw; - struct gr1553bc_bd_tr tr; - struct gr1553bc_bd_cond cond; -}; - -/* Current state of the BC hardware */ -struct gr1553bc_status { - unsigned int status; - unsigned int time; -}; - -#define KEEP_TIMESLOT 0x10 -/* Initialize a BC descriptor. The words written is controllable by - * the flags argument. - * - * flags: - * bit[N=0..3]: 1 = set BD wordN according to argument wordN, - * 0 = do not modify BD wordN - * - * If bit KEEP_TIMESLOT is set the time slot of word0 is preserved, - * this bit only have an affect when the descriptor is a transfer - * descriptor. - */ -extern void gr1553bc_bd_init( - union gr1553bc_bd *bd, - unsigned int flags, - uint32_t word0, - uint32_t word1, - uint32_t word2, - uint32_t word3 - ); - -/* Initialize a Transfer descriptor - * - * Arguments: - * struct gr1553bc_bd_tr *bd - * uint32_t setting0 - * uint32_t setting1 - * uint32_t data - * uint32_t status - */ -#define gr1553bc_bd_tr_init(bd, set0, set1, data, status) \ - gr1553bc_bd_init((union gr1553bc_bd *)bd,\ - 0xf, set0, set1, data, status) -/* Initializa a Condition descriptor - * - * Arguments: - * struct gr1553bc_bd_cond *bd - * uint32_t cond - * uint32_t jump_adr - */ -#define gr1553bc_bd_cond_init(bd, cond, jump_adr) \ - gr1553bc_bd_init((union gr1553bc_bd *)bd, \ - 0xf, cond, jump_adr, 0, 0) - -/* Size of a descriptor */ -#define GR1553BC_BD_SIZE sizeof(struct gr1553bc_bd_raw) - -/* Alignment of a descriptor */ -#define GR1553BC_BD_ALIGN 16 - -/* End of list marker */ -#define GR1553BC_TR_EOL 0x80ffffff - -#define GR1553BC_BD_TYPE 0x80000000 - -/* Condition descriptor bits */ -#define GR1553BC_UNCOND_JMP 0x820000ff -#define GR1553BC_UNCOND_IRQ 0x860000ff -#define GR1553BC_UNCOND_NOJMP 0x82000000 - -/* Transfer descriptor bits */ -#define GR1553BC_TR_DUMMY_0 0x00000000 -#define GR1553BC_TR_DUMMY_1 0x80000000 - -#define GR1553BC_TR_TIME 0x0000ffff - -#define GR1553BC_TR_EXTTRIG 0x40000000 - -/* Take a GR1553BC hardware device identified by instance index (minor). - * A pointer is returned that is used internally by the GR1553BC - * driver, it is used as an input paramter 'bc' to all other - * functions that manipulate the hardware. - */ -extern void *gr1553bc_open(int minor); - -extern void gr1553bc_close(void *bc); - -/* Stores Current Major/Minor frame number and the Slot number executing - * into the location indicated by 'mid'. There may be two lists executing - * in "parallel", the 'async' argument select for which list the MID is - * looked up, the Syncronous (async=0) list or the Asynchronous (async=1) - * list. - * - */ -extern int gr1553bc_indication(void *bc, int async, int *mid); - -/* Trigger external time sync by writing to the BC action register. - * This may be good for debugging or if the time management is - * implemented in software. - * - * if trig=0 the external trigger memory is cleared. - * if trig!=0 the external trigger memory is set. - */ -extern void gr1553bc_ext_trig(void *bc, int trig); - -/* Configure the GR1553BC driver */ -/*extern int gr1553bc_config(struct gr1553bc_config *cfg);*/ - -/* Start major frame processing. At least one list pointer must be - * non-zero to affect BC operation. The BC communication is enabled - * depending on list and Interrupts are enabled. This function can - * be called multiple times. - * - * If a list is already executing it will be replaced with the new - * list. - * - * list - Schedule Transfer List - * list_async - Asynchronous list - */ -extern int gr1553bc_start - ( - void *bc, - struct gr1553bc_list *list, - struct gr1553bc_list *list_async - ); - -/* Pause GR1553B BC scheduled transfers. - * - * Does not affect asynchronous operation. - */ -extern int gr1553bc_pause(void *bc); - -/* Restart GR1553B BC scheduled transfers, after being paused - * - * Does not affect asynchronous operation. - */ -extern int gr1553bc_restart(void *bc); - -/* Stop BC transmission. - * - * OPTIONS - * bit0 - 1=STOP schedule list - * bit1 - 1=STOP asynchronous list - */ -extern int gr1553bc_stop(void *bc, int options); - -/* Standard IRQ function setup. IRQ can be generated by condition descriptors - * or by transfer descriptors or by errors. - * - * Condition descriptors are inserted into the list by user, each condition - * may have a custom function and data assigned to it, see - * gr1553bc_slot_irq_prepare(). IRQs generated by condition descriptors are - * not handled by this function. - * - * Transfer descriptors can generate IRQ if enabled by user. - * - * IRQs generated by transfer descriptors or by BC errors (DMA error etc.) - * is handled by this standard ISR handler. - */ -extern int gr1553bc_irq_setup - ( - void *bc, - bcirq_func_t func, - void *data - ); - -/* Get Current BC hardware state/status. The Status is stored into the - * area pointed to by status. See "struct gr1553bc_status" for more - * info. - */ -extern void gr1553bc_status(void *bc, struct gr1553bc_status *status); - -#ifdef __cplusplus -} -#endif - -#endif /* __GR1553BC_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/gr1553bc_list.h b/c/src/lib/libbsp/sparc/shared/include/gr1553bc_list.h deleted file mode 100644 index a89ddf58cf..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr1553bc_list.h +++ /dev/null @@ -1,707 +0,0 @@ -/* - * GR1553B BC driver, Descriptor LIST handling - * - * COPYRIGHT (c) 2010. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GR1553BC_LIST_H__ -#define __GR1553BC_LIST_H__ - -/*!\file doc/gr1553bc_list.h - * \brief GR1553B BC driver - * - * \section OVERVIEW - * - * The BC device driver can schedule synchronous and asynchronous lists - * of descriptors. The list contains a descriptor table and a software - * description to make some operations possible, for example translate - * descriptor-address into descriptor-number. - * - * This is the LIST API. It provides functionality to create and manage - * a BC descriptor list. - * - * A list is built up by the following build blocks: - * - Major Frame (Consists of N Minor Frames) - * - Minor Frame (Consists of up to 32 1553 Message Slots) - * - Message Slot (Transfer/Condition BC descriptor) - * - * The user can configure lists with different configuration of number of - * Major Frames, Minor Frame and messages slots within a Minor Frame. The - * List manages a strait descriptor table (may be changed) and a Frame/Slot - * tree in order to easily find it's way through all descriptor created. - * - * Each Minor frame consist of up to 32 message slot and 2 message slots - * for time management and descriptor find operations. The list can manage - * time slots per minor frame, for example a minor frame may be programmed - * to take 8ms and when the user allocate a message slot within that Minor - * frame the time spcified will be subtracted from the 8ms, and when the - * message slot is freed the time will be returned to the Minor frame again. - * - * A Major, Minor and Message Slots are identified using a MID (Message-ID). - * The MID is a way for the user to avoid using pointers are talk with the - * list API in an easier way. For example a condition Slot that should jump - * to a transfer slot can be created by knowing "MID and Jump-To-MID". When - * allocating a Slot (with or without time) the user may specify a certain - * Slot or a Minor frame, when a Minor frame is given then the API will find - * a free Slot as early in the Minor Frame as possible and return it to the - * user. - * - * A MID can be created using the macros: - * GR1553BC_ID(major,minor,slot) - ID of a SLOT - * GR1553BC_MINOR_ID(major,minor) - ID of a MINOR (Slot=0xff) - * GR1553BC_MAJOR_ID(major) - ID of a Major (Minor=0xff,Slot=0xff) - * - * The typical approach create lists is in the following order: - * -# gr1553bc_list_alloc(&list, MAJOR_CNT) - * -# gr1553bc_list_config(list, &listcfg) - * -# Create all Major Frames and Minor frame, for each major frame: - * a) gr1553bc_major_alloc_skel(&major, &major_minor_cfg) - * b) gr1553bc_list_set_major(list, &major, MAJOR_NUM) - * -# link end Major Frames together: - * a) gr1553bc_list_set_major(&major7, &major0) // Connect Major frames - * -# gr1553bc_list_table_alloc() (Allocate Descriptor Table) - * -# gr1553bc_list_table_build() (Build Descriptor Table from Majors/Minors) - * -# Allocate and initialize Descriptors pre defined before starting: - * -## gr1553bc_slot_alloc(list, &MID, TIME_REQUIRED, ..) - * -## gr1553bc_slot_transfer(MID, ...) - * -# START BC HARDWARE BY SHCDULING ABOVE LIST - * -# Operate on List - * - * - * \section bc_list_update Changing a scheduled BC list (during BC-runtime) - * - * One can use the INDICATION service to avoid modifying - * a descriptor currently in use by the BC core. One can also in most cases - * do descriptor initialization in three steps: Init Descriptor as Dummy - * with and allocated time (often done before starting/scheduling list), - * then modify transfer options and data-pointers, then clear the Dummy - * bit in one atomic data store. This approach will avoid potential races - * between software has hardware. - * - * - * \section bc_memory_setup Custom Memory Setup - * - * For designs where dynamically memory is not an option, or the driver - * is used on a AMBA-over-PCI bus (where malloc() does not work), the - * API allows the user to provide custom addresses for descriptor table - * and object descriptions (lists, major frames, minor frames). Custom - * descriptor table is probably the most interesting thing for most, it - * is setup with gr1553bc_list_table_alloc(list, CUSTOM_ADDRESS). - * - * Object descriptions are normally allocated during initialization - * procedure by providing the API with a object configuration, for - * example a Major Frame configuration enables the API to allocate - * the software description of a Major Frame with all it's Minor frames. - * - * - * \section major Major Frame - * - * Consists of multiple Minor frames. A Major frame may be connected/linked - * with another Major frame, this will result in a Jump Slot from last - * Minor frame in the first Major to the first Minor in the second Major. - * - * - * \section minor Minor Frame - * - * Consists of up to 32 Message Slots. The services are Time-Management and - * Slot allocation. - * - * Time-Management is optional. - * - * Time-Slot-Management can be enabled per Minor frame. A Minor frame can be - * assigned a time in microseconds. The BC will not continue to the next - * Minor frame until the time has passed. It is managed by adding an extra - * Dummy Message Slot with the total minor frame time. Each time a message - * Slot is allocated (with a certain time: Slot-Time) the Slot-Time will - * be decremented from the total time of the Minor frame. This way the - * sum of the Message Slot will always sum up to the total time of the - * Minor configuration. When a message slot is freed, the Dymmy Message - * Slot's Slot-Time is incremented with the freed Slot-Time. - * - * A Message Slot can be allocated by identifying a specific free Slot - * by the MID (Message-ID) or by letting the API allocate the first free - * Slot in the Minor Frame (Set MID Slot-ID to 0xff to identify Minor - * Frame). - * - * - * \section slot Message Slot - * - * The GR1553B BC core supports two Slot (Descriptor) Types: - * - Transfer descriptor - * - Condition descriptor (Jump, unconditional-IRQ) - * - * See the hardware manual for a detail description of a descriptor (Slot). - * - * The BC Core is unaware of lists, it steps through executing each - * descriptor as the encountered, Conditionals resulting in jumps may - * let us to create more complex arrangements of buffer descriptos (BDs) - * which we call list. - * - * Transfer BDs (TBDs) may have a time slot assigned, the BC core will wait - * until the time has expired before executing the next descriptor. Time - * slots are handled by a Minor frame in the list. - * - * A Message Slot is allocated using the gr1553bc_slot_alloc() function, - * and configured by calling one of the below functions: - * - gr1553bc_slot_irq_prepare [unconditional IRQ slot] - * - gr1553bc_slot_jump [unconditional jump] - * - gr1553bc_slot_exttrig [Dummy transfer, wait for EXTERNAL-TRIGGER] - * - gr1553bc_slot_transfer [Transfer descriptor] - * - gr1553bc_slot_empty [Create Dummy Transfer descriptor] - * - gr1553bc_slot_raw [Custom Descriptor handling] - * - * - gr1553bc_slot_dummy [Set existing Transfer descriptor to Dummy] - * - gr1553bc_slot_update [Update DataPointer|Status of a TBD] - * - * - * \section bc_IRQ Interrupt Handling - * - * There are different types of interrupts, Error IRQs or transfer IRQs. The - * Error IRQs are handled by the driver can a callback function is called. - * - * Transfer Descriptors can be programmed to generate interrupt, and - * condition descriptors can be programmed to generate interrupt - * unconditionaly (there exists more conditional types). When a Transfer - * descriptor causes IRQ the general ISR callback of the BC driver is - * called to let the user handle the interrupt. When a condition descriptor - * causes an IRQ a custom IRQ handler is called (if assigned). - * - * Transfers descriptor IRQ is enabled by configuring the descriptor. - * - * The API provides functions for placing unconditional IRQ points anywhere - * in the list. The order: - * -# gr1553bc_slot_alloc(&MID, TIME=0, ..) - * -# gr1553bc_slot_irq_prepare(MID, funcISR, data) - * -# gr1553bc_slot_irq_enable(MID) - * - * \verbatim - * void funcISR(*bd, *data) - * { - * // HANDLE ONE OR MULTIPLE DESCRIPTORS (MULTIPLE IN THIS EXAMPLE): - * int MID; - * gr1553bc_mid_from_bd(bd,&MID,NULL); - * printf("IRQ ON %06x\n", MID); - * } - * \endverbatim - * - * \ingroup GR1553BC - */ - -#include <stdint.h> -#include <bsp/gr1553bc.h> - -/**** CONFIGURATION OPTIONS ****/ - -/* Define GR1553BC_TIMESLOT to make driver take care of time - * management of minor frames. - */ -#define GR1553BC_TIMESLOT - -#define GR1553BC_MINOR_MAX 256 -#define GR1553BC_SLOT_MAX 32 - -#ifdef __cplusplus -extern "C" { -#endif - -struct gr1553bc_list; -struct gr1553bc_major; -struct gr1553bc_minor; -struct gr1553bc_minor_cfg; -struct gr1553bc_major_cfg; - -struct gr1553bc_minor_cfg { - int slot_cnt; - int timeslot; /* Total time of minor frame in us */ -}; - -struct gr1553bc_major_cfg { - int minor_cnt; /* Number of Minor Frames */ - struct gr1553bc_minor_cfg minor_cfgs[1]; -}; - -struct gr1553bc_list_cfg { - unsigned char rt_timeout[31]; /* Number of us timeout tolerance per RT */ - unsigned char bc_timeout; /* Number of us timeout tolerance of - * broadcast transfers */ - int tropt_irq_on_err; /* Generate IRQ on transfer error */ - int tropt_pause_on_err; /* Pause list on transfer error */ - int async_list; /* Set to non-zero if asyncronous list*/ -}; - -/* Default Configuration */ -extern struct gr1553bc_list_cfg gr1553bc_def_cfg; - -/* Complete list of all major frames */ -struct gr1553bc_list { - void *_table_custom; /* Config option given by user */ - void *_table; /* address of allocated bd-table */ - unsigned int table_hw; /* Descriptor table base HW-ADR */ - unsigned int table_cpu; /* Descriptor table base CPU-ADR */ - int table_size; /* Descriptor Table Size */ - void *bc; /* BC HW, needed for adr translation */ - unsigned char rt_timeout[32]; /* Tolerance per RT, default 20us - * Note: 31 is for Broadcast */ - uint32_t tropts; /* Transfer descriptor options: - * On transfer error the following bits - * do affect: - * - bit28 1=Generate IRQ - * - bit26 1=Pause transfer list - * - */ - int async_list; /* async list or not */ - int major_cnt; /* Number of Major frames */ - struct gr1553bc_major *majors[1]; /* Var-Array of Major Pointers*/ -}; - -/* Alloc a List with a maximum number of Major frames supported */ -extern int gr1553bc_list_alloc(struct gr1553bc_list **list, int max_major); - -/* Free List if allocated with gr1553bc_list_alloc() */ -extern void gr1553bc_list_free(struct gr1553bc_list *list); - -/* Configure Global List parameters - * - * \param list List to be configured and initialized. - * \param cfg List Configuration - * \param bc The BC hardware device description - * (only needed for address translation) - */ -extern int gr1553bc_list_config - ( - struct gr1553bc_list *list, - struct gr1553bc_list_cfg *cfg, - void *bc - ); - -/* Link a 'major' Major frame with next major frame - * The links affected: - * - major->next - * - major->minor[LAST]->next - */ -extern void gr1553bc_list_link_major( - struct gr1553bc_major *major, - struct gr1553bc_major *next - ); - -/* Link in a Major frame into a BC list. - * Calls gr1553bc_list_link_major() to link major frame with major-1 and - * major+1. If ending or starting major frame the frame is wrapped around. - */ -extern int gr1553bc_list_set_major( - struct gr1553bc_list *list, - struct gr1553bc_major *major, - int no); - -/* Calculate the size required in the descriptor table by one minor frame. */ -extern int gr1553bc_minor_table_size(struct gr1553bc_minor *minor); - -/* Calculate the size required for the descriptor table. - */ -extern int gr1553bc_list_table_size(struct gr1553bc_list *list); - -/* Allocate an empty descriptor table from list description suitable for - * the BC given by 'bc'. - * - * \param bdtab_custom Custom Descriptor Allocation options: - * ZERO: Dynamically allocated by Driver (CPU near RAM) - * Non-Zero: Use provided address as BASE of BD-TABLE - * Non-Zero with LSB set: Same as Non-Zero but address - * is given as HW address (used with AMBA-over-PCI to - * to specify RAM location on PCI board). - */ -extern int gr1553bc_list_table_alloc - ( - struct gr1553bc_list *list, - void *bdtab_custom - ); - -/* Free descriptor table allocated with gr1553bc_list_table_alloc() */ -extern void gr1553bc_list_table_free(struct gr1553bc_list *list); - -/* Build an empty descriptor table from list description, - * the minor frames will be linked together. - */ -extern int gr1553bc_list_table_build(struct gr1553bc_list *list); - -/* Major Frame */ -struct gr1553bc_major { - struct gr1553bc_major *next; /* Next Major Frame */ - struct gr1553bc_major_cfg *cfg; /* User Config of Major frame */ - struct gr1553bc_minor *minors[1]; /* Minor frames */ -}; - -/* Minor Frame */ -struct gr1553bc_minor { - struct gr1553bc_minor *next; /* Next Minor Frame */ - struct gr1553bc_minor_cfg *cfg; /* User Config of Minor frame */ - uint32_t alloc; /* Descripts allocated */ - - /* Note: THIS POINTER MUST BE ALIGNED ON A 128-bit BOUNDARY */ - union gr1553bc_bd *bds; /* Descriptors for this minor frame (CPU ADRS)*/ -}; - -/* Alloc a Major/Minor frame skeleton according to the configuration structure. - * The descriptor table is not allocated. - */ -extern int gr1553bc_major_alloc_skel - ( - struct gr1553bc_major **major, - struct gr1553bc_major_cfg *cfg - ); - -/* Unique Message/Descriptor ID. Can be used to identify a Major or Minor - * Frame, or a Slot. - * - * - If minor_num is 0xff, the ID identifies a Major Frame - * - If slot_num is 0xff, the ID identifies a Minor Frame - * - If non of the above is true, the ID identifies a specific Slot - */ -#define GR1553BC_ID(major_num, minor_num, slot_num) \ - ((((major_num)<<16)&0xff0000) | (((minor_num)<<8)&0xff00) | \ - ((slot_num) & 0xff)) -#define GR1553BC_MINOR_ID(major_num, minor_num) \ - GR1553BC_ID(major_num, minor_num, 0xff) -#define GR1553BC_MAJOR_ID(major_num) \ - GR1553BC_ID(major_num, 0xff, 0xff) - -#define GR1553BC_MAJID_FROM_ID(mid) (((mid) >> 16) & 0xff) -#define GR1553BC_MINID_FROM_ID(mid) (((mid) >> 8) & 0xff) -#define GR1553BC_SLOTID_FROM_ID(mid) ((mid) & 0xff) -#define GR1553BC_ID_SET_SLOT(mid, slot_num) (((mid) & ~0xff) | ((slot_num) & 0xff)) - -extern struct gr1553bc_major *gr1553bc_major_from_id - ( - struct gr1553bc_list *list, - int mid - ); - -extern struct gr1553bc_minor *gr1553bc_minor_from_id - ( - struct gr1553bc_list *list, - int mid - ); - -/* Get free time left of minor frame identified by MID 'mid' */ -extern int gr1553bc_list_freetime(struct gr1553bc_list *list, int mid); - -/* Get free time left of minor frame */ -extern int gr1553bc_minor_freetime(struct gr1553bc_minor *minor); - -/* Allocate a time slot on a minor frame, major/minor frame is identified - * by MID. The 'mid' is a input/ouput parameter, the resulting slot taken - * will be placed in 'mid', a pointer to the allocated descriptor is stored - * into bd. - * - * Major/Minor must be specified by MID, if slot is specified that slot will - * be allocated, if slot is 0xff, then the first free slot is allocated. - * - * The function fails (return negative) if timeslot is longer than remaining - * time in minor frame, if no more slots are available in minor frame, if - * MID points to a bad major/minor or major/minor/slot. - */ -extern int gr1553bc_slot_alloc( - struct gr1553bc_list *list, - int *mid, - int timeslot, - union gr1553bc_bd **bd - ); -/* Same as gr1553bc_slot_alloc but identifies a minor instead of list. - * The major/minor part of MID is ignored. - */ -extern int gr1553bc_slot_alloc2( - struct gr1553bc_minor *minor, - int *mid, - int timeslot, - union gr1553bc_bd **bd - ); - -/* Free message slot and the time associated with it. The time taken by the - * message slot is added to the END TIME descriptor, if managed by the driver - * for this minor frame. The descriptor will be - */ -extern int gr1553bc_slot_free(struct gr1553bc_list *list, int mid); -extern int gr1553bc_slot_free2(struct gr1553bc_minor *minor, int mid); - -/* Find MID from Descriptor pointer - * - * In the end of each minor frame is a unconditional jump - * to next minor frame descriptor. The hardware does not - * use the last 8 bytes of conditional descriptors, in the - * padding area a MID is stored so that we can lookup the - * MID of a descriptor. This function finds the jump - * descriptor and subtracs the offset from it. - * - * A faster way of looking up can be implemented if the - * list is symertical, however in the current setup we - * allow different numbers of slots in minor frames, and - * different number of minor frames in a major frame. - * - * \param bd IN: Descriptor to lookup MID of (CPU address of BD) - * \param mid OUT: Pointer to where Message-ID (Slot-ID) will be stored - * \param async OUT: Function will store non-zero value if BD belogs to - * async list. - */ -extern int gr1553bc_mid_from_bd( - union gr1553bc_bd *bd, - int *mid, - int *async - ); - -/********** TRANSFER DESCRIPTOR MANIPULATION **********/ - -/* Get pointer to descriptor entry from MID. */ -extern union gr1553bc_bd *gr1553bc_slot_bd - ( - struct gr1553bc_list *list, - int mid - ); - -/* IRQ function */ -typedef void (*bcirq_func_t)(union gr1553bc_bd *bd, void *data); - -/* Create unconditional IRQ customly defined location. - * The IRQ is disabled, enable it with gr1553bc_slot_irq_enable(). - */ -extern int gr1553bc_slot_irq_prepare - ( - struct gr1553bc_list *list, - int mid, - bcirq_func_t func, - void *data - ); - -/* Enable previously prepared unconditional IRQ */ -extern int gr1553bc_slot_irq_enable(struct gr1553bc_list *list, int mid); - -/* Disable unconditional IRQ point, changed to unconditional JUMP - * to descriptor following. - * After disabling it it can be enabled again, or freed. - */ -extern int gr1553bc_slot_irq_disable(struct gr1553bc_list *list, int mid); - -/* Create custom jump to descriptor, conditional or unconditional, see - * hardware manual for conditions. - * - * set conditional to GR1553BC_UNCOND_JMP for unconditional jump. - */ -extern int gr1553bc_slot_jump - ( - struct gr1553bc_list *list, - int mid, - uint32_t condition, - int to_mid - ); - -/* Create a dummy transfer, paused until external trigger is set. The - * Slot is will have the dummy bit set, no transfer will take place. - */ -extern int gr1553bc_slot_exttrig(struct gr1553bc_list *list, int mid); - -/* Create a transfer on a previous allocated descriptor. It is assumed - * that the descriptor has been initialized empty before calling this - * function, this is to avoid races. - * - * The settings that are controlled on a global level (and not - * by this function): - * - IRQ after transfer error - * - IRQ after transfer (not supported, insert separate IRQ slot after this) - * - Pause schedule after transfer error - * - Pause schedule after transfer (not supported) - * - slot time optional (set when MID allocated), otherwise 0 - * - (OPTIONAL) Dummy Bit, set using slot_empty() or ..._TT_DUMMY - * - RT timeout tolerance (managed per RT) - * - * Input Parameters: - * - Retry Mode (options) - * - Number of retires (options) - * - Bus selection (A or B) (options) - * - dummy bit (options) - * - transfer type (tt) - * - rt src/dst address (tt) - * - RT subaddress (tt) - * - word count (tt) - * - mode code (tt) - * - data pointer (dptr) - * - * - * See macros defined in this header file for creating transfer types (tt) - * and word count etc. - * - * See macros defined in this header file for creating the mask of options. - * - * Note that if bit0 (LSB) of dptr is set, then the address is translated into - * hardware address, otherwise the dptr is assumed to be accessible from the - * 1553 core. This is an option only for AMBA-over-PCI. - */ -extern int gr1553bc_slot_transfer( - struct gr1553bc_list *list, - int mid, - int options, - int tt, - uint16_t *dptr); - -/* Remove or set dummy bit of a transfer descriptor - * Bit31 of *dummy is written to the dummy bit, the - * old descriptor value is stored into *dummy. - */ -extern int gr1553bc_slot_dummy( - struct gr1553bc_list *list, - int mid, - unsigned int *dummy); - -/* Make a slot empty (BC will not generate bus transfers), time slot - * allocated is untouched (if assigned). - */ -extern int gr1553bc_slot_empty(struct gr1553bc_list *list, int mid); - -/* Transfer descriptor status and/or update Transfer descriptor data pointer. - * - * Read and/or write Status of a slot. Writing the status word may be - * used by software to indicate that result has been handled, or bit 31 - * may be written 1 telling software that when it reaches 0, then BC - * has executed the request. - * - * Operation: - * bd->status = *stat & (bd->status 0xffffff) | (*stat & 0x80000000); - * *stat = Value of bd->status before rewrite. - * - * Note that the status word is not written when *stat is zero. - * - * Note that if bit0 (LSB) of dptr is set, then the address is translated into - * hardware address, otherwise the dptr is assumed to be accessible from the - * 1553 core. This is an option only for AMBA-over-PCI. - */ -extern int gr1553bc_slot_update( - struct gr1553bc_list *list, - int mid, - uint16_t *dptr, - unsigned int *stat); - -/* Modify a transfer descriptor in any way, - * - * flags: - * bit[N=0..3]: 1 = set BD wordN according to argument wordN, - * 0 = do not modify BD wordN - */ -extern int gr1553bc_slot_raw - ( - struct gr1553bc_list *list, - int mid, - unsigned int flags, - uint32_t word0, - uint32_t word1, - uint32_t word2, - uint32_t word3 - ); - - -/***** Macros to create BC Transfer Types (tt) for gr1553bc_slot_transfer() *****/ - -/* WRITE TO RT (BC-to-RT) */ -#define GR1553BC_BC2RT(rtadr, subadr, word_count) \ - ((rtadr<<11) | (subadr<<5) | (0x1f<<21) | (0<<10) | \ - ((word_count>=32) ? 0 : word_count)) - -/* READ FROM RT (RT-to-BC) */ -#define GR1553BC_RT2BC(rtadr, subadr, word_count) \ - ((rtadr<<11) | (subadr<<5) | (0x1f<<21) | (1<<10) | \ - ((word_count>=32) ? 0 : word_count)) - -/* RT(TX) WRITE TO RT(RX) (RT-to-RT) */ -#define GR1553BC_RT2RT(tx_rtadr, tx_subadr, rx_rtadr, rx_subadr, word_count) \ - ((rx_rtadr<<11) | (rx_subadr<<5) | \ - (tx_rtadr<<21) | (tx_subadr<<16) | \ - (0<<10) | \ - ((word_count>=32) ? 0 : word_count)) - -/* Mode command without data. (BC-to-RT) - * Mode code: 0,1,2,3,4,5,6,7 or 8. - */ -#define GR1553BC_MC_NODATA(rtadr, modecode) \ - ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ - (modecode<<0) | (1<<10)) - -/* Mode command with 4 byte data (RT-to-BC) - * Mode code: 16, 18 or 19. - */ -#define GR1553BC_MC_RT2BC(rtadr, modecode) \ - ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ - (modecode<<0) | (1<<10)) - -/* Mode command with 4 byte data (BC-to-RT) - * Mode code: 17, 20 or 21. - */ -#define GR1553BC_MC_BC2RT(rtadr, modecode) \ - ((rtadr<<11) | (0x1f<<5) | (0x1f<<21) | \ - (modecode<<0) | (0<<10)) - -/* Broadcast to all RTs, to a specific subaddress (BC-to-RTs) */ -#define GR1553BC_BC_BC2RT(subadr, word_count) \ - ((0x1f<<11) | (subadr<<5) | (0x1f<<21) | \ - (0<<10) | \ - ((word_count>=32) ? 0 : word_count)) - -/* Request RT to broadcast to all RTs, to a specific subaddress (RT-to-RTs) */ -#define GR1553BC_BC_RT2RT(tx_rtadr, tx_subadr, rx_subadr, word_count) \ - ((0x1f<<11) | (rx_subadr<<5) | \ - (tx_rtadr<<21) | (tx_subadr<<16) | \ - (0<<10) | \ - ((word_count>=32) ? 0 : word_count)) - -/* Broadcast mode command without data (BC-to-RTs) - * Mode code: 1,3,4,5,6,7 or 8 - */ -#define GR1553BC_BC_MC_NODATA(modecode) \ - ((0x1f<<11) | (0x1f<<5) | (0x1f<<21) | \ - ((modecode)<<0) | (1<<10)) - -/* Broadcast mode command with 4 byte data (BC-to-RTs) - * Mode code: 17, 20 or 21 - */ -#define GR1553BC_BC_MC_BC2RT(modecode) \ - ((0x1f<<11) | (0x1f<<5) | (0x1f<<21) | \ - ((modecode)<<0) | (0<<10)) - - -/***** Macros to create BC options (options) for gr1553bc_slot_transfer() *****/ - -/* Dummy (BC does no bus trasactions) */ -#define GR1553BC_OPT_DUMMY (1<<1) - -/* Retry modes */ -#define GR1553BC_RETRY_SAME 0x0 /* Retry on the same bus only */ -#define GR1553BC_RETRY_ALTER 0x1 /* Retry alternating on both busses */ -#define GR1553BC_RETRY_ATTEMPT 0x2 /* Many attepts first on original - * bus then on other bus */ -/* Number of retires supported */ -#define GR1553BC_RETRY_CNT_MAX 6 - -/* Dummy bit: No transfer - * Bus bit: 0=A, 1=B - * Exttrig bit: Wait for external trigger (used for timesync) - * Exclusive bit: 1=Don't allow other messages in this time slot. - */ -#define GR1553BC_OPTIONS(dummy, exttrig, exclusive, retrymode, nretry, bus) \ - ((((exttrig) & 0x1) << 30) | (((exclusive) & 0x1) << 29) | \ - ((retrymode) << 23) | ((nretry) << 20) | \ - ((bus) & 1) | (((dummy) & 0x1) << 1)) - -#define GR1553BC_OPTIONS_BUSA GR1553BC_OPTIONS(0,0,0,GR1553BC_RETRY_SAME,0,0) -#define GR1553BC_OPTIONS_BUSB GR1553BC_OPTIONS(0,0,0,GR1553BC_RETRY_SAME,0,1) -#define GR1553BC_OPTIONS_BUSA_DUM GR1553BC_OPTIONS(1,0,0,GR1553BC_RETRY_SAME,0,0) -#define GR1553BC_OPTIONS_BUSB_DUM GR1553BC_OPTIONS(1,0,0,GR1553BC_RETRY_SAME,0,1) - -/* Show parts of a list - this is for debugging only */ -extern void gr1553bc_show_list(struct gr1553bc_list *list, int options); - -#ifdef __cplusplus -} -#endif - -#endif /* __GR1553BC_LIST_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/gr1553bm.h b/c/src/lib/libbsp/sparc/shared/include/gr1553bm.h deleted file mode 100644 index 058bc59a45..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr1553bm.h +++ /dev/null @@ -1,204 +0,0 @@ -/* GR1553B BM driver - * - * COPYRIGHT (c) 2010. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GR1553BM_H__ -#define __GR1553BM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Register GR1553B driver needed by BM driver */ -extern void gr1553bm_register(void); - -struct gr1553bm_entry { - uint32_t time; /* bit31=1, bit 30=0 */ - uint32_t data; /* bit31=0, bit 30=0 */ -}; - -#define GR1553BM_ERROPTS_MANL 0x02 -#define GR1553BM_ERROPTS_UDWL 0x04 -#define GR1553BM_ERROPTS_IMCL 0x08 -#define GR1553BM_ERROPTS_ALL 0x0e - -/* Function used to implement a custom copy routine. - * Returns number of bytes the desctionation address - * should be incremented with. - * - * \param dst Optional Destination address - * \param src Source DMA address - * \param nentires Number of entries to be processed. - * \param data Custom Data (set by config) - */ -typedef int (*bmcopy_func_t)( - unsigned int dst, - struct gr1553bm_entry *src, - int nentries, - void *data - ); - -/* IRQ function callback, called on BM DMA error */ -typedef void (*bmisr_func_t)(void *bm, void *data); - -/* BM driver configuration */ -struct gr1553bm_config { - - /*** Time options ***/ - - /* 8-bit time resolution, the BM will update the time according - * to this setting. 0 will make the time tag be of highest - * resolution (no division), 1 will make the BM increment the - * time tag once for two time ticks (div with 2), etc. - */ - uint8_t time_resolution; - - /* Enable Time Overflow IRQ handling. Setting this to 1 - * makes the driver to update the 64-bit time by it self, - * it will use time overflow IRQ to detect when the 64-bit - * time counter must be incremented. - * - * If set to zero, the driver expect the user to call - * gr1553bm_time() regularly, it must be called more often - * than the time overflows to avoid an incorrect time. - */ - int time_ovf_irq; - - - - /*** Filtering options ***/ - - /* Bus error log options - * - * bit0,4-31 = reserved, set to zero - * Bit1 = Enables logging of Invalid mode code errors - * Bit2 = Enables logging of Unexpected Data errors - * Bit3 = Enables logging of Manchester/parity errors - */ - unsigned int filt_error_options; - - /* RT Address filtering bit mask. Each bit enables (if set) - * logging of a certain RT sub address. Bit 31 enables logging - * of broadcast messages. - */ - unsigned int filt_rtadr; - - /* RT Subaddress filtering bit mask, bit definition: - * 31: Enables logging of mode commands on subadr 31 - * 1..30: BitN enables/disables logging of RT subadr N - * 0: Enables logging of mode commands on subadr 0 - */ - unsigned int filt_subadr; - - /* Mode code Filter, is written into "BM RT Mode code filter" - * register, please see hardware manual for bit declarations. - */ - unsigned int filt_mc; - - - - /*** Buffer options ***/ - - /* Size of buffer in bytes, must be aligned to 8-byte - * The size is limited to max 4Mb. - */ - unsigned int buffer_size; - - /* Custom buffer, must be aligned to 8-byte and be of buffer_size - * length. If NULL dynamic memory allocation is used. - */ - void *buffer_custom; - - /* Custom Copy function, may be used to implement a more - * effective way of copying the DMA buffer. For example - * the DMA log may need to be compressed before copied - * onto a storage, this function can be used to avoid an - * extra copy. - */ - bmcopy_func_t copy_func; - - /* Optional Custom Data passed on to copy_func() */ - void *copy_func_arg; - - - - /*** Interrupt options ***/ - - /* Custom DMA error function, note that this function is called - * from Interrupt Context. Set to NULL to disable this callback. - */ - bmisr_func_t dma_error_isr; - - /* Optional Custom Data passed on to dma_error_isr() */ - void *dma_error_arg; -}; - -/* Open BM device by instance number (minor) - * - * The return value is used as input parameter in all other function calls - * in the A - */ -extern void *gr1553bm_open(int minor); - -/* Close previously opened Bm device */ -extern void gr1553bm_close(void *bm); - -/* Configure the BM driver before starting */ -extern int gr1553bm_config(void *bm, struct gr1553bm_config *cfg); - -/* Start logging */ -extern int gr1553bm_start(void *bm); - -/* Get 64-bit 1553 Time. Low 24-bit time is acquired from BM hardware, - * the MSB is taken from a software counter internal to the driver. The - * counter is incremented every time the Time overflows by: - * - using "Time overflow" IRQ if enabled in user configuration - * - by checking IRQ flag (IRQ disabled), it is required that user - * calls this function before the next time overflow. - * - * The BM timer is limited to 24-bits, in order to handle overflows - * correctly and maintain a valid time an Interrupt handler is used - * or this function must be called when IRQ is not used. - * - * Update software time counters and return the current time. - */ -extern void gr1553bm_time(void *bm, uint64_t *time); - -/* Return zero when logging has not been started, non-zero when logging - * has been started - */ -extern int gr1553bm_started(void *bm); - -/* Check how many entries are currently stored in the BM Log DMA-area */ -extern int gr1553bm_available(void *bm, int *nentries); - -/* Stop logging */ -extern void gr1553bm_stop(void *bm); - -/* Read a maximum number of entries from LOG buffer. This function - * must be - * - * Arguments - * bm - Private pointer returned by gr1553bm_open() - * dst - Address where log data is written - * max - (IN/OUT) Maximum number of entires, when successfull - * the number of entries actually written is stored - * into the address of max. - * - * Result - * 0 = success - * -1 = fail. (may be due to BM logging not started) - */ -extern int gr1553bm_read(void *bm, struct gr1553bm_entry *dst, int *max); - -#ifdef __cplusplus -} -#endif - -#endif /* __GR1553BM_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/gr1553rt.h b/c/src/lib/libbsp/sparc/shared/include/gr1553rt.h deleted file mode 100644 index 55237b5dfd..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr1553rt.h +++ /dev/null @@ -1,434 +0,0 @@ -/* GR1553B RT driver - * - * COPYRIGHT (c) 2010. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GR1553RT_H__ -#define __GR1553RT_H__ - -/* CONFIG OPTION: Maximum number of LIST IDs supported. - * There are two lists per RT subaddress, one for RX one - * for TX. - */ -#define RTLISTID_MAX 64 - -/* CONFIG OPTION: Maximum number of Interrupt handlers per device supported - * max is 256 supported, and minimum is 1. - */ -#define RTISR_MAX 64 - -/* CONFIG OPTION: Maximum number of transfer (RX/TX) descriptors supported. - * - * Set this option to zero to allow flexible number of descriptors, - * requires dynamically allocation of driver structures. - */ -/*#define RTBD_MAX 4096*/ -#define RTBD_MAX 0 - -#ifdef __cplusplus -extern "C" { -#endif - -/* Register GR1553B driver needed by RT driver */ -extern void gr1553rt_register(void); - -struct gr1553rt_list; - -/* Descriptor read/written by hardware. - * - * Must be aligned to 16 byte boundary - */ -struct gr1553rt_bd { - volatile unsigned int ctrl; /* 0x00 Control/Status word */ - volatile unsigned int dptr; /* 0x04 Data Pointer */ - volatile unsigned int next; /* 0x08 Next Descriptor in list */ - volatile unsigned int unused; /* 0x0C UNUSED BY HARDWARE */ -}; - -/* Sub address table entry, the hardware access */ -struct gr1553rt_sa { - volatile unsigned int ctrl; /* 0x00 SUBADDRESS CONTROL WORD */ - volatile unsigned int txptr; /* 0x04 TRANSMIT BD POINTER */ - volatile unsigned int rxptr; /* 0x08 RECEIVE BD POINTER */ - volatile unsigned int unused; /* 0x0C UNUSED BY HARDWARE */ -}; - -/* Configuration of a RT-SubAddress-List */ -struct gr1553rt_list_cfg { - unsigned int bd_cnt; /* Number of hw-descriptors in list */ -}; - -/* A TX or RX subaddress descriptor list */ -struct gr1553rt_list { - short listid; /* ID/NUMBER of List. -1 unassigned */ - short subadr; /* SubAddress. -1 when not scheduled */ - void *rt; /* Scheduled on Device */ - struct gr1553rt_list_cfg *cfg; /* List configuration */ - int bd_cnt; /* Number of Descriptors */ - - /* !!Must be last in data structure!! - * !!Array must at least be of length bd_cnt!! - */ - unsigned short bds[1]; /* Array of BDIDs, -1 unused/end */ -}; - -/* GR1553B-RT Driver configuration options used when calling gr1553rt_config(). - * - * Note that if not custom addresses are given the driver will dynamically - * allocate memory for buffers. - * Note that if custom addresses with the LSB set, the address will be - * interpreted as a address accessible by hardware, and translated - * into an address used by CPU. - */ -struct gr1553rt_cfg { - unsigned char rtaddress; /* RT Address 0..30 */ - - /*** MODE CODE CONFIG ***/ - unsigned int modecode; /* Mode codes enable/disable/IRQ/EV-Log. - * Each modecode has a 2-bit cfg field. - * See Mode Code Control Register in - * hardware manual. - */ - - /*** TIME CONFIG ***/ - unsigned short time_res; /* Time tag resolution in us */ - - /*** SUBADDRESS TABLE CONFIG ***/ - void *satab_buffer; /* Optional Custom buffer. Must be - * At least 16*32 bytes, and be aligned - * to 10-bit (1KB) boundary. Set to NULL - * to make driver allocate buffer. - */ - - /*** EVENT LOG CONFIG ***/ - void *evlog_buffer; /* Optional Custom buffer */ - int evlog_size; /* Length, must be a multiple of 2. - * If set to ZERO event log is disabled - */ - - /*** TRANSFER DESCRIPTOR CONFIG ***/ - int bd_count; /* Number of transfer descriptors shared - * by all RX/TX sub-addresses */ - void *bd_buffer; /* Optional Custom descriptor area. - * Must hold bd_count*32 bytes. - * If NULL, descriptors will be - * allocated dynamically. */ -}; - -/* GR1553B-RT status indication, copied from the RT registers and stored - * here. Used when calling the gr1553rt_status() function. - */ -struct gr1553rt_status { - unsigned int status; /* RT Status word */ - unsigned int bus_status; /* BUS Status */ - unsigned short synctime; /* Time Tag of last sync with data */ - unsigned short syncword; /* Data of last mode code synchronize - * with data. */ - unsigned short time_res; /* Time resolution (set by config) */ - unsigned short time; /* Current Time Tag */ -}; - -/* ISR callback definition for ERRORs detected in the GR1553B-RT interrupt - * handler. - * - * \param err Inidicate Error type. The IRQ flag register bit mask: - * Bit 9 - RT DMA ERROR - * Bit 10 - RT Table access error - * \param data Custom data assigned by user - */ -typedef void (*gr1553rt_irqerr_t)(int err, void *data); - -/* ISR callback definition for modecodes that are configured to generate - * an IRQ. The callback is called from within the GR1553B-RT interrupt - * handler. - * - * \param mcode Mode code that caused this IRQ - * \param entry The raw Eventlog Entry - * \param data Custom data assigned by user - */ -typedef void (*gr1553rt_irqmc_t)(int mcode, unsigned int entry, void *data); - -/* Transfer ISR callback definition. Called from GR1553B-RT interrupt handler - * when an interrupt has been generated and a event logged due to a 1553 - * transfer to this RT. - * - * \param list List (Subaddress/TransferType) that caused IRQ - * \param entry The raw Eventlog Entry - * \param bd_next Next Descriptor-entry index in the list (Subaddress/tr-type) - * This can be used to process all descriptors upto entry_next. - * \param data Custom data assigned by user - */ -typedef void (*gr1553rt_irq_t)( - struct gr1553rt_list *list, - unsigned int entry, - int bd_next, - void *data - ); - -/* Configure a list according to configuration. Assign the list - * to a device, however not to a RT sub address yet. The rt - * is stored within list. - * - * \param rt RT Device driver identification, stored within list. - * \param list The list to configure - * \param cfg Configuration for list. Pointer to configuration is - * stored within list for later use. - */ -extern int gr1553rt_list_init - ( - void *rt, - struct gr1553rt_list **plist, - struct gr1553rt_list_cfg *cfg - ); - -/* Assign an Error Interrupt handler. Before the handler is called the - * RT hardware is stopped/disabled. The handler is optional, if not assigned - * the ISR will still stop the RT upon error. - * - * Errors detected by the interrupt handler: - * - DMA error - * - Subaddress table access error - * - * \param func ISR called when an error causes an interrupt. - * \param data Custom data given as an argument when calling ISR - */ -extern int gr1553rt_irq_err - ( - void *rt, - gr1553rt_irqerr_t func, - void *data - ); - -/* Assign a ModeCode Interrupt handler callback. Called when a 1553 modecode - * transfer is logged and cause an IRQ. The modecode IRQ generation is - * configured from "struct gr1553rt_cfg" when calling gr1553rt_config(). - * - * \param func ISR called when a modecode causes an interrupt. - * \param data Custom data given as an argument when calling ISR - */ -extern int gr1553rt_irq_mc - ( - void *rt, - gr1553rt_irqmc_t func, - void *data - ); - -/* Assign transfer interrupt handler callback. Called when a RX or TX - * transfer is logged and cause an interrupt, the function is called - * from the GR1553B-RT driver's ISR, in interrupt context. - * - * The callback can be installed per subaddress and transfer type. - * Subaddress 0 and 31 are not valid (gr1553rt_irq_mc() for modecodes). - * - * \param subadr Select subaddress (1-30) - * \param tx 1=TX subaddress, 0=RX subaddress - * \param func ISR called when subaddress of spcified transfer type - * causes an interrupt. - * \param data Custom data given as an argument when calling ISR - */ -extern int gr1553rt_irq_sa - ( - void *rt, - int subadr, - int tx, - gr1553rt_irq_t func, - void *data - ); - -#define GR1553RT_BD_FLAGS_IRQEN (1<<30) -/* Initialize a descriptor entry in a list. This is typically done - * prior to scheduling the list. - * - * \param entry_no Entry number in list (descriptor index in list) - * \param flags Enable IRQ when descriptor is accessed by setting - * argument GR1553RT_BD_FLAGS_IRQEN. Enabling IRQ on a - * descriptor basis will override SA-table IRQ config. - * \param dptr Data Pointer to RX or TX operation. The LSB indicate - * if the address must be translated into Hardware address - * - this is useful when a buffer close to CPU is used - * as a data pointer and the RT core is located over PCI. - * \param next Next Entry in list. Set to 0xffff for end of list. Set - * 0xfffe for next entry in list, wrap around to entry - * zero if entry_no is last descriptor in list (circular). - */ -extern int gr1553rt_bd_init( - struct gr1553rt_list *list, - unsigned short entry_no, - unsigned int flags, - uint16_t *dptr, - unsigned short next - ); - -/* Manipulate/Read Control/Status and Data Pointer words of a buffer descriptor. - * If status is zero, the control/status word is accessed. If dptr is non-zero - * the data pointer word is accessed. - * - * \param list The list that the descriptor is located at - * - * \param entry_no The descriptor number accessed - * - * \param status IN/OUT. If zero no effect. If pointer is non-zero the - * value pointed to: - * IN: Written to Control/Status - * OUT: the value of the Control/Status word before writing. - * - * \param dptr IN/OUT. If zero no effect. If pointer is non-zero, the - * value pointed to: - * IN: non-zero: Descriptor data pointer will be updated with - * this value. Note that the LSB indicate if the address - * must be translated into hardware-aware address. - * OUT: The old data pointer is stored here. - */ -extern int gr1553rt_bd_update( - struct gr1553rt_list *list, - int entry_no, - unsigned int *status, - uint16_t **dptr - ); - -/* Get the next/current descriptor processed of a RT sub-address. - * - * \param subadr RT Subaddress - * \param txeno Pointer to where TX descriptor number is stored. - * \param rxeno Pointer to where RX descriptor number is stored. - */ -extern int gr1553rt_indication(void *rt, int subadr, int *txeno, int *rxeno); - -/* Take a GR1553RT hardware device identified by minor. - * A pointer is returned that is used internally by the GR1553RT - * driver, it is used as an input parameter 'rt' to all other - * functions that manipulate the hardware. - * - * This function initializes the RT hardware to a stopped/disable level. - */ -extern void *gr1553rt_open(int minor); - -/* Close and stop/disable the RT hardware. */ -extern void gr1553rt_close(void *rt); - -/* Configure the RT. The RT device must be configured once before - * started. A started RT device can not be configured. - * - * \param rt The RT to configure - * \param cfg Configuration parameters - */ -extern int gr1553rt_config(void *rt, struct gr1553rt_cfg *cfg); - -/* Schedule a RX or TX list on a sub address. If a list has already been - * schduled on the subaddress and on the same transfer type (RX/TX), the - * old list is replaced with the list given here. - * - * \param subadr Subaddress to schedule list on - * \param tx Subaddress transfer type: 1=TX, 0=RX - * \param list Preconfigued RT list scheduled - */ -extern void gr1553rt_sa_schedule( - void *rt, - int subadr, - int tx, - struct gr1553rt_list *list - ); - -/* Set SubAdress options. One may for example Enable or Disable a sub - * address RX and/or TX. See hardware manual for SA-Table configuration - * options. - * - * \param subadr SubAddress to configure - * \param mask Bit mask of option-bits written to subaddress config - * \param options The new options written to subaddress config. - * - */ -extern void gr1553rt_sa_setopts( - void *rt, - int subadr, - unsigned int mask, - unsigned int options - ); - -/* Get The Subaddress and transfer type of a scheduled list. Normally the - * application knows which subaddress the list is for. - * - * \param list List to lookup information for - * \param subadr Pointer to where the subaddress is stored - * \param tx Transfer type is stored here. 1=TX, 0=RX. - */ -extern void gr1553rt_list_sa( - struct gr1553rt_list *list, - int *subadr, - int *tx - ); - -/* Start RT Communication - * - * Interrupts will be enabled. The RT enabled and the "RT-run-time" - * part of the API will be opened for the user and parts that need the - * RT to be stopped are no longer available. After the RT has been - * started the configuration function can not be called. - */ -extern int gr1553rt_start(void *rt); - -/* Get Status of the RT core. See data structure gr1553rt_status for more - * information about the result. It can be used to read out: - * - time information - * - sync information - * - bus & RT status - * - * \param status Pointer to where the status words will be stored. They - * are stored according to the gr1553rt_status data structure. - */ -extern void gr1553rt_status(void *rt, struct gr1553rt_status *status); - -/* Stop RT communication. Only possible to stop an already started RT device. - * Interrupts are disabled and the RT Enable bit cleared. - */ -extern void gr1553rt_stop(void *rt); - -/* Set RT vector and/or bit word. - * - * - Vector Word is used in response to "Transmit vector word" BC commands - * - Bit Word is used in response to "Transmit bit word" BC commands - * - * - * \param mask Bit-Mask, bits that are 1 will result in that bit in the - * words register being overwritten with the value of words - * \param words Bits 31..16: Bit Word. Bits 15..0: Vector Word. - * - * Operation: - * hw_words = (hw_words & ~mask) | (words & mask) - */ -extern void gr1553rt_set_vecword( - void *rt, - unsigned int mask, - unsigned int words - ); - -/* Set selectable bits of the "Bus Status Register". The bits written - * is determined by the "mask" bit-mask. Operation: - * - * bus_status = (bus_status & ~mask) | (sts & mask) - * - */ -extern void gr1553rt_set_bussts(void *rt, unsigned int mask, unsigned int sts); - -/* Read up to MAX number of entries in eventlog log. - * - * \param dst Destination address for event log entries - * \param max Maximal number of event log entries that an be stored into dst - * - * Return - * negative Failure - * zero No entries available at the moment - * positive Number of entries copied into dst - */ -extern int gr1553rt_evlog_read(void *rt, unsigned int *dst, int max); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_701.h b/c/src/lib/libbsp/sparc/shared/include/gr_701.h deleted file mode 100644 index acfd9237a2..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr_701.h +++ /dev/null @@ -1,51 +0,0 @@ -/* GR-701 PCI Target driver. - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * Configures the GR-701 interface PCI board. - * This driver provides a AMBA PnP bus by using the general part - * of the AMBA PnP bus driver (ambapp_bus.c). - * - * Driver resources for the AMBA PnP bus provided can be set using - * gr701_set_resources(). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GR_701_H__ -#define __GR_701_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* An array of pointers to GR-701 resources. The resources will be - * used by the drivers controlling the cores on the GR-701 target AMBA bus. - * - * The gr701_resources is declared weak so that the user can override the - * default configuration. The array must be terminated with a NULL resource. - */ -extern struct drvmgr_bus_res *gr701_resources[]; - -#define GR701_OPTIONS_AMBA 0x01 -#define GR701_OPTIONS_IRQ 0x02 - -/* Print information about all GR-701 PCI boards */ -void gr701_print(int options); - -/* Print information about one GR-701 PCI board */ -void gr701_print_dev(struct drvmgr_dev *dev, int options); - -/* Register GR-701 driver */ -void gr701_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_cpci_gr740.h b/c/src/lib/libbsp/sparc/shared/include/gr_cpci_gr740.h deleted file mode 100644 index 55c28acb4c..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr_cpci_gr740.h +++ /dev/null @@ -1,61 +0,0 @@ -/* GR-CPCI-GR740 PCI Peripheral driver - * - * COPYRIGHT (c) 2017. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Configures the GR-CPIC-GR740 interface PCI board in peripheral - * mode. This driver provides a AMBA PnP bus by using the general part - * of the AMBA PnP bus driver (ambapp_bus.c). - * - * - * Driver resource options: - * NAME DEFAULT VALUE - * ahbmst2pci _RAM_START AMBA->PCI translation PCI base address - * ambaFreq 250000000 (250MHz) AMBA system frequency of GR740 - * cgEnMask 0x1f (all) Clock gating enable mask - * - * TODO/UNTESTED - * Interrupt testing - * bar0 RESOURCE 0x00000000 L2-Cache SDRAM memory - * bar1 RESOURCE 0xf0000000 L2-Cache registers - */ - -#ifndef __GR_CPCI_GR740_H__ -#define __GR_CPCI_GR740_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* An array of pointers to GR-CPCI-GR740 resources. The resources will be - * used by the drivers controlling the cores on the GR-CPCI-GR740 target - * AMBA bus. - * - * The gr_cpci_gr740_resources is declared weak so that the user can override the - * default configuration. The array must be terminated with a NULL resource. - */ -extern struct drvmgr_bus_res *gr_cpci_gr740_resources[]; - -/* Options to gr_cpci_gr740_print function */ -#define GR_CPCI_GR740_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ - -/* Print information about all GR-CPCI-GR740 PCI boards */ -void gr_cpci_gr740_print(int options); - -/* Print information about one GR-CPCI-GR740 PCI board */ -void gr_cpci_gr740_print_dev(struct drvmgr_dev *dev, int options); - -/* Register GR-CPCI-GR740 driver */ -void gr_cpci_gr740_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_leon4_n2x.h b/c/src/lib/libbsp/sparc/shared/include/gr_leon4_n2x.h deleted file mode 100644 index 9a8041202a..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr_leon4_n2x.h +++ /dev/null @@ -1,61 +0,0 @@ -/* GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver - * - * COPYRIGHT (c) 2013. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Configures the GR-CPIC-LEON4-N2X interface PCI board in peripheral - * mode. This driver provides a AMBA PnP bus by using the general part - * of the AMBA PnP bus driver (ambapp_bus.c). - * - * - * Driver resource options: - * NAME DEFAULT VALUE - * ahbmst2pci _RAM_START AMBA->PCI translation PCI base address - * ambaFreq 200000000 (200MHz) AMBA system frequency of LEON4-N2X - * cgEnMask 0x1f (all) Clock gating enable mask - * - * TODO/UNTESTED - * Interrupt testing - * bar0 RESOURCE 0x00000000 L2-Cache SDRAM memory - * bar1 RESOURCE 0xf0000000 L2-Cache registers - */ - -#ifndef __GR_CPCI_LEON4_N2X_H__ -#define __GR_CPCI_LEON4_N2X_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* An array of pointers to GR-CPCI-LEON4-N2X resources. The resources will be - * used by the drivers controlling the cores on the GR-CPCI-LEON4-N2X target - * AMBA bus. - * - * The gr_leon4_n2x_resources is declared weak so that the user can override the - * default configuration. The array must be terminated with a NULL resource. - */ -extern struct drvmgr_bus_res *gr_leon4_n2x_resources[]; - -/* Options to gr_cpci_leon4_n2x_print function */ -#define GR_LEON4_N2X_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ - -/* Print information about all GR-CPCI-LEON4-N2X PCI boards */ -void gr_leon4_n2x_print(int options); - -/* Print information about one GR-CPCI-LEON4-N2X PCI board */ -void gr_cpci_leon4_n2x_print_dev(struct drvmgr_dev *dev, int options); - -/* Register GR-CPCI-LEON4-N2X driver */ -void gr_cpci_leon4_n2x_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_adcdac.h b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_adcdac.h deleted file mode 100644 index 9e16cab96b..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_adcdac.h +++ /dev/null @@ -1,52 +0,0 @@ -/* GR-RASTA-ADCDAC PCI Target driver. - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * Configures the GR-RASTA-ADCDAC interface PCI board. - * This driver provides a AMBA PnP bus by using the general part - * of the AMBA PnP bus driver (ambapp_bus.c). - * - * Driver resources for the AMBA PnP bus provided can be set using - * gr_rasta_adcdac_set_resources(). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GR_RASTA_ADCDAC_H__ -#define __GR_RASTA_ADCDAC_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* An array of pointers to GR-RASTA-ADCDAC resources. The resources will be - * used by the drivers controlling the cores on the GR-RASTA-ADCDAC target AMBA bus. - * - * The gr_rasta_adcdac_resources is declared weak so that the user can override - * the default configuration. The array must be terminated with a NULL resource. - */ -extern struct drvmgr_bus_res *gr_rasta_adcdac_resources[]; - -/* Options to gr_rasta_io_print function */ -#define RASTA_ADCDAC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define RASTA_ADCDAC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ - -/* Print information about all GR-RASTA-IO PCI boards */ -void gr_rasta_adcdac_print(int options); - -/* Print information about one GR-RASTA-IO PCI board */ -void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options); - -/* Register GR-RASTA-IO driver */ -void gr_rasta_adcdac_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_io.h b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_io.h deleted file mode 100644 index 72a44f5151..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_io.h +++ /dev/null @@ -1,52 +0,0 @@ -/* GR-RASTA-IO PCI Target driver. - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * Configures the GR-RASTA-IO interface PCI board. - * This driver provides a AMBA PnP bus by using the general part - * of the AMBA PnP bus driver (ambapp_bus.c). - * - * Driver resources for the AMBA PnP bus provided can be set using - * gr_rasta_io_set_resources(). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GR_RASTA_IO_H__ -#define __GR_RASTA_IO_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* An array of pointers to GR-RASTA-IO resources. The resources will be - * used by the drivers controlling the cores on the GR-RASTA-IO target AMBA bus. - * - * The gr_rasta_io_resources is declared weak so that the user can override the - * default configuration. The array must be terminated with a NULL resource. - */ -extern struct drvmgr_bus_res *gr_rasta_io_resources[]; - -/* Options to gr_rasta_io_print function */ -#define RASTA_IO_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define RASTA_IO_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ - -/* Print information about GR-RASTA-IO PCI boards */ -void gr_rasta_io_print(int options); - -/* Print information about a GR-RASTA-IO PCI board */ -void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options); - -/* Register GR-RASTA-IO driver */ -void gr_rasta_io_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_spw_router.h b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_spw_router.h deleted file mode 100644 index 1cc9e41979..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_spw_router.h +++ /dev/null @@ -1,48 +0,0 @@ -/* GR-RASTA-SPW-ROUTER PCI Peripheral driver - * - * COPYRIGHT (c) 2015. - * Cobham Gaisler. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef __GR_RASTA_SPW_ROUTER_H__ -#define __GR_RASTA_SPW_ROUTER_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* An array of pointers to GR-RASTA-SPW-ROUTER resources. The resources will be - * used by the drivers controlling the cores on the GR-RASTA-SPW-ROUTER target - * AMBA bus. - * - * The gr_rasta_spw_router_resources is declared weak so that the user can - * override the default configuration. The array must be terminated with a - * NULL resource. - */ -extern struct drvmgr_bus_res *gr_rasta_spw_router_resources[]; - -/* Options to gr_rasta_spw_router_print function */ -#define RASTA_SPW_ROUTER_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define RASTA_SPW_ROUTER_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ - -/* Print information about all GR-CPCI-LEON4-N2X PCI boards */ -void gr_rasta_spw_router_print(int options); - -/* Print information about one GR-CPCI-LEON4-N2X PCI board */ -void gr_rasta_spw_router_print_dev(struct drvmgr_dev *dev, int options); - -/* Register GR-RASTA-SPW-ROUTER driver to Driver Manager */ -void gr_rasta_spw_router_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_tmtc.h b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_tmtc.h deleted file mode 100644 index 2b10ce2df3..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_tmtc.h +++ /dev/null @@ -1,103 +0,0 @@ -/* GR-RASTA-TMTC PCI Target driver. - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * Configures the GR-RASTA-TMTC interface PCI board. - * This driver provides a AMBA PnP bus by using the general part - * of the AMBA PnP bus driver (ambapp_bus.c). - * - * Driver resources for the AMBA PnP bus provided can be set using - * gr_rasta_tmtc_set_resources(). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GR_RASTA_TMTC_H__ -#define __GR_RASTA_TMTC_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* GPIO TM/TC configuration pin definitions - * --31 PWRX (1=PW2APB, 0=TM VC3/4) - * --30 PWTC (1=APB2PW, 0=TC MAP1/2) - * --29 Redundant TM (1=enable, 0=disable) - * --28 Redundant TC (1=enable, 0=disable) - * --27 Select TM output (1=GRTM, 0=PTME) - * --26 Loop back PW (1=enable, 0=disable) - * --25 Transponder clock (1=PLL, 0=PLL bypass) - * --24 PWTX-SELECT (0=TX0-0, 1=TX0-1) - * --23 PDEC Map Switch (1=on, 0=off) - * --22 PDEC Ext CPDU (1=on, 0=off) - * --21 PDEC Super User (1=on, 0=off) - * --20 PDEC RM On (1=on, 0=off) - * --19 PDEC AU Enable (1=on, 0=off) - * --18 PDEC Dynamic Mode (1=on, 0=off) - * --17 PDEC Priority (1=on, 0=off) - * --16 TC PSS Support (1=on, 0=off) - * --15 TC Mark (1=on, 0=off) - * --14 TC Pseudo (1=on, 0=off) - * --13 TC Rising Clock (1=rise, 0=fall) - * --12 TC Active High (1=high, 0=low) - * --11 Bit Lock Positive (1=high, 0=low) - * --10 RF Avail Positive (1=high, 0=low) - * -- 9 : 0 SpaceCraft ID - */ - -#define GR_TMTC_GPIO_PWRX (1<<31) -#define GR_TMTC_GPIO_PWTC (1<<30) -#define GR_TMTC_GPIO_RED_TM (1<<29) -#define GR_TMTC_GPIO_RED_TC (1<<28) -#define GR_TMTC_GPIO_GRTM_SEL (1<<27) -#define GR_TMTC_GPIO_LB_PW (1<<26) -#define GR_TMTC_GPIO_TRANSP_CLK (1<<25) -#define GR_TMTC_GPIO_PWTX_SEL (1<<24) -#define GR_TMTC_GPIO_PDEC_MAP (1<<23) -#define GR_TMTC_GPIO_PDEC_CPDU (1<<22) -#define GR_TMTC_GPIO_PDEC_SU (1<<21) -#define GR_TMTC_GPIO_PDEC_RM (1<<20) -#define GR_TMTC_GPIO_PDEC_AU (1<<19) -#define GR_TMTC_GPIO_PDEC_DYN_MODE (1<<18) -#define GR_TMTC_GPIO_PDEC_PRIO (1<<17) -#define GR_TMTC_GPIO_TC_PSS (1<<16) -#define GR_TMTC_GPIO_TC_MARK (1<<15) -#define GR_TMTC_GPIO_TC_PSEUDO (1<<14) -#define GR_TMTC_GPIO_TC_RISING_CLK (1<<13) -#define GR_TMTC_GPIO_TC_ACTIVE_HIGH (1<<12) -#define GR_TMTC_GPIO_TC_BIT_LOCK (1<<11) -#define GR_TMTC_GPIO_TC_RF_AVAIL (1<<10) -#define GR_TMTC_GPIO_SCID (0x000003ff) - -/* An array of pointers to GR-RASTA-TMTC bus resources. The resources will be - * used by the device drivers controlling the cores on the GR-RASTA-IO target - * AMBA bus. - * - * The array is defined weak, and defaults to no resources. The array must be - * terminated with a NULL resource. - */ -extern struct drvmgr_bus_res *gr_rasta_tmtc_resources[]; - -/* Options to gr_rasta_io_print function */ -#define RASTA_TMTC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define RASTA_TMTC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ - -/* Print information about GR-RASTA-TMTC PCI boards */ -void gr_rasta_tmtc_print(int options); - -/* Print information about a GR-RASTA-TMTC PCI boards */ -void gr_rasta_tmtc_print_dev(struct drvmgr_dev *dev, int options); - -/* Register GR-RASTA-TMTC driver */ -void gr_rasta_tmtc_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_tmtc_1553.h b/c/src/lib/libbsp/sparc/shared/include/gr_tmtc_1553.h deleted file mode 100644 index b6ac43da00..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gr_tmtc_1553.h +++ /dev/null @@ -1,55 +0,0 @@ -/* GR-TMTC-1553 PCI Target driver. - * - * COPYRIGHT (c) 2010. - * Cobham Gaisler AB. - * - * Configures the GR-TMTC-1553 interface PCI board. - * This driver provides a AMBA PnP bus by using the general part - * of the AMBA PnP bus driver (ambapp_bus.c). - * - * Driver resources for the AMBA PnP bus provided can be set using - * gr_tmtc_1553_set_resources(). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GR_TMTC_1553_H__ -#define __GR_TMTC_1553_H__ - -#include <drvmgr/drvmgr.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* An array of pointers to GR-TMTC-1553 resources. The resources will be - * used by the drivers controlling the cores on the GR-TMTC-1553 target AMBA bus. - * - * The gr_rasta_io_resources is declared weak so that the user can override the - * default configuration. The array must be terminated with a NULL resource. - */ -extern struct drvmgr_bus_res *gr_tmtc_1553_resources[]; - -/* Options to gr_rasta_io_print function */ -#define TMTC_1553_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ -#define TMTC_1553_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ - -/* Print information about GR-RASTA-IO PCI board */ -void gr_tmtc_1553_print(int options); - -/* Register GR-RASTA-IO driver */ -void gr_tmtc_1553_register_drv(void); - -/* Print information about all GR-TMTC-1553 devices registered to this driver */ -void gr_tmtc_1553_print(int options); - -/* Print information about one GR-TMTC-1553 device */ -void gr_tmtc_1553_print_dev(struct drvmgr_dev *dev, int options); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/gradcdac.h b/c/src/lib/libbsp/sparc/shared/include/gradcdac.h deleted file mode 100644 index b52077845f..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/gradcdac.h +++ /dev/null @@ -1,227 +0,0 @@ -/* ADC / DAC (GRADCDAC) interface -/* - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRADCDAC_H__ -#define __GRADCDAC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -struct gradcdac_regs { - volatile unsigned int config; /* 0x00 Configuration Register */ - volatile unsigned int status; /* 0x04 Status Register */ - int unused0[2]; - volatile unsigned int adc_din; /* 0x10 ADC Data Input Register */ - volatile unsigned int dac_dout; /* 0x14 DAC Data Output Register */ - int unused1[2]; - volatile unsigned int adrin; /* 0x20 Address Input Register */ - volatile unsigned int adrout; /* 0x24 Address Output Register */ - volatile unsigned int adrdir; /* 0x28 Address Direction Register */ - int unused2[1]; - volatile unsigned int data_in; /* 0x30 Data Input Register */ - volatile unsigned int data_out; /* 0x34 Data Output Register */ - volatile unsigned int data_dir; /* 0x38 Data Direction Register */ -}; - -#define GRADCDAC_CFG_DACWS 0x00f80000 -#define GRADCDAC_CFG_WRPOL 0x00040000 -#define GRADCDAC_CFG_DACDW 0x00030000 -#define GRADCDAC_CFG_ADCWS 0x0000f800 -#define GRADCDAC_CFG_RCPOL 0x00000400 -#define GRADCDAC_CFG_CSMODE 0x00000300 -#define GRADCDAC_CFG_CSPOL 0x00000080 -#define GRADCDAC_CFG_RDYMODE 0x00000040 -#define GRADCDAC_CFG_RDYPOL 0x00000020 -#define GRADCDAC_CFG_TRIGPOL 0x00000010 -#define GRADCDAC_CFG_TRIGMODE 0x0000000c -#define GRADCDAC_CFG_ADCDW 0x00000003 - -#define GRADCDAC_CFG_DACWS_BIT 19 -#define GRADCDAC_CFG_WRPOL_BIT 18 -#define GRADCDAC_CFG_DACDW_BIT 16 -#define GRADCDAC_CFG_ADCWS_BIT 11 -#define GRADCDAC_CFG_RCPOL_BIT 10 -#define GRADCDAC_CFG_CSMODE_BIT 8 -#define GRADCDAC_CFG_CSPOL_BIT 7 -#define GRADCDAC_CFG_RDYMODE_BIT 6 -#define GRADCDAC_CFG_RDYPOL_BIT 5 -#define GRADCDAC_CFG_TRIGPOL_BIT 4 -#define GRADCDAC_CFG_TRIGMODE_BIT 2 -#define GRADCDAC_CFG_ADCDW_BIT 0 - -#define GRADCDAC_STATUS_DACNO 0x40 -#define GRADCDAC_STATUS_DACRDY 0x20 -#define GRADCDAC_STATUS_DACON 0x10 -#define GRADCDAC_STATUS_ADCTO 0x08 -#define GRADCDAC_STATUS_ADCNO 0x04 -#define GRADCDAC_STATUS_ADCRDY 0x02 -#define GRADCDAC_STATUS_ADCON 0x01 - -#define GRADCDAC_STATUS_DACNO_BIT 6 -#define GRADCDAC_STATUS_DACRDY_BIT 5 -#define GRADCDAC_STATUS_DACON_BIT 4 -#define GRADCDAC_STATUS_ADCTO_BIT 3 -#define GRADCDAC_STATUS_ADCNO_BIT 2 -#define GRADCDAC_STATUS_ADCRDY_BIT 1 -#define GRADCDAC_STATUS_ADCON_BIT 0 - -#define GRADCDAC_IRQ_DAC 1 -#define GRADCDAC_IRQ_ADC 0 - -struct gradcdac_config { - unsigned char dac_ws; - char wr_pol; - unsigned char dac_dw; - unsigned char adc_ws; - char rc_pol; - unsigned char cs_mode; - char cs_pol; - char ready_mode; - char ready_pol; - char trigg_pol; - unsigned char trigg_mode; - unsigned char adc_dw; -}; - -extern void *gradcdac_open(char *devname); - -extern void gradcdac_set_config(void *cookie, struct gradcdac_config *cfg); - -extern void gradcdac_get_config(void *cookie, struct gradcdac_config *cfg); - -extern void gradcdac_set_cfg(void *cookie, unsigned int config); - -extern unsigned int gradcdac_get_cfg(void *cookie); - -extern unsigned int gradcdac_get_status(void *cookie); - -static int __inline__ gradcdac_DAC_ReqRej(unsigned int status) -{ - return (status & GRADCDAC_STATUS_DACNO); -} - -static int __inline__ gradcdac_DAC_isCompleted(unsigned int status) -{ - return (status & GRADCDAC_STATUS_DACRDY); -} - -static int __inline__ gradcdac_DAC_isOngoing(unsigned int status) -{ - return (status & GRADCDAC_STATUS_DACON); -} - -static int __inline__ gradcdac_ADC_isTimeouted(unsigned int status) -{ - return (status & GRADCDAC_STATUS_ADCTO); -} - -static int __inline__ gradcdac_ADC_ReqRej(unsigned int status) -{ - return (status & GRADCDAC_STATUS_ADCNO); -} - -static int __inline__ gradcdac_ADC_isCompleted(unsigned int status) -{ - return (status & GRADCDAC_STATUS_ADCRDY); -} - -static int __inline__ gradcdac_ADC_isOngoing(unsigned int status) -{ - return (status & GRADCDAC_STATUS_ADCON); -} - -#define GRADCDAC_ISR_BOTH 3 -#define GRADCDAC_ISR_DAC 2 -#define GRADCDAC_ISR_ADC 1 - -/* Install IRQ handler for ADC and/or DAC interrupt. - * The installed IRQ handler(ISR) must read the status - * register to clear the pending interrupt avoiding multiple - * entries to the ISR caused by the same IRQ. - * - * \param adc 1=ADC interrupt, 2=ADC interrupt, 3=ADC and DAC interrupt - * \param isr Interrupt service routine called when IRQ is fired - * \param arg custom argument passed to ISR when called. - */ -extern int gradcdac_install_irq_handler - (void *cookie, int adc, void (*isr)(void *cookie, void *arg), void *arg); - -extern void gradcdac_uninstall_irq_handler(void *cookie, int adc); - -/* Make the ADC circuitry initialize a analogue to digital - * conversion. The result can be read out by gradcdac_adc_convert_try - * or gradcdac_adc_convert. - */ -extern void gradcdac_adc_convert_start(void *cookie); - -/* Tries to read the conversion result. If the circuitry is busy - * converting the function return a non-zero value, if the conversion - * has successfully finished the function return zero. - * - * \param digital_value the resulting converted value is placed here - * \return zero = ADC conversion complete, digital_value contain current conversion result - * positive = ADC busy, digital_value contain previous conversion result - * negative = Conversion request failed. - */ -extern int gradcdac_adc_convert_try(void *cookie, unsigned short *digital_value); - -/* Waits until the ADC circuity has finished a digital to analogue - * conversion. The Waiting is implemented as a busy loop utilizing - * 100% CPU load. - * - * \return zero = Conversion ok - * negative = Conversion request failed. - */ -extern int gradcdac_adc_convert(void *cookie, unsigned short *digital_value); - -/* Try to make the DAC circuitry initialize a digital to analogue - * conversion. If the circuitry is busy by a previous conversion - * the function return a non-zero value, if the conversion is - * successfully initialized the function return zero. - */ -extern int gradcdac_dac_convert_try(void *cookie, unsigned short digital_value); - -/* Initializes a digital to analogue conversion by waiting until - * previous conversions is finished before procceding with the - * conversion. The Waiting is implemented as a busy loop utilizing - * 100% CPU load. - */ -extern void gradcdac_dac_convert(void *cookie, unsigned short digital_value); - -extern unsigned int gradcdac_get_adrinput(void *cookie); -extern void gradcdac_set_adrinput(void *cookie, unsigned int input); - -extern unsigned int gradcdac_get_adroutput(void *cookie); -extern void gradcdac_set_adroutput(void *cookie, unsigned int output); - -extern unsigned int gradcdac_get_adrdir(void *cookie); -extern void gradcdac_set_adrdir(void *cookie, unsigned int dir); - -extern unsigned int gradcdac_get_datainput(void *cookie); -extern void gradcdac_set_datainput(void *cookie, unsigned int input); - -extern unsigned int gradcdac_get_dataoutput(void *cookie); -extern void gradcdac_set_dataoutput(void *cookie, unsigned int output); - -extern unsigned int gradcdac_get_datadir(void *cookie); -extern void gradcdac_set_datadir(void *cookie, unsigned int dir); - -/* Show one or all GRADCDAC cores. If cookie is NULL all GRADCDAC's are shown */ -extern void grAdcDacShow(void *cookie); - -/* Register Driver routine */ -extern void gradcdac_register_drv (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grascs.h b/c/src/lib/libbsp/sparc/shared/include/grascs.h deleted file mode 100644 index b393e77888..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grascs.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Header file for GRASCS RTEMS driver - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRASCS_H__ -#define __GRASCS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Minimum and maximum system frequency */ -#define GRASCS_MIN_SFREQ 10000 -#define GRASCS_MAX_SFREQ 255000 - -/* Default, minimum and maximum ETR pulse frequency */ -#define GRASCS_DEFAULT_ETRFREQ 10 -#define GRASCS_MIN_ETRFREQ 1 -#define GRASCS_MAX_ETRFREQ 100 - -/* Maximum number of external time markers */ -#define GRASCS_MAX_TMS 6 - -/* Error codes */ -#define GRASCS_ERROR_STARTSTOP 1 /* Serial/synch interface is running/stopped */ -#define GRASCS_ERROR_TRANSACTIVE 2 /* Busy with transaction */ -#define GRASCS_ERROR_CAPFAULT 3 /* Core capabilities prohibit request */ - -/* Command register */ -#define GRASCS_CMD_RESET (1 << 0) -#define GRASCS_CMD_STARTSTOP (1 << 1) -#define GRASCS_CMD_ESTARTSTOP (1 << 2) -#define GRASCS_CMD_SENDTM (1 << 3) -#define GRASCS_CMD_ETRCTRL (7 << 4) -#define GRASCS_CMD_ETRCTRL_BITS 4 -#define GRASCS_CMD_SLAVESEL (15 << 8) -#define GRASCS_CMD_SLAVESEL_BITS 8 -#define GRASCS_CMD_TCDONE (1 << 12) -#define GRASCS_CMD_TMDONE (1 << 13) -#define GRASCS_CMD_US1 (255 << 16) -#define GRASCS_CMD_US1_BITS 16 -#define GRASCS_CMD_US1C (1 << 24) - -/* Clock scale register */ -#define GRASCS_CLK_ETRFREQ_BITS 12 - -/* Status register */ -#define GRASCS_STS_RUNNING (1 << 0) -#define GRASCS_STS_ERUNNING (1 << 1) -#define GRASCS_STS_TCDONE (1 << 4) -#define GRASCS_STS_TMDONE (1 << 5) -#define GRASCS_STS_DBITS_BITS 8 -#define GRASCS_STS_NSLAVES_BITS 13 -#define GRASCS_STS_USCONF_BITS 18 -#define GRASCS_STS_TMCONF_BITS 19 - -extern int ASCS_init(void); - -extern int ASCS_input_select(int slave); - -extern int ASCS_etr_select(int etr, int freq); - -extern void ASCS_start(void); - -extern void ASCS_stop(void); - -extern int ASCS_iface_status(void); - -extern int ASCS_TC_send(int *word); - -extern int ASCS_TC_send_block(int *block, int ntrans); - -extern void ASCS_TC_sync_start(void); - -extern void ASCS_TC_sync_stop(void); - -extern int ASCS_TM_recv(int *word); - -extern int ASCS_TM_recv_block(int *block, int ntrans); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grcan.h b/c/src/lib/libbsp/sparc/shared/include/grcan.h deleted file mode 100644 index 5cdbad4b01..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grcan.h +++ /dev/null @@ -1,342 +0,0 @@ -/** - * @file - * @ingroup sparc_bsp - * @defgroup can GRCAN - * @ingroup can - * @brief Macros used for grcan controller - */ - -/* - * COPYRIGHT (c) 2007. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRCAN_H__ -#define __GRCAN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -struct grcan_regs { - volatile unsigned int conf; /* 0x00 */ - volatile unsigned int stat; /* 0x04 */ - volatile unsigned int ctrl; /* 0x08 */ - volatile unsigned int dummy0[3]; /* 0x0C-0x014 */ - volatile unsigned int smask; /* 0x18 */ - volatile unsigned int scode; /* 0x1C */ - - volatile unsigned int dummy1[56]; /* 0x20-0xFC */ - - volatile unsigned int pimsr; /* 0x100 */ - volatile unsigned int pimr; /* 0x104 */ - volatile unsigned int pisr; /* 0x108 */ - volatile unsigned int pir; /* 0x10C */ - volatile unsigned int imr; /* 0x110 */ - volatile unsigned int picr; /* 0x114 */ - - volatile unsigned int dummy2[58]; /* 0x118-0x1FC */ - - volatile unsigned int tx0ctrl; /* 0x200 */ - volatile unsigned int tx0addr; /* 0x204 */ - volatile unsigned int tx0size; /* 0x208 */ - volatile unsigned int tx0wr; /* 0x20C */ - volatile unsigned int tx0rd; /* 0x210 */ - volatile unsigned int tx0irq; /* 0x214 */ - - volatile unsigned int dummy3[58]; /* 0x218-0x2FC */ - - volatile unsigned int rx0ctrl; /* 0x300 */ - volatile unsigned int rx0addr; /* 0x304 */ - volatile unsigned int rx0size; /* 0x308 */ - volatile unsigned int rx0wr; /* 0x30C */ - volatile unsigned int rx0rd; /* 0x310 */ - volatile unsigned int rx0irq; /* 0x314 */ - volatile unsigned int rx0mask; /* 0x318 */ - volatile unsigned int rx0code; /* 0x31C */ -}; - -struct grcan_stats { - unsigned int passive_cnt; - unsigned int overrun_cnt; - unsigned int rxsync_cnt; - unsigned int txsync_cnt; - unsigned int txloss_cnt; - unsigned int ahberr_cnt; - unsigned int ints; - unsigned int busoff_cnt; -}; - -struct grcan_timing { - unsigned char scaler; - unsigned char ps1; - unsigned char ps2; - unsigned int rsj; - unsigned char bpr; -}; - -struct grcan_selection { - int selection; - int enable0; - int enable1; -}; - -struct grcan_filter { - unsigned long long mask; - unsigned long long code; -}; - -/* CAN MESSAGE */ -typedef struct { - char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ - char rtr; /* RTR - Remote Transmission Request */ - char unused; /* unused */ - unsigned char len; - unsigned char data[8]; - unsigned int id; -} CANMsg; - -enum { - GRCAN_RET_OK = 0, - GRCAN_RET_INVARG = -1, - GRCAN_RET_NOTSTARTED = -2, - GRCAN_RET_TIMEOUT = -3, - /* Bus-off condition detected (request aborted by driver) */ - GRCAN_RET_BUSOFF = -4, - /* AHB error condition detected (request aborted by driver) */ - GRCAN_RET_AHBERR = -5, -}; - -/* - * User functions can cause these transitions: - * STATE_STOPPED -> STATE_STARTED - * STATE_STARTED -> STATE_STOPPED - * STATE_BUSOFF -> STATE_STOPPED - * STATE_AHBERR -> STATE_STOPPED - * - * ISR can cause these transition - * STATE_STARTED -> STATE_BUSOFF - * STATE_STARTED -> STATE_AHBERR - * - * STATE_BUSOFF is entered from ISR on bus-off condition. STATE_AHBERR is - * entered from ISR on AHB DMA errors on RX/TX operations. At transition the ISR - * disables DMA, masks all interrupts and releases semaphores. - */ -enum grcan_state { - STATE_STOPPED = 0, - STATE_STARTED = 1, - STATE_BUSOFF = 2, - STATE_AHBERR = 3, -}; - -#define GRCAN_CFG_ABORT 0x00000001 -#define GRCAN_CFG_ENABLE0 0x00000002 -#define GRCAN_CFG_ENABLE1 0x00000004 -#define GRCAN_CFG_SELECTION 0x00000008 -#define GRCAN_CFG_SILENT 0x00000010 -#define GRCAN_CFG_BPR 0x00000300 -#define GRCAN_CFG_RSJ 0x00007000 -#define GRCAN_CFG_PS1 0x00f00000 -#define GRCAN_CFG_PS2 0x000f0000 -#define GRCAN_CFG_SCALER 0xff000000 - -#define GRCAN_CFG_BPR_BIT 8 -#define GRCAN_CFG_RSJ_BIT 12 -#define GRCAN_CFG_PS1_BIT 20 -#define GRCAN_CFG_PS2_BIT 16 -#define GRCAN_CFG_SCALER_BIT 24 - -#define GRCAN_CTRL_RESET 0x2 -#define GRCAN_CTRL_ENABLE 0x1 - -#define GRCAN_TXCTRL_ENABLE 1 -#define GRCAN_TXCTRL_ONGOING 1 - -#define GRCAN_RXCTRL_ENABLE 1 -#define GRCAN_RXCTRL_ONGOING 1 - -/* Relative offset of IRQ sources to AMBA Plug&Play */ -#define GRCAN_IRQ_IRQ 0 -#define GRCAN_IRQ_TXSYNC 1 -#define GRCAN_IRQ_RXSYNC 2 - -#define GRCAN_ERR_IRQ 0x1 -#define GRCAN_OFF_IRQ 0x2 -#define GRCAN_OR_IRQ 0x4 -#define GRCAN_RXAHBERR_IRQ 0x8 -#define GRCAN_TXAHBERR_IRQ 0x10 -#define GRCAN_RXIRQ_IRQ 0x20 -#define GRCAN_TXIRQ_IRQ 0x40 -#define GRCAN_RXFULL_IRQ 0x80 -#define GRCAN_TXEMPTY_IRQ 0x100 -#define GRCAN_RX_IRQ 0x200 -#define GRCAN_TX_IRQ 0x400 -#define GRCAN_RXSYNC_IRQ 0x800 -#define GRCAN_TXSYNC_IRQ 0x1000 -#define GRCAN_RXERR_IRQ 0x2000 -#define GRCAN_TXERR_IRQ 0x4000 -#define GRCAN_RXMISS_IRQ 0x8000 -#define GRCAN_TXLOSS_IRQ 0x10000 - -#define GRCAN_STAT_PASS 0x1 -#define GRCAN_STAT_OFF 0x2 -#define GRCAN_STAT_OR 0x4 -#define GRCAN_STAT_AHBERR 0x8 -#define GRCAN_STAT_ACTIVE 0x10 -#define GRCAN_STAT_RXERRCNT 0xff00 -#define GRCAN_STAT_TXERRCNT 0xff0000 - -/* - * Return number of GRCAN devices available to driver - */ -extern int grcan_dev_count(void); - -/* - * Open a GRCAN device - * - * dev_no: Device number to open - * return: Device handle to use with all other grcan_ API functions. The - * function returns NULL if device can not be opened. - */ -extern void *grcan_open(int dev_no); - -/* - * Open a GRCAN device by name. Finds device index then calls - * grcan_open(index). - * - * name: Device name to open - * dev_no: Device number matching name. Will be set if device found. - * return: Device handle to use with all other grcan_ API functions. The - * function returns NULL if device can not be opened or not found. - */ -extern void *grcan_open_by_name(char *name, int *dev_no); - -/* - * Close a GRCAN device - * - * return: This function always returns 0 (success) - */ -extern int grcan_close(void *d); - -/* - * Receive CAN messages - * - * Multiple CAN messages can be received in one call. - * - * d: Device handle - * msg: Pointer to receive messages - * count: Number of CAN messages to receive - * - * return: - * >=0: Number of CAN messages received. This can be - * less than the count parameter. - * GRCAN_RET_INVARG: count parameter less than one or NULL msg. - * GRCAN_RET_NOTSTARTED: Device not in started mode - * GRCAN_RET_TIMEOUT: Timeout in non-blocking mode - * GRCAN_RET_BUSOFF: A read was interrupted by a bus-off error. - * Device has left started mode. - * GRCAN_RET_AHBERR: Similar to BUSOFF, but was caused by AHB Error. - */ -extern int grcan_read( - void *d, - CANMsg *msg, - size_t count -); - -/* - * Transmit CAN messages - * - * Multiple CAN messages can be transmit in one call. - * - * d: Device handle - * msg: Pointer to messages to transmit - * count: Number of CAN messages to transmit - * - * return: - * >=0: Number of CAN messages transmitted. This can be - * less than the count parameter. - * GRCAN_RET_INVARG: count parameter less than one. - * GRCAN_RET_NOTSTARTED: Device not in started mode - * GRCAN_RET_TIMEOUT: Timeout in non-blocking mode - * GRCAN_RET_BUSOFF: A write was interrupted by a Bus-off error. - * Device has left started mode - * GRCAN_RET_AHBERR: Similar to BUSOFF, but was caused by AHB Error. - */ -extern int grcan_write( - void *d, - CANMsg *msg, - size_t count -); - -/* - * Returns current GRCAN software state - * - * If STATE_BUSOFF or STATE_AHBERR is returned then the function grcan_stop() - * shall be called before continue using the driver. - * - * d: Device handle - * return: - * STATE_STOPPED Stopped - * STATE_STARTED Started - * STATE_BUSOFF Bus-off has been detected - * STATE_AHBERR AHB error has been detected - */ -extern int grcan_get_state(void *d); - -/* The remaining functions return 0 on success and non-zero on failure. */ - -/* Functions controlling operational - * mode - */ -/* Bring the link up after open or bus-off */ -extern int grcan_start(void *d); -/* stop to change baud rate/config or closing down */ -extern int grcan_stop(void *d); -/* Wait until all TX messages have been sent */ -extern int grcan_flush(void *d); - -/* Functions that require connection - * to be stopped - */ -/* enable silent mode read only state */ -extern int grcan_set_silent(void *d, int silent); -/* enable/disable stopping link on AHB Error */ -extern int grcan_set_abort(void *d, int abort); -/* Set Enable0,Enable1,Selection */ -extern int grcan_set_selection(void *d, const struct grcan_selection *selection); -/* Set baudrate by using driver's baud rate timing calculation routines */ -extern int grcan_set_speed(void *d, unsigned int hz); -/* Set baudrate by specifying the timing registers manually */ -extern int grcan_set_btrs(void *d, const struct grcan_timing *timing); - -/* Functions can be called whenever */ -/* Enable/disable Blocking on reception (until at least one message has been received) */ -int grcan_set_rxblock(void* d, int block); -/* Enable/disable Blocking on transmission (until at least one message has been transmitted) */ -int grcan_set_txblock(void* d, int block); -/* Enable/disable Blocking until all requested messages has been sent */ -int grcan_set_txcomplete(void* d, int complete); -/* Enable/disable Blocking until all requested has been received */ -int grcan_set_rxcomplete(void* d, int complete); -/* Get statistics */ -extern int grcan_get_stats(void *d, struct grcan_stats *stats); -/* Clear statistics */ -extern int grcan_clr_stats(void *d); -/* Set Acceptance filters, provide pointer to "struct grcan_filter" or NULL to disable filtering (let all messages pass) */ -extern int grcan_set_afilter(void *d, const struct grcan_filter *filter); -/* Set Sync Messages RX/TX filters, NULL disables the IRQ completely */ -extern int grcan_set_sfilter(void *d, const struct grcan_filter *filter); -/* Get status register of GRCAN core */ -extern int grcan_get_status(void *d, unsigned int *status); - -void grcan_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grctm.h b/c/src/lib/libbsp/sparc/shared/include/grctm.h deleted file mode 100644 index 5ff81559aa..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grctm.h +++ /dev/null @@ -1,171 +0,0 @@ -/* GRCTM - CCSDS Time Manager - register driver interface. - * - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRCTM_H__ -#define __GRCTM_H__ - -#define DAT0_IRQ 0x1 -#define DAT1_IRQ 0x2 -#define DAT2_IRQ 0x4 -#define PULSE0_IRQ 0x10 -#define PULSE1_IRQ 0x20 -#define PULSE2_IRQ 0x40 -#define PULSE3_IRQ 0x80 -#define PULSE4_IRQ 0x100 -#define PULSE5_IRQ 0x200 -#define PULSE6_IRQ 0x400 -#define PULSE7_IRQ 0x800 - -struct grctm_regs { - volatile unsigned int grr; - volatile unsigned int gcr; - volatile unsigned int gsr; - volatile unsigned int unused[2]; - volatile unsigned int pfr; - volatile unsigned int etcr; - volatile unsigned int etfr; - volatile unsigned int dcr0; - volatile unsigned int dfr0; - volatile unsigned int dcr1; - volatile unsigned int dfr1; - volatile unsigned int dcr2; - volatile unsigned int dfr2; - volatile unsigned int stcr; - volatile unsigned int stfr; - volatile unsigned int pdr[8]; - volatile unsigned int pimsr; - volatile unsigned int pimr; - volatile unsigned int pisr; - volatile unsigned int pir; - volatile unsigned int imr; - volatile unsigned int picr; - volatile unsigned int unused1[2]; - volatile unsigned int etir; - volatile unsigned int fsir; - volatile unsigned int serconf; - volatile unsigned int unused2; - volatile unsigned int twsc; - volatile unsigned int twadj; - volatile unsigned int twtx; - volatile unsigned int twrx; -}; - -struct grctm_stats { - - /* IRQ Stats */ - unsigned int nirqs; - unsigned int pulse; -}; - -/* Function ISR callback prototype */ -typedef void (*grctm_isr_t)(unsigned int pimr, void *data); - -/* Open a GRCTM device by minor number. */ -extern void *grctm_open(int minor); - -/* Close a previously opened GRCTM device */ -extern void grctm_close(void *spwcuc); - -/* Hardware Reset of GRCTM */ -extern int grctm_reset(void *grctm); - -/* Enable Interrupts at Interrupt controller */ -extern void grctm_int_enable(void *grctm); - -/* Disable Interrupts at Interrupt controller */ -extern void grctm_int_disable(void *grctm); - -/* Clear Statistics gathered by the driver */ -extern void grctm_clr_stats(void *grctm); - -/* Get Statistics gathered by the driver */ -extern void grctm_get_stats(void *grctm, struct grctm_stats *stats); - -/* Register an Interrupt handler and custom data, the function call is - * removed by setting func to NULL. - */ -extern void grctm_int_register(void *grctm, grctm_isr_t func, void *data); - -/* Enable external synchronisation (from spwcuc) */ -extern void grctm_enable_ext_sync(void *grctm); - -/* Disable external synchronisation (from spwcuc) */ -extern void grctm_disable_ext_sync(void *grctm); - -/* Enable TimeWire synchronisation */ -extern void grctm_enable_tw_sync(void *grctm); - -/* Disable TimeWire synchronisation */ -extern void grctm_disable_tw_sync(void *grctm); - -/* Disable frequency synthesizer from driving ET */ -extern void grctm_disable_fs(void *grctm); - -/* Enable frequency synthesizer to drive ET */ -extern void grctm_enable_fs(void *grctm); - -/* Return elapsed coarse time */ -extern unsigned int grctm_get_et_coarse(void *grctm); - -/* Return elapsed fine time */ -extern unsigned int grctm_get_et_fine(void *grctm); - -/* Return elapsed time (coarse and fine) */ -extern unsigned long long grctm_get_et(void *grctm); - -/* Return 1 if specified datation has been latched */ -extern int grctm_is_dat_latched(void *grctm, int dat); - -/* Set triggering edge of datation input */ -extern void grctm_set_dat_edge(void *grctm, int dat, int edge); - -/* Return latched datation coarse time */ -extern unsigned int grctm_get_dat_coarse(void *grctm, int dat); - -/* Return latched datation fine time */ -extern unsigned int grctm_get_dat_fine(void *grctm, int dat); - -/* Return latched datation ET */ -extern unsigned long long grctm_get_dat_et(void *grctm, int dat); - -/* Return current pulse configuration */ -extern unsigned int grctm_get_pulse_reg(void *grctm, int pulse); - -/* Set pulse register */ -extern void grctm_set_pulse_reg(void *grctm, int pulse, unsigned int val); - -/* Configure pulse: pp = period, pw = width, pl = level, en = enable */ -extern void grctm_cfg_pulse(void *grctm, int pulse, int pp, int pw, int pl, int en); - -/* Enable pulse output */ -extern void grctm_enable_pulse(void *grctm, int pulse); - -/* Disable pulse output */ -extern void grctm_disable_pulse(void *grctm, int pulse); - -/* Clear interrupts */ -extern void grctm_clear_irqs(void *grctm, int irqs); - -/* Enable interrupts */ -extern void grctm_enable_irqs(void *grctm, int irqs); - -/* Set Frequency synthesizer increment */ -void grctm_set_fs_incr(void *grctm, int incr); - -/* Set ET increment */ -void grctm_set_et_incr(void *grctm, int incr); - -/* Get register base address */ -struct grctm_regs *grctm_get_regs(void *grctm); - -/* Register the GRCTM driver to Driver Manager */ -extern void grctm_register(void); - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/greth.h b/c/src/lib/libbsp/sparc/shared/include/greth.h deleted file mode 100644 index 9209d823e3..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/greth.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Cobham Gaisler ethernet MAC driver - * adapted from Opencores driver by Marko Isomaki - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRETH_H__ -#define __GRETH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Ethernet configuration registers */ - -typedef struct _greth_regs { - volatile uint32_t ctrl; /* Ctrl Register */ - volatile uint32_t status; /* Status Register */ - volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */ - volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */ - volatile uint32_t mdio_ctrl; /* MDIO control and status */ - volatile uint32_t txdesc; /* Transmit descriptor pointer */ - volatile uint32_t rxdesc; /* Receive descriptor pointer */ -} greth_regs; - -#define GRETH_TOTAL_BD 128 -#define GRETH_MAXBUF_LEN 1520 - -/* Tx BD */ -#define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */ -#define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */ -#define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */ -#define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */ -#define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */ -#define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */ -#define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */ - -#define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */ -#define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */ -#define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */ - -#define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \ - GRETH_TXD_RETLIM | \ - GRETH_TXD_LATECOL) - -#define GRETH_TXD_CS (GRETH_TXD_IPCS | \ - GRETH_TXD_TCPCS | \ - GRETH_TXD_UDPCS) - -/* Rx BD */ -#define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */ -#define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */ -#define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */ - -#define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */ -#define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */ -#define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */ -#define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */ -#define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */ -#define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */ -#define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */ -#define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/ -#define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */ -#define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */ -#define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */ - - -#define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \ - GRETH_RXD_DRIBBLE | \ - GRETH_RXD_TOOLONG | \ - GRETH_RXD_CRCERR) - -/* CTRL Register */ -#define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */ -#define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */ -#define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */ -#define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */ -#define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */ -#define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */ -#define GRETH_CTRL_RST 0x00000040 /* Reset MAC */ -#define GRETH_CTRL_SP 0x00000080 /* 100MBit speed mode */ -#define GRETH_CTRL_GB 0x00000100 /* 1GBit speed mode */ -#define GRETH_CTRL_DD 0x00001000 /* Disable EDCL Duplex Detection */ -#define GRETH_CTRL_ED 0x00004000 /* EDCL Disable */ - -/* Status Register */ -#define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */ -#define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */ -#define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */ -#define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */ -#define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */ -#define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */ - -/* MDIO Control */ -#define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */ -#define GRETH_MDIO_READ 0x00000002 /* MDIO Read */ -#define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */ -#define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */ -#define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */ -#define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */ -#define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */ - - -/* MII registers */ -#define GRETH_MII_EXTADV_1000FD 0x00000200 -#define GRETH_MII_EXTADV_1000HD 0x00000100 -#define GRETH_MII_EXTPRT_1000FD 0x00000800 -#define GRETH_MII_EXTPRT_1000HD 0x00000400 - -#define GRETH_MII_100T4 0x00000200 -#define GRETH_MII_100TXFD 0x00000100 -#define GRETH_MII_100TXHD 0x00000080 -#define GRETH_MII_10FD 0x00000040 -#define GRETH_MII_10HD 0x00000020 - - -/* Attach routine */ - -void greth_register_drv(void); - -/* PHY data */ -struct phy_device_info -{ - int vendor; - int device; - int rev; - - int adv; - int part; - - int extadv; - int extpart; -}; - -/* Limit speed modes advertised during auto-negotiation */ -#define GRETH_ADV_10_HD 0x0001 -#define GRETH_ADV_10_FD 0x0002 -#define GRETH_ADV_100_HD 0x0004 -#define GRETH_ADV_100_FD 0x0008 -#define GRETH_ADV_1000_HD 0x0010 -#define GRETH_ADV_1000_FD 0x0020 -#define GRETH_ADV_ALL 0x003f -/* -#ifdef CPU_U32_FIX -void ipalign(struct mbuf *m); -#endif - -*/ -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/c/src/lib/libbsp/sparc/shared/include/grgpio.h b/c/src/lib/libbsp/sparc/shared/include/grgpio.h deleted file mode 100644 index c49054548c..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grgpio.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * GRGPIO GPIO Driver interface. - * - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRGPIO_H__ -#define __GRGPIO_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -extern void grgpio_register_drv (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/griommu.h b/c/src/lib/libbsp/sparc/shared/include/griommu.h deleted file mode 100644 index 2bafe4c513..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/griommu.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * GRIOMMU Driver Interface - * - * COPYRIGHT (c) 2017 - * Cobham Gaisler AB - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * OVERVIEW - * ======== - * This driver controls the GRIOMMU device located - * at an on-chip AMBA. - */ - -#ifndef __GRIOMMU_H__ -#define __GRIOMMU_H__ - -#include <stdint.h> -#include <stdio.h> - -#ifdef __cplusplus -extern "C" { -#endif - -extern void griommu_register_drv(void); - -#define GRIOMMU_ERR_OK 0 -#define GRIOMMU_ERR_NOINIT -1 -#define GRIOMMU_ERR_EINVAL -2 -#define GRIOMMU_ERR_IMPLEMENTED -3 -#define GRIOMMU_ERR_NOTFOUND -4 - -/* Size of APV (has to be divided by page size in bytes) */ -#define GRIOMMU_APV_SIZE 0x20000000 - -/* Alignment of APV */ -#define GRIOMMU_APV_ALIGN 0x10 - -/* IOMMU APV allocation helper functions */ -extern void * griommu_apv_new(void); -extern void griommu_apv_delete(void * apv); - -/* IOMMU Master Setup */ - -/* IOMMU Master find */ -/* - * GRIOMMU MASTER register fields - */ -#define MASTER_VENDOR (0xff << MASTER_VENDOR_BIT) -#define MASTER_DEVICE (0xfff << MASTER_DEVICE_BIT) -#define MASTER_BS (0x1 << MASTER_BS_BIT) -#define MASTER_GROUP (0xf << MASTER_GROUP_BIT) - -#define MASTER_VENDOR_BIT 24 -#define MASTER_DEVICE_BIT 12 -#define MASTER_BS_BIT 4 -#define MASTER_GROUP_BIT 0 - -#define GRIOMMU_OPTIONS_BUS0 0 -#define GRIOMMU_OPTIONS_BUS1 1 -extern int griommu_master_setup(int master, int group, int options); -extern int griommu_master_find(int vendor, int device, int instance); -extern int griommu_master_info(int master, uint32_t * info); -#define griommu_get_master_vendor(info) \ - ((info & MASTER_VENDOR) >> MASTER_VENDOR_BIT) -#define griommu_get_master_device(info) \ - ((info & MASTER_DEVICE) >> MASTER_DEVICE_BIT) -#define griommu_get_master_routing(info) \ - ((info & MASTER_BS) >> MASTER_BS_BIT) -#define griommu_get_master_group(info) \ - ((info & MASTER_GROUP) >> MASTER_GROUP_BIT) - -/* IOMMU Group Setup */ -#define GRIOMMU_OPTIONS_GROUP_PASSTHROUGH 2 -#define GRIOMMU_OPTIONS_GROUP_ENABLE 1 -#define GRIOMMU_OPTIONS_GROUP_DISABLE 0 -extern int griommu_group_setup(int group, void * apv, int options); -extern int griommu_group_info(int group, uint32_t * info); -#define GRIOMMU_OPTIONS_APV_ALLOW 0x1 -#define GRIOMMU_OPTIONS_APV_DONTALLOW 0x0 -extern int griommu_group_apv_init(int group, int options); -extern int griommu_group_apv_address_set(int group, uint32_t addr, int size, - int options); -extern int griommu_group_apv_page_set(int group, int index, int size, - int options); -extern int griommu_group_apv_flush(int group); - -/* IOMMU Setup */ -/* - * GRIOMMU CTRL register fields - */ -#define CTRL_PGSZ (0x7 << CTRL_PGSZ_BIT) -#define CTRL_LB (0x1 << CTRL_LB_BIT) -#define CTRL_SP (0x1 << CTRL_SP_BIT) -#define CTRL_ITR (0xf << CTRL_ITR_BIT) -#define CTRL_DP (0x1 << CTRL_DP_BIT) -#define CTRL_SIV (0x1 << CTRL_SIV_BIT) -#define CTRL_HPROT (0x3 << CTRL_HPROT_BIT) -#define CTRL_AU (0x1 << CTRL_AU_BIT) -#define CTRL_WP (0x1 << CTRL_WP_BIT) -#define CTRL_DM (0x1 << CTRL_DM_BIT) -#define CTRL_GS (0x1 << CTRL_GS_BIT) -#define CTRL_CE (0x1 << CTRL_CE_BIT) -#define CTRL_PM (0x3 << CTRL_PM_BIT) -#define CTRL_PM_APV (0x0 << CTRL_PM_BIT) -#define CTRL_PM_IOMMU (0x1 << CTRL_PM_BIT) -#define CTRL_EN (0x1 << CTRL_EN_BIT) - -#define CTRL_PGSZ_BIT 18 -#define CTRL_LB_BIT 17 -#define CTRL_SP_BIT 16 -#define CTRL_ITR_BIT 12 -#define CTRL_DP_BIT 11 -#define CTRL_SIV_BIT 10 -#define CTRL_HPROT_BIT 8 -#define CTRL_AU_BIT 7 -#define CTRL_WP_BIT 6 -#define CTRL_DM_BIT 5 -#define CTRL_GS_BIT 4 -#define CTRL_CE_BIT 3 -#define CTRL_PM_BIT 1 -#define CTRL_EN_BIT 0 - -#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS0 0 -#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS1 CTRL_LB -#define GRIOMMU_OPTIONS_CACHE_DISABLE 0 -#define GRIOMMU_OPTIONS_CACHE_ENABLE CTRL_CE -#define GRIOMMU_OPTIONS_GROUPADDRESSING_DISABLE 0 -#define GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE CTRL_GS -#define GRIOMMU_OPTIONS_WPROTONLY_DISABLE 0 -#define GRIOMMU_OPTIONS_WPROTONLY_ENABLE CTRL_WP -#define GRIOMMU_OPTIONS_AHBUPDATE_DISABLE 0 -#define GRIOMMU_OPTIONS_AHBUPDATE_ENABLE CTRL_AU -#define GRIOMMU_OPTIONS_PREFETCH_DISABLE CTRL_DP -#define GRIOMMU_OPTIONS_PREFETCH_ENABLE 0 -#define GRIOMMU_OPTIONS_PAGESIZE_4KIB 0 -#define GRIOMMU_OPTIONS_PAGESIZE_8KIB (0x1 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_16KIB (0x2 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_32KIB (0x3 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_64KIB (0x4 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_128KIB (0x5 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_256KIB (0x6 << CTRL_PGSZ_BIT) -#define GRIOMMU_OPTIONS_PAGESIZE_512KIB (0x7 << CTRL_PGSZ_BIT) -extern int griommu_setup(int options); -extern int griommu_status(void); - -#define GRIOMMU_MODE_IOMMU 1 -#define GRIOMMU_MODE_GROUPAPV 0 -extern int griommu_enable(int mode); -extern int griommu_disable(void); - -/* IOMMU APV setup */ -extern int griommu_apv_flush(void); -extern int griommu_apv_init(void * apv, int options); -extern int griommu_apv_address_set(void * apv, uint32_t addr, int size, - int options); -extern int griommu_apv_page_set(void * apv, int index, int size, int options); - -/* GRIOMMU Interrupts */ -/* Function Interrupt-Code ISR callback prototype. - * arg - Custom arg provided by user - * access - AHB Access that failed - * status - Error status register of the GRIOMMU core - */ -typedef void (*griommu_isr_t)(void *arg, uint32_t access, uint32_t status); -#define GRIOMMU_INTERRUPT_ALL (0x2f << 0) -#define GRIOMMU_INTERRUPT_PARITY_ERROR (0x1 << 5) -#define GRIOMMU_INTERRUPT_FLUSH_COMPLETED (0x1 << 3) -#define GRIOMMU_INTERRUPT_FLUSH_START (0x1 << 2) -#define GRIOMMU_INTERRUPT_ACCESS_DENIED (0x1 << 1) -#define GRIOMMU_INTERRUPT_TRANSLATION_ERROR (0x1 << 0) -extern int griommu_isr_register(griommu_isr_t isr, void * arg, int options); -extern int griommu_isr_unregister(void); -extern int griommu_interrupt_unmask(int options); -extern int griommu_interrupt_mask(int options); - -extern int griommu_error_status(uint32_t * access); - -extern int griommu_print(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __GRIOMMU_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/grlib.h b/c/src/lib/libbsp/sparc/shared/include/grlib.h deleted file mode 100644 index a2d0877fb8..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grlib.h +++ /dev/null @@ -1,164 +0,0 @@ -/** - * @file - * @ingroup amba - * @brief Common GRLIB AMBA Core Register definitions - */ - -/* - * COPYRIGHT (c) 2012 - * Aeroflex Gaisler - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRLIB_H__ -#define __GRLIB_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* ESA MEMORY CONTROLLER */ -struct mctrl_regs { - unsigned int mcfg1; - unsigned int mcfg2; - unsigned int mcfg3; -}; - -/* APB UART */ -struct apbuart_regs { - volatile unsigned int data; - volatile unsigned int status; - volatile unsigned int ctrl; - volatile unsigned int scaler; -}; - -/* IRQMP and IRQAMP interrupt controller timestamps */ -struct irqmp_timestamp_regs { - volatile unsigned int counter; /* 0x00 */ - volatile unsigned int control; /* 0x04 */ - volatile unsigned int assertion; /* 0x08 */ - volatile unsigned int ack; /* 0x0c */ -}; - -/* IRQMP and IRQAMP interrupt controllers */ -struct irqmp_regs { - volatile unsigned int ilevel; /* 0x00 */ - volatile unsigned int ipend; /* 0x04 */ - volatile unsigned int iforce; /* 0x08 */ - volatile unsigned int iclear; /* 0x0c */ - volatile unsigned int mpstat; /* 0x10 */ - volatile unsigned int bcast; /* 0x14 */ - volatile unsigned int notused02; /* 0x18 */ - volatile unsigned int wdgctrl; /* 0x1c */ - volatile unsigned int ampctrl; /* 0x20 */ - volatile unsigned int icsel[2]; /* 0x24,0x28 */ - volatile unsigned int notused13; /* 0x2c */ - volatile unsigned int notused20; /* 0x30 */ - volatile unsigned int notused21; /* 0x34 */ - volatile unsigned int notused22; /* 0x38 */ - volatile unsigned int notused23; /* 0x3c */ - volatile unsigned int mask[16]; /* 0x40 */ - volatile unsigned int force[16]; /* 0x80 */ - /* Extended IRQ registers */ - volatile unsigned int intid[16]; /* 0xc0 */ - volatile struct irqmp_timestamp_regs timestamp[16]; /* 0x100 */ - volatile unsigned int resetaddr[4]; /* 0x200 */ - volatile unsigned int resv0[12]; /* 0x210 - 0x23C */ - volatile unsigned int pboot; /* 0x240 */ - volatile unsigned int resv1[47]; /* 0x244 - 0x2FC */ - volatile unsigned int irqmap[8]; /* 0x300 - 0x31C */ - volatile unsigned int resv2[824]; /* 0x320 - 0x1000 */ -}; - -/* GPTIMER Timer instance */ -struct gptimer_timer_regs { - volatile unsigned int value; - volatile unsigned int reload; - volatile unsigned int ctrl; - volatile unsigned int notused; -}; - -#define GPTIMER_TIMER_CTRL_EN 0x00000001U -#define GPTIMER_TIMER_CTRL_RS 0x00000002U -#define GPTIMER_TIMER_CTRL_LD 0x00000004U -#define GPTIMER_TIMER_CTRL_IE 0x00000008U -#define GPTIMER_TIMER_CTRL_IP 0x00000010U -#define GPTIMER_TIMER_CTRL_CH 0x00000020U -#define GPTIMER_TIMER_CTRL_DH 0x00000040U - -/* GPTIMER common registers */ -struct gptimer_regs { - volatile unsigned int scaler_value; /* common timer registers */ - volatile unsigned int scaler_reload; - volatile unsigned int cfg; - volatile unsigned int notused; - struct gptimer_timer_regs timer[7]; -}; - -/* GRGPIO GPIO */ -struct grgpio_regs { - volatile unsigned int data; /* 0x00 I/O port data register */ - volatile unsigned int output; /* 0x04 I/O port output register */ - volatile unsigned int dir; /* 0x08 I/O port direction register */ - volatile unsigned int imask; /* 0x0C Interrupt mask register */ - volatile unsigned int ipol; /* 0x10 Interrupt polarity register */ - volatile unsigned int iedge; /* 0x14 Interrupt edge register */ - volatile unsigned int bypass; /* 0x18 Bypass register */ - volatile unsigned int cap; /* 0x1C Capability register */ - volatile unsigned int irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */ - volatile unsigned int res_30; /* 0x30 Reserved */ - volatile unsigned int res_34; /* 0x34 Reserved */ - volatile unsigned int res_38; /* 0x38 Reserved */ - volatile unsigned int res_3C; /* 0x3C Reserved */ - volatile unsigned int iavail; /* 0x40 Interrupt available register */ - volatile unsigned int iflag; /* 0x44 Interrupt flag register */ - volatile unsigned int res_48; /* 0x48 Reserved */ - volatile unsigned int pulse; /* 0x4C Pulse register */ - volatile unsigned int res_50; /* 0x50 Reserved */ - volatile unsigned int output_or; /* 0x54 I/O port output register, logical-OR */ - volatile unsigned int dir_or; /* 0x58 I/O port direction register, logical-OR */ - volatile unsigned int imask_or; /* 0x5C Interrupt mask register, logical-OR */ - volatile unsigned int res_60; /* 0x60 Reserved */ - volatile unsigned int output_and; /* 0x64 I/O port output register, logical-AND */ - volatile unsigned int dir_and; /* 0x68 I/O port direction register, logical-AND */ - volatile unsigned int imask_and; /* 0x6C Interrupt mask register, logical-AND */ - volatile unsigned int res_70; /* 0x70 Reserved */ - volatile unsigned int output_xor; /* 0x74 I/O port output register, logical-XOR */ - volatile unsigned int dir_xor; /* 0x78 I/O port direction register, logical-XOR */ - volatile unsigned int imask_xor; /* 0x7C Interrupt mask register, logical-XOR */ -}; - -/* L2C - Level 2 Cache Controller registers */ -struct l2c_regs { - volatile unsigned int control; /* 0x00 Control register */ - volatile unsigned int status; /* 0x04 Status register */ - volatile unsigned int flush_mem_addr; /* 0x08 Flush (Memory address) */ - volatile unsigned int flush_set_index; /* 0x0c Flush (set, index) */ - volatile unsigned int access_counter; /* 0x10 */ - volatile unsigned int hit_counter; /* 0x14 */ - volatile unsigned int bus_cycle_counter; /* 0x18 */ - volatile unsigned int bus_usage_counter; /* 0x1c */ - volatile unsigned int error_status_control; /* 0x20 Error status/control */ - volatile unsigned int error_addr; /* 0x24 Error address */ - volatile unsigned int tag_check_bit; /* 0x28 TAG-check-bit */ - volatile unsigned int data_check_bit; /* 0x2c Data-check-bit */ - volatile unsigned int scrub_control_status; /* 0x30 Scrub Control/Status */ - volatile unsigned int scrub_delay; /* 0x34 Scrub Delay */ - volatile unsigned int error_injection; /* 0x38 Error injection */ - volatile unsigned int access_control; /* 0x3c Access control */ - volatile unsigned int reserved_40[16]; /* 0x40 Reserved */ - volatile unsigned int mtrr[32]; /* 0x80 - 0xFC MTRR registers */ - volatile unsigned int reserved_100[131008]; /* 0x100 Reserved */ - volatile unsigned int diag_iface_tag[16384]; /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */ - volatile unsigned int reserved_90000[376832]; /* 0x90000 Reserved */ - volatile unsigned int diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */ -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grpci.h b/c/src/lib/libbsp/sparc/shared/include/grpci.h deleted file mode 100644 index 2321706200..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grpci.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __GRPCI_H__ -#define __GRPCI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Register the GRPCI driver to the Driver Manager */ -extern void grpci_register_drv(void); - -/* Transfer data using GRPCI DMA unit from AMBA to PCI space. Blocks until - * operation completes. - */ -int grpci_dma_to_pci( - unsigned int ahb_addr, - unsigned int pci_addr, - unsigned int len); - -/* Transfer data using GRPCI DMA unit from PCI to AMBA space. Blocks until - * operation completes. - */ -int grpci_dma_from_pci( - unsigned int ahb_addr, - unsigned int pci_addr, - unsigned int len); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grpci2.h b/c/src/lib/libbsp/sparc/shared/include/grpci2.h deleted file mode 100644 index c356b5641f..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grpci2.h +++ /dev/null @@ -1,65 +0,0 @@ -/* GRLIB GRPCI2 PCI HOST driver. - * - * COPYRIGHT (c) 2011 - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRPCI2_H__ -#define __GRPCI2_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -extern void grpci2_register_drv(void); - -/* Driver Resources: - * - * PCI Interrupts - * ============== - * The interrupt settings are normally autodetected from Plyg&Play, however - * if IRQs are routed using custom GPIO pins in order to reduce the PIN count - * reserved for PCI, the options below can be used to tell GRPCI2 driver which - * System IRQ a PCI interrupt is connected to. - * Name="INTA#", Type=INT, System Interrupt number that PCI INTA is connected to - * Name="INTB#", Type=INT, System Interrupt number that PCI INTB is connected to - * Name="INTC#", Type=INT, System Interrupt number that PCI INTC is connected to - * Name="INTD#", Type=INT, System Interrupt number that PCI INTD is connected to - * - * Name="IRQmask", Type=INT, - * - * PCI Bytetwisting (endianess) - * ============================ - * Name="byteTwisting", Type=INT, Enable/Disable Bytetwisting by hardware - * - * PCI Latency timer - * ============================ - * Name="latencyTimer", Type=INT, Set the latency timer - * - * PCI Host's Target BARs setup - * ============================ - * The Host's BARs are not configured by the configuration routines, by default - * the BARs are configured disabled (BAR=0) except for BAR0 which is mapped to - * the Main Memory for the Host. - * Name="tgtBarCfg", Type=PTR (*grpci2_pcibar_cfg), Target PCI BARs of Host - */ - -/* When the Host acts as a target on the PCI bus, the PCI BARs of the host's - * configuration space determine at which PCI address the Host will be accessed - * at and when accessing a BAR which AMBA address it will be translated to. - */ -struct grpci2_pcibar_cfg { - unsigned int pciadr; /* PCI address of BAR (BAR content) */ - unsigned int ahbadr; /* 'pciadr' translated to this AHB Address */ - unsigned int barsize; /* PCI BAR Size, must be a power of 2 */ -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grpci2dma.h b/c/src/lib/libbsp/sparc/shared/include/grpci2dma.h deleted file mode 100644 index c1a2663a86..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grpci2dma.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * GRPCI2 DMA Driver - * - * COPYRIGHT (c) 2017 - * Cobham Gaisler AB - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * OVERVIEW - * ======== - * This driver controls the DMA on the GRPCI2 device, located - * at an on-chip AMBA. - */ - -#ifndef __GRPCI2DMA_H__ -#define __GRPCI2DMA_H__ - -#include <stdint.h> -#include <stdio.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Error return codes */ -#define GRPCI2DMA_ERR_OK 0 -#define GRPCI2DMA_ERR_WRONGPTR -1 -#define GRPCI2DMA_ERR_NOINIT -2 -#define GRPCI2DMA_ERR_TOOMANY -3 -#define GRPCI2DMA_ERR_ERROR -4 -#define GRPCI2DMA_ERR_STOPDMA -5 -#define GRPCI2DMA_ERR_NOTFOUND -6 - -/* Size of a dma descriptors */ -#define GRPCI2DMA_BD_CHAN_SIZE 0x10 -#define GRPCI2DMA_BD_DATA_SIZE 0x10 - -/* Alignment of dma descriptors */ -#define GRPCI2DMA_BD_CHAN_ALIGN 0x10 -#define GRPCI2DMA_BD_DATA_ALIGN 0x10 - -/* User-helper functions to allocate/deallocate - * channel and data descriptors - */ -extern void * grpci2dma_channel_new(int number); -extern void grpci2dma_channel_delete(void * chanbd); -extern void * grpci2dma_data_new(int number); -extern void grpci2dma_data_delete(void * databd); - -/* Function: - * -grpci2dma_prepare - * Description: - * -Prepare a transfer, initializing the required data descriptors - * Parameters: - * -pci_start: Where in PCI/remote starts the transfer - * -ahb_start: Where in AHB/local starts the transfer - * -dir: Direction of the transfer (AHBTOPCI or PCITOAHB) - * -endianness: Endianness of the transfer (LITTLEENDIAN or BIGENDIAN) - * -size: Size in bytes of the transfer (the function will calculate if there - * are enough descriptors) - * -databd: Pointer to the data descriptor buffer - * -bdindex: Where in the buffer to start the transfer - * -bdmax: Maximum index for the data descriptor buffer - * -block_size: Size in bytes for each PCI transaction (or block). Guaranteed - * to be at least smaller that this value. Put 0 to use default. - * Default is maximum, which is 0x10000*4 bytes. - * Returns: - * -WRONGPTR: Wrong input parameters - * -TOOMANY: Not enough data descriptors in the buffer - * -value > 0: A positive return value means the number of data descriptors - * prepared/used in the buffer, starting from index. - */ -#define GRPCI2DMA_AHBTOPCI 1 -#define GRPCI2DMA_PCITOAHB 0 -#define GRPCI2DMA_LITTLEENDIAN 1 -#define GRPCI2DMA_BIGENDIAN 0 -extern int grpci2dma_prepare( - uint32_t pci_start, uint32_t ahb_start, int dir, int endianness, - int size, void * databd, int bdindex, int bdmax, int block_size); - -/* Function: - * -grpci2dma_status - * Description: - * -Status of an transfer: - * Parameters: - * -databd: Pointer to the data descriptor buffer - * -bdindex: Where in the buffer starts the transfer - * -bdsize: Number of descriptors used by the transfer - * Returns: - * -WRONGPTR: Wrong input parameters - * -GRPCI2DMA_BD_DATA_STATUS_ERR: If at least one of the descriptors has an - * error - * -GRPCI2DMA_BD_DATA_STATUS_ENABLED: If at least one of the descriptors is - * enabled, which means that the transfer is still not finished. - * -GRPCI2DMA_BD_DATA_STATUS_DISABLED: If all the descriptors are disabled, - * which means that either the transfer finished or it was never prepared. - */ -#define GRPCI2DMA_BD_STATUS_DISABLED 0 -#define GRPCI2DMA_BD_STATUS_ENABLED 1 -#define GRPCI2DMA_BD_STATUS_ERR 2 -extern int grpci2dma_status(void *databd, int bdindex, int bdsize); - -/* Function Interrupt-Code ISR callback prototype. - * arg - Custom arg provided by user - * cid - Channel ID that got the interrupt - * status - Error status of the DMA core - */ -typedef void (*grpci2dma_isr_t)(void *arg, int cid, unsigned int status); - -/* Function: - * -grpci2dma_isr_register - * Description: - * -Register an ISR for a channel (and enable interrupts if disabled) - * Parameters: - * -chan_no: ID of the channel - * -dmaisr: ISR - * -arg: Argument to pass to the ISR when called - * Returns: - * -NOINIT: GRPCI2 DMA not initialized - * -WRONGPTR: Wrong input parameters - * -OK (=0): Done - */ -extern int grpci2dma_isr_register( - int chan_no, grpci2dma_isr_t dmaisr, void *arg); - -/* Function: - * -grpci2dma_isr_unregister - * Description: - * -Unregister an ISR for a channel (and enable interrupts if disabled) - * Parameters: - * -chan_no: ID of the channel - * Returns: - * -NOINIT: GRPCI2 DMA not initialized - * -WRONGPTR: Wrong input parameters - * -OK (=0): Done - */ -extern int grpci2dma_isr_unregister(int chan_no); - -/* Function: - * -grpci2dma_open - * Description: - * -Open a channel (and allocate the descriptor if the user does not provide - * one). - * Parameters: - * -chan: Descriptor for the channel (must be aligned to 0x10) - * Returns: - * -NOINIT: GRPCI2 DMA not initialized - * -TOOMANY: Maximum number of channels already opened. - * -WRONGPTR: Wrong input parameters - * -ERROR: Inconsistent state found in driver - * -value > 0: A positive return value means the id for the channel. - */ -extern int grpci2dma_open(void * chan); - -/* Function: - * -grpci2dma_close - * Description: - * -Stop and close a channel (and deallocate it if the user did not provide a - * pointer when opening it) - * Parameters: - * -chan_no: Id of the channel - * Returns: - * -NOINIT: GRPCI2 DMA not initialized - * -NOTFOUND: Channel not opened. - * -STOPDMA: Cannot stop channel. - * -WRONGPTR: Wrong input parameters - * -OK (=0): Done. - */ -extern int grpci2dma_close(int chan_no); - -/* Function: - * -grpci2dma_start - * Description: - * -Start a channel - * Parameters: - * -chan_no: Id of the channel - * -options: Maximum number of data descriptors to be executed before moving - * to next channel (up to 0x10000) - * Returns: - * -NOINIT: GRPCI2 DMA not initialized - * -WRONGPTR: Wrong input parameters - * -ERROR: Inconsistent state found in driver - * -OK (=0): Done. - */ -extern int grpci2dma_start(int chan_no, int options); - -/* Function: - * -grpci2dma_stop - * Description: - * -Start a channel - * Parameters: - * -chan_no: Id of the channel - * Returns: - * -NOINIT: GRPCI2 DMA not initialized - * -WRONGPTR: Wrong input parameters - * -ERROR: Inconsistent state found in driver - * -OK (=0): Done. - */ -extern int grpci2dma_stop(int chan_no); - -/* Function: - * -grpci2dma_push - * Description: - * -Push a transfer into a channel (already started or not) - * Parameters: - * -chan_no: Id of the channel - * -databd: Pointer to the data descriptor buffer - * -bdindex: Where in the buffer starts the transfer - * -bdsize: Number of descriptors used by the transfer - * Returns: - * -NOINIT: GRPCI2 DMA not initialized - * -WRONGPTR: Wrong input parameters - * -NOTFOUND: Channel not opened. - * -OK (=0): Done. - */ -extern int grpci2dma_push(int chan_no, void *databd, int bdindex, int bdsize); - -/* Function: - * -grpci2dma_active - * Description: - * -Check if dma is active - * Parameters: - * Returns: - * -(!=0): Active. - * -(=0): Not active. - */ -extern int grpci2dma_active(void); - -/* Function: - * -grpci2dma_interrupt_enable - * Description: - * -Enable interrupt for a transfer - * Parameters: - * -databd: Pointer to the data descriptor buffer - * -bdindex: Where in the buffer starts the transfer - * -bdmax: Upper limit for index. index < bdmax - * -options: - * (=GRPCI2DMA_OPTIONS_ALL)=Enable interrupt on all transfer descriptors. - * (=GRPCI2DMA_OPTIONS_ONE)=Enable interrupt on transfer descriptor - * indicated by bdindex. - * Returns: - * -NOINIT: GRPCI2 DMA not initialized - * -WRONGPTR: Wrong input parameters - * -ERROR: Inconsistent state found in driver - * -OK (=0): Done. - */ -#define GRPCI2DMA_OPTIONS_ALL 1 -#define GRPCI2DMA_OPTIONS_ONE 0 -extern int grpci2dma_interrupt_enable( - void *databd, int bdindex, int bdmax, int options); - -/* Debug function: print dma channel and associated data descriptors. - * Only prints if driver internal DEBUG flag is defined. */ -extern int grpci2dma_print(int chan_no); -extern int grpci2dma_print_bd(void * data); - -#ifdef __cplusplus -} -#endif - -#endif /* __GRPCI2DMA_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/grpwm.h b/c/src/lib/libbsp/sparc/shared/include/grpwm.h deleted file mode 100644 index 6898f8ac2e..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grpwm.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * GRPWM PWM Driver interface. - * - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRPWM_H__ -#define __GRPWM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -extern void grpwm_register_drv (void); - -#define GRPWM_IOCTL_GET_CAP 1 /* Get Capabilities */ -#define GRPWM_IOCTL_SET_CONFIG 2 /* Configure one PWM Channel */ -#define GRPWM_IOCTL_SET_SCALER 3 /* Set one scaler */ -#define GRPWM_IOCTL_UPDATE 4 /* Set current period and compare value */ -#define GRPWM_IOCTL_IRQ 5 /* Set up IRQ handling */ - -/*** Argument for GRPWM_IOCTL_GET_CAP ***/ - -/* The Capability of the PWM core */ -struct grpwm_ioctl_cap { - int channel_cnt; /* Number of channels */ - unsigned int pwm; /* Capability1 register */ - unsigned int wave; /* Capability2 register, Wave form capabilities of last PWM channel, otherwise 0 */ -}; - -/*** Argument for GRPWM_IOCTL_GET_CONFIG and GRPWM_IOCTL_SET_CONFIG ***/ - -/* Config One PWM */ -struct grpwm_ioctl_config { - unsigned int channel; /* Select channel to configure */ - - /* Specific for one PWM channel */ - unsigned int options; /* PWM options */ - unsigned char dbscaler; /* value greater than 15 disable Dead band */ - unsigned char scaler_index; /* Select scaler used by PWM channel */ - - /* IRQ Setup */ - unsigned char irqscaler; /* IRQ scaler */ - void *isr_arg; /* Argument of IRQ handler */ - void (*isr)(int channel, void *arg); /* Interrupt service routine for this PWM Channel */ - - /* Waveform set up */ - int wave_activate; /* Enables Waveform functionality */ - unsigned int wave_synccfg; /* Bits [29,30,31] is written into Wave-Config register */ - unsigned int wave_sync; /* Sets sync compare register */ - unsigned int *wave_data; /* If not NULL, the Wave RAM is filled with data */ - unsigned int wave_data_length; /* Length of Wave RAM Data, Also used for wstopaddr */ -}; - -#define GRPWM_CONFIG_OPTION_FLIP 0x04000000 /* Set this to Flip PWM output pair */ -#define GRPWM_CONFIG_OPTION_DEAD_BAND 0x00200000 /* Dead Band enable */ -#define GRPWM_CONFIG_OPTION_SYMMETRIC 0x00000040 /* If not defined, asymmetric */ -#define GRPWM_CONFIG_OPTION_ASYMMERTIC 0 -#define GRPWM_CONFIG_OPTION_DUAL 0x00000020 /* Dual Compare Enable */ -#define GRPWM_CONFIG_OPTION_PAIR 0x00000004 /* PWM Pair Enable */ -#define GRPWM_CONFIG_OPTION_SINGLE 0x00000000 /* PWM Pair Disable */ -#define GRPWM_CONFIG_OPTION_POLARITY_HIGH 0x00000002 /* PWM Polarity HIGH */ -#define GRPWM_CONFIG_OPTION_POLARITY_LOW 0x00000000 /* PWM Polarity LOW */ - -#define GRPWM_CONFIG_OPTION_MASK ( \ - GRPWM_CONFIG_OPTION_DEAD_BAND | GRPWM_CONFIG_OPTION_SYMMETRIC | \ - GRPWM_CONFIG_OPTION_DUAL | GRPWM_CONFIG_OPTION_PAIR | \ - GRPWM_CONFIG_OPTION_POLARITY_HIGH \ - ) - -/*** Argument for GPPWM_IOCTL_SET_SCALER ***/ - -struct grpwm_ioctl_scaler { - unsigned int index_mask;/* Scaler update index mask, bit 0 = Scaler 0, bit 1 = Scaler 1 */ - unsigned int values[8]; /* Scaler update values, values[N] is stored into scaler N, if mask & 1<<N is set */ -}; - -/*** Argument for GRPWM_IOCTL_UPDATE ***/ - -#define GRPWM_UPDATE_OPTION_ENABLE 0x01 /* Enable the PWM core */ -#define GRPWM_UPDATE_OPTION_DISABLE 0x02 /* Disable the PWM core */ -#define GRPWM_UPDATE_OPTION_PERIOD 0x04 /* Update period register */ -#define GRPWM_UPDATE_OPTION_COMP 0x08 /* Update Compare register */ -#define GRPWM_UPDATE_OPTION_DBCOMP 0x10 /* Update Dead band register */ -#define GRPWM_UPDATE_OPTION_FIX 0x20 /* Update fix output pins (bypass PWM) */ - -/* FIX PIN bit-mask */ -#define GRPWM_UPDATE_FIX_ENABLE 1 /* Enable force ouput */ -#define GRPWM_UPDATE_FIX_DISABLE 0 /* Disable force ouput */ -#define GRPWM_UPDATE_FIX_0_LOW 0 /* PIN 0 OUPUT: LOW */ -#define GRPWM_UPDATE_FIX_0_HIGH 2 /* PIN 0 OUPUT: HIGH */ -#define GRPWM_UPDATE_FIX_1_LOW 0 /* PIN 1 OUPUT: LOW */ -#define GRPWM_UPDATE_FIX_1_HIGH 4 /* PIN 1 OUPUT: HIGH */ - -struct grpwm_ioctl_update_chan { - unsigned int options; /* Select what is updated */ - unsigned int period; /* Period register content */ - unsigned int compare; /* Compare register content */ - unsigned int dbcomp; /* Dead band register content */ - unsigned char fix; /* Bit-mask that select output on one or two PWM - * output pins. Depends on PAIR config value. - */ -}; -struct grpwm_ioctl_update { - unsigned char chanmask; /* Bit Mask select channels */ - struct grpwm_ioctl_update_chan channels[8]; /* */ -}; - -/*** Argument for GPPWM_IOCTL_IRQ ***/ - -#define GRPWM_IRQ_DISABLE 0 /* Disable IRQ */ -#define GRPWM_IRQ_PERIOD 1 /* Enable IRQ on period match */ -#define GRPWM_IRQ_COMPARE 3 /* Enable IRQ on Compare Match */ -#define GRPWM_IRQ_CLEAR 0x10 /* Clear any pending IRQ on GRPWM and IRQ controller */ - -#define GRPWM_IRQ_CHAN 0x100 /* Channel N is selected, by adding 0x100*N */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grslink.h b/c/src/lib/libbsp/sparc/shared/include/grslink.h deleted file mode 100644 index 575a24aee4..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grslink.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Header file for RTEMS GRSLINK SLINK master driver - * - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRSLINK_H__ -#define __GRSLINK_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/**** Configuration ****/ -/* Collect statistics ? */ -#define SLINK_COLLECT_STATISTICS - -/* Frequency of SLINK SCLK */ -#define SLINK_FREQ_HZ 6000000 -/* Number of queues used in driver */ -#define SLINK_NUMQUEUES 4 - -/* The four values below are only used in the demo software */ -#define SLINK_CORE_REGBASE 0x80000600 -#define SLINK_CORE_IRQ 6 -#define IRQ_CNTRL_REG 0x80000200 -#define IRQ_CNTRL_MASK_OFFSET 0x40 - -/* - * Structure returned by SLINK_statistics if SLINK_COLLECT_STATISTCS has - * been defined - */ -typedef struct { - unsigned int parerr; /* Number of parity errors */ - unsigned int recov; /* Number of receive overflows */ - unsigned int reads; /* Number of completed READs */ - unsigned int writes; /* Number of performed WRITES */ - unsigned int sequences; /* Number of started SEQUENCEs */ - unsigned int seqcomp; /* Number of completed SEQUENCEs */ - unsigned int interrupts; /* Number of INTERRUPT transfers */ - unsigned int lostwords; /* Number of lost words due to full queue */ -} SLINK_stats; - -/**** SLINK status codes ****/ -#define SLINK_ABORTED 0 -#define SLINK_QFULL 1 -#define SLINK_ACTIVE 2 -#define SLINK_AMBAERR 3 -#define SLINK_COMPLETED 4 -#define SLINK_PARERR 5 -#define SLINK_ROV 6 /* Only used internally in driver */ - -/**** SLINK master register fields *****/ -/* Control register */ -#define SLINK_C_SLEN_POS 16 -#define SLINK_C_SRO (1 << 8) -#define SLINK_C_SCN_POS 4 -#define SLINK_C_PAR (1 << 3) -#define SLINK_C_AS (1 << 2) -#define SLINK_C_SE (1 << 1) -#define SLINK_C_SLE (1 << 0) - -/* Status register fields */ -#define SLINK_S_SI_POS 16 -#define SLINK_S_PERR (1 << 7) -#define SLINK_S_AERR (1 << 6) -#define SLINK_S_ROV (1 << 5) -#define SLINK_S_RNE (1 << 4) -#define SLINK_S_TNF (1 << 3) -#define SLINK_S_SC (1 << 2) -#define SLINK_S_SA (1 << 1) -#define SLINK_S_SRX (1 << 0) - -/* Mask register fields */ -#define SLINK_M_PERRE (1 << 7) -#define SLINK_M_AERRE (1 << 6) -#define SLINK_M_ROVE (1 << 5) -#define SLINK_M_RNEE (1 << 4) -#define SLINK_M_TNFE (1 << 3) -#define SLINK_M_SCE (1 << 2) -#define SLINK_M_SAE (1 << 1) -#define SLINK_M_SRXE (1 << 0) - -/**** Macros ****/ -/* Get channel field from received SLINK word */ -#define SLINK_WRD_CHAN(x) ((x >> 16) & 0xF) -/* Get IO card # from received SLINK word */ -#define SLINK_WRD_CARDNUM(x) ((x >> 21) & 0x3) -/* Get data part from SLINK word */ -#define SLINK_WRD_PAYLOAD(x) (x & 0xFFFF) - -/* Checks status value to see if transmit queue has free slot */ -#define SLINK_STS_TRANSFREE(x) (x & SLINK_S_TNF) -/* Get Sequence Index value */ -#define SLINK_STS_SI(x) ((x >> 16) & 0xFF) - -/**** Function declarations, driver interface ****/ -/* Initializes the SLINK core */ -int SLINK_init(unsigned int nullwrd, int parity, int qsize, - void (*interrupt_trans_handler)(int), - void (*sequence_callback)(int)); - -/* Enables the core */ -void SLINK_start(void); - -/* Disables the core */ -void SLINK_stop(void); - -/* Reads one word */ -int SLINK_read(int data, int channel, int *reply); - -/* Writes one word */ -int SLINK_write(int data, int channel); - -/* Peforms a SEQUENCE */ -int SLINK_seqstart(int *a, int *b, int n, int channel, int reconly); - -/* Aborts a SEQUENCE */ -void SLINK_seqabort(void); - -/* Status of current or last SEQUENCE */ -int SLINK_seqstatus(void); - -/* Number of words transferred in last SEQUENCE */ -int SLINK_seqwrds(void); - -/* Returns value of core's status register */ -int SLINK_hwstatus(void); - -/* Returns number of elements in queue associated with IO card */ -int SLINK_queuestatus(int iocard); - -/* Take first element from queue for IO card # 'iocard' */ -int SLINK_dequeue(int iocard, int *elem); - -/* Returns structure containing core driver statistics */ -SLINK_stats *SLINK_statistics(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __GRSLINK_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/grspw.h b/c/src/lib/libbsp/sparc/shared/include/grspw.h deleted file mode 100644 index 3270e8a5a2..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grspw.h +++ /dev/null @@ -1,168 +0,0 @@ -/** - * @file - * @ingroup sparc_bsp - * @defgroup spw SpaceWire - * @ingroup spw - * @brief GRSPW Device Driver - */ - -/* - * COPYRIGHT (c) 2007. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRSPW_H__ -#define __GRSPW_H__ - -#include <ambapp.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define SPW_LINKERR_EVENT RTEMS_EVENT_0 - -typedef struct { - unsigned int rxsize; - unsigned int txdsize; - unsigned int txhsize; -} spw_ioctl_packetsize; - -#define GRSPW_PKTSEND_OPTION_HDR_CRC 0x1 -#define GRSPW_PKTSEND_OPTION_DATA_CRC 0x2 -#define GRSPW_PKTSEND_OPTION_NOCRCLEN(len) ((len & 0xf) << 8) -#define GRSPW_PKTSEND_OPTION_NOCRCLEN_MASK 0xf00 - -typedef struct { - unsigned int hlen; - char *hdr; - unsigned int dlen; - char *data; - unsigned int sent; - unsigned int options; -} spw_ioctl_pkt_send; - -typedef struct { - unsigned int tx_link_err; - unsigned int rx_rmap_header_crc_err; - unsigned int rx_rmap_data_crc_err; - unsigned int rx_eep_err; - unsigned int rx_truncated; - unsigned int parity_err; - unsigned int escape_err; - unsigned int credit_err; - unsigned int write_sync_err; - unsigned int disconnect_err; - unsigned int early_ep; - unsigned int invalid_address; - unsigned int packets_sent; - unsigned int packets_received; -} spw_stats; - -typedef struct { - unsigned int nodeaddr; - unsigned int destkey; - unsigned int clkdiv; /* Note: contain both CLKDIVSTART and CLKDIVRUN, but IOCTL_SET_CLKDIV* commands are split into two */ - unsigned int rxmaxlen; - unsigned int timer; - unsigned int disconnect; - unsigned int promiscuous; - unsigned int rmapen; - unsigned int rmapbufdis; - unsigned int linkdisabled; - unsigned int linkstart; - - unsigned int check_rmap_err; /* check incoming packets for rmap errors */ - unsigned int rm_prot_id; /* remove protocol id from incoming packets */ - unsigned int tx_blocking; /* use blocking tx */ - unsigned int tx_block_on_full; /* block when all tx_buffers are used */ - unsigned int rx_blocking; /* block when no data is available */ - unsigned int disable_err; /* disable link automatically when link error is detected */ - unsigned int link_err_irq; /* generate an interrupt when link error occurs */ - rtems_id event_id; /* task id that should receive link err irq event */ - - unsigned int is_rmap; - unsigned int is_rxunaligned; - unsigned int is_rmapcrc; - - unsigned int nodemask; - unsigned int keep_source; /* copy source address to user-buffer in read() operations - * Note that rm_prot_id has no effect when keep_source is - * set. - */ - unsigned int rtimeout; /* Read timeout if != 0 */ -} spw_config; - -#define SPACEWIRE_IOCTRL_SET_NODEADDR 1 -#define SPACEWIRE_IOCTRL_SET_RXBLOCK 2 -#define SPACEWIRE_IOCTRL_SET_DESTKEY 4 -#define SPACEWIRE_IOCTRL_SET_CLKDIV 5 -#define SPACEWIRE_IOCTRL_SET_TIMER 6 -#define SPACEWIRE_IOCTRL_SET_DISCONNECT 7 -#define SPACEWIRE_IOCTRL_SET_PROMISCUOUS 8 -#define SPACEWIRE_IOCTRL_SET_RMAPEN 9 -#define SPACEWIRE_IOCTRL_SET_RMAPBUFDIS 10 -#define SPACEWIRE_IOCTRL_SET_CHECK_RMAP 11 -#define SPACEWIRE_IOCTRL_SET_RM_PROT_ID 12 -#define SPACEWIRE_IOCTRL_SET_TXBLOCK 14 -#define SPACEWIRE_IOCTRL_SET_DISABLE_ERR 15 -#define SPACEWIRE_IOCTRL_SET_LINK_ERR_IRQ 16 -#define SPACEWIRE_IOCTRL_SET_EVENT_ID 17 -#define SPACEWIRE_IOCTRL_SET_PACKETSIZE 20 -#define SPACEWIRE_IOCTRL_GET_LINK_STATUS 23 -#define SPACEWIRE_IOCTRL_GET_CONFIG 25 -#define SPACEWIRE_IOCTRL_GET_STATISTICS 26 -#define SPACEWIRE_IOCTRL_CLR_STATISTICS 27 -#define SPACEWIRE_IOCTRL_SEND 28 -#define SPACEWIRE_IOCTRL_LINKDISABLE 29 -#define SPACEWIRE_IOCTRL_LINKSTART 30 -#define SPACEWIRE_IOCTRL_SET_TXBLOCK_ON_FULL 31 -#define SPACEWIRE_IOCTRL_SET_COREFREQ 32 -#define SPACEWIRE_IOCTRL_SET_CLKDIVSTART 33 -#define SPACEWIRE_IOCTRL_SET_NODEMASK 34 -#define SPACEWIRE_IOCTRL_SET_KEEP_SOURCE 35 -#define SPACEWIRE_IOCTRL_SET_TCODE_CTRL 36 -#define SPACEWIRE_IOCTRL_SET_TCODE 37 -#define SPACEWIRE_IOCTRL_GET_TCODE 38 -#define SPACEWIRE_IOCTRL_SET_READ_TIMEOUT 39 - -#define SPACEWIRE_IOCTRL_START 64 -#define SPACEWIRE_IOCTRL_STOP 65 - -/* Defines what register bits that will be touched - * for SPACEWIRE_IOCTRL_SET_TCODE_CTRL - */ -#define SPACEWIRE_TCODE_CTRL_IE_MSK 0x001 -#define SPACEWIRE_TCODE_CTRL_TT_MSK 0x004 -#define SPACEWIRE_TCODE_CTRL_TR_MSK 0x008 - -/* Defines what register bits that should be set - * for SPACEWIRE_IOCTRL_SET_TCODE_CTRL - */ -#define SPACEWIRE_TCODE_CTRL_IE 0x100 -#define SPACEWIRE_TCODE_CTRL_TT 0x400 -#define SPACEWIRE_TCODE_CTRL_TR 0x800 - -/* SPACEWIRE_IOCTRL_SET_TCODE argument mask */ -#define SPACEWIRE_TCODE_TCODE 0x0ff -#define SPACEWIRE_TCODE_SET 0x100 /* Set Timecode register */ -#define SPACEWIRE_TCODE_TX 0x400 - -void grspw_register_drv (void); - -void grspw_print(int options); - -/* Global GRSPW Function pointer called upon timecode receive interrupt */ -extern void (*grspw_timecode_callback) - (void *pDev, void *regs, int minor, unsigned int tc); - - -#ifdef __cplusplus -} -#endif - -#endif /* __GRSPW_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h b/c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h deleted file mode 100644 index a74a7c9f6a..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h +++ /dev/null @@ -1,845 +0,0 @@ -/* - * GRSPW/GRSPW2 SpaceWire Kernel Library Interface - * - * COPYRIGHT (c) 2011 - * Cobham Gaisler AB - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRSPW_PKT_H__ -#define __GRSPW_PKT_H__ - -struct grspw_pkt; - -/* Maximum number of GRSPW devices supported by driver */ -#define GRSPW_MAX 32 - -/* Weak overridable variable the user can use to define the worker-task - * priority (0..255) or to disable (-1) the creation of the worker-task - * and the message queue to save space */ -extern int grspw_work_task_priority; - -#ifndef GRSPW_PKT_FLAGS -#define GRSPW_PKT_FLAGS -/*** TX Packet flags ***/ - -/* Enable IRQ generation */ -#define TXPKT_FLAG_IE 0x0040 - -/* Enable Header CRC generation (if CRC is available in HW) - * Header CRC will be appended (one byte at end of header) - */ -#define TXPKT_FLAG_HCRC 0x0100 - -/* Enable Data CRC generation (if CRC is available in HW) - * Data CRC will be appended (one byte at end of packet) - */ -#define TXPKT_FLAG_DCRC 0x0200 - -/* Control how many bytes the beginning of the Header - * the CRC should not be calculated for */ -#define TXPKT_FLAG_NOCRC_MASK 0x0000000f -#define TXPKT_FLAG_NOCRC_LEN0 0x00000000 -#define TXPKT_FLAG_NOCRC_LEN1 0x00000001 -#define TXPKT_FLAG_NOCRC_LEN2 0x00000002 -#define TXPKT_FLAG_NOCRC_LEN3 0x00000003 -#define TXPKT_FLAG_NOCRC_LEN4 0x00000004 -#define TXPKT_FLAG_NOCRC_LEN5 0x00000005 -#define TXPKT_FLAG_NOCRC_LEN6 0x00000006 -#define TXPKT_FLAG_NOCRC_LEN7 0x00000007 -#define TXPKT_FLAG_NOCRC_LEN8 0x00000008 -#define TXPKT_FLAG_NOCRC_LEN9 0x00000009 -#define TXPKT_FLAG_NOCRC_LENa 0x0000000a -#define TXPKT_FLAG_NOCRC_LENb 0x0000000b -#define TXPKT_FLAG_NOCRC_LENc 0x0000000c -#define TXPKT_FLAG_NOCRC_LENd 0x0000000d -#define TXPKT_FLAG_NOCRC_LENe 0x0000000e -#define TXPKT_FLAG_NOCRC_LENf 0x0000000f - -#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \ - TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC) - -/* Marks if packet was transmitted or not */ -#define TXPKT_FLAG_TX 0x4000 - -/* Link Error */ -#define TXPKT_FLAG_LINKERR 0x8000 - -#define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR) - -/*** RX Packet Flags ***/ - -/* Enable IRQ generation */ -#define RXPKT_FLAG_IE 0x0010 - -#define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE) - -/* Packet was truncated */ -#define RXPKT_FLAG_TRUNK 0x0800 -/* Data CRC error (only valid if RMAP CRC is enabled) */ -#define RXPKT_FLAG_DCRC 0x0400 -/* Header CRC error (only valid if RMAP CRC is enabled) */ -#define RXPKT_FLAG_HCRC 0x0200 -/* Error in End-of-Packet */ -#define RXPKT_FLAG_EEOP 0x0100 -/* Marks if packet was recevied or not */ -#define RXPKT_FLAG_RX 0x8000 - -#define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \ - RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP) - -/*** General packet flag options ***/ - -/* Translate Hdr and/or Payload address */ -#define PKT_FLAG_TR_DATA 0x1000 -#define PKT_FLAG_TR_HDR 0x2000 -/* All General options */ -#define PKT_FLAG_MASK 0x3000 - -#endif -/* GRSPW RX/TX Packet structure. - * - * - For RX the 'hdr' and 'hlen' fields are not used, they are not written - * by driver. - * - * - The 'pkt_id' field is untouched by driver, it is intended for packet - * numbering or user-custom data. - * - * - The last packet in a list must have 'next' set to NULL. - * - * - data and hdr pointers are written without modification to hardware, - * this means that caller must do address translation to hardware - * address itself. - * - * - the 'flags' field are interpreted differently depending on transfer - * type (RX/TX). See XXPKT_FLAG_* options above. - */ -struct grspw_pkt { - struct grspw_pkt *next; /* Next packet in list. NULL if last packet */ - unsigned int pkt_id; /* User assigned ID (not touched by driver) */ - unsigned short flags; /* RX/TX Options and status */ - unsigned char reserved; /* Reserved, must be zero */ - unsigned char hlen; /* Length of Header Buffer (only TX) */ - unsigned int dlen; /* Length of Data Buffer */ - void *data; /* 4-byte or byte aligned depends on HW */ - void *hdr; /* 4-byte or byte aligned depends on HW (only TX) */ -}; - -/* GRSPW SpaceWire Packet List */ -struct grspw_list { - struct grspw_pkt *head; - struct grspw_pkt *tail; -}; - -/* SpaceWire Link State */ -typedef enum { - SPW_LS_ERRRST = 0, - SPW_LS_ERRWAIT = 1, - SPW_LS_READY = 2, - SPW_LS_CONNECTING = 3, - SPW_LS_STARTED = 4, - SPW_LS_RUN = 5 -} spw_link_state_t; - -/* Address Configuration */ -struct grspw_addr_config { - /* Ignore address field and put all received packets to first - * DMA channel. - */ - int promiscuous; - - /* Default Node Address and Mask */ - unsigned char def_addr; - unsigned char def_mask; - /* DMA Channel custom Node Address and Mask */ - struct { - char node_en; /* Enable Separate Addr */ - unsigned char node_addr; /* Node address */ - unsigned char node_mask; /* Node address mask */ - } dma_nacfg[4]; -}; - -/* Hardware Support in GRSPW Core */ -struct grspw_hw_sup { - char rmap; /* If RMAP in HW is available */ - char rmap_crc; /* If RMAP CRC is available */ - char rx_unalign; /* RX unaligned (byte boundary) access allowed*/ - char nports; /* Number of Ports (1 or 2) */ - char ndma_chans; /* Number of DMA Channels (1..4) */ - char strip_adr; /* Hardware can strip ADR from packet data */ - char strip_pid; /* Hardware can strip PID from packet data */ - int hw_version; /* GRSPW Hardware Version */ - char reserved[2]; - char irq; /* SpW Distributed Interrupt available if 1 */ - char irq_num; /* Number of interrupts that can be generated */ - char itmr_width; /* SpW Intr. ISR timers bit width. 0=no timer */ -}; - -struct grspw_core_stats { - int irq_cnt; - int err_credit; - int err_eeop; - int err_addr; - int err_parity; - int err_disconnect; - int err_escape; - int err_wsync; /* only in GRSPW1 */ -}; - -/* grspw_link_ctrl() options */ -#define LINKOPTS_ENABLE 0x0000 -#define LINKOPTS_DISABLE 0x0001 -#define LINKOPTS_START 0x0002 -#define LINKOPTS_AUTOSTART 0x0004 -#define LINKOPTS_DIS_ONERR 0x0008 /* Disable DMA transmitter on link error - * Controls LE bit in DMACTRL register. - */ -#define LINKOPTS_DIS_ON_CE 0x0020000/* Disable Link on Credit error */ -#define LINKOPTS_DIS_ON_ER 0x0040000/* Disable Link on Escape error */ -#define LINKOPTS_DIS_ON_DE 0x0080000/* Disable Link on Disconnect error */ -#define LINKOPTS_DIS_ON_PE 0x0100000/* Disable Link on Parity error */ -#define LINKOPTS_DIS_ON_WE 0x0400000/* Disable Link on write synchonization - * error (GRSPW1 only) - */ -#define LINKOPTS_DIS_ON_EE 0x1000000/* Disable Link on Early EOP/EEP error*/ - -/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */ -#define LINKOPTS_EIRQ 0x0200 /* Enable Error Link IRQ */ - -#define LINKOPTS_MASK 0x15e020f/* All above options */ -#define LINKOPTS_MASK_DIS_ON 0x15e0000/* All disable link on error options - * On a certain error the link disable - * bit will be written and the work - * task will call dma_stop() for all - * channels. - */ - -#define LINKSTS_CE 0x002 /* Credit error */ -#define LINKSTS_ER 0x004 /* Escape error */ -#define LINKSTS_DE 0x008 /* Disconnect error */ -#define LINKSTS_PE 0x010 /* Parity error */ -#define LINKSTS_WE 0x040 /* Write synchonization error (GRSPW1 only) */ -#define LINKSTS_IA 0x080 /* Invalid address */ -#define LINKSTS_EE 0x100 /* Early EOP/EEP */ -#define LINKSTS_MASK 0x1de - -/* grspw_tc_ctrl() options */ -#define TCOPTS_EN_RXIRQ 0x0001 /* Tick-Out IRQ */ -#define TCOPTS_EN_TX 0x0004 -#define TCOPTS_EN_RX 0x0008 - -/* grspw_ic_ctrl() options: - * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines - */ -#define ICOPTS_INTNUM (0x1f << 27) -#define ICOPTS_EN_SPWIRQ_ON_EE (1 << 24) -#define ICOPTS_EN_SPWIRQ_ON_IA (1 << 23) -#define ICOPTS_EN_PRIO (1 << 22) -#define ICOPTS_EN_TIMEOUTIRQ (1 << 20) -#define ICOPTS_EN_ACKIRQ (1 << 19) -#define ICOPTS_EN_TICKOUTIRQ (1 << 18) -#define ICOPTS_EN_RX (1 << 17) -#define ICOPTS_EN_TX (1 << 16) -#define ICOPTS_BASEIRQ (0x1f << 8) -#define ICOPTS_EN_FLAGFILTER (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */ - -/* grspw_ic_rlisr() and grspw_ic_rlintack() */ -#define ICRELOAD_EN (1 << 31) -#define ICRELOAD_MASK 0x7fffffff - -/* grspw_rmap_ctrl() options */ -#define RMAPOPTS_EN_RMAP 0x0001 -#define RMAPOPTS_EN_BUF 0x0002 - -/* grspw_dma_config.flags options */ -#define DMAFLAG_NO_SPILL 0x0001 /* See HW doc DMA-CTRL NS bit */ -#define DMAFLAG_RESV1 0x0002 /* HAS NO EFFECT */ -#define DMAFLAG_STRIP_ADR 0x0004 /* See HW doc DMA-CTRL SA bit */ -#define DMAFLAG_STRIP_PID 0x0008 /* See HW doc DMA-CTRL SP bit */ -#define DMAFLAG_RESV2 0x0010 /* HAS NO EFFECT */ -#define DMAFLAG_MASK (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID) -/* grspw_dma_config.flags misc options (not shifted internally) */ -#define DMAFLAG2_TXIE 0x00100000 /* See HW doc DMA-CTRL TI bit. - * Used to enable TX DMA interrupt - * when tx_irq_en_cnt=0. - */ -#define DMAFLAG2_RXIE 0x00200000 /* See HW doc DMA-CTRL RI bit. - * Used to enable RX DMA interrupt - * when rx_irq_en_cnt=0. - */ -/* Defines how the ISR will disable RX/TX DMA interrupt source when a DMA RX/TX - * interrupt has happended. DMA Error Interrupt always disables both RX/TX DMA - * interrupt. By default both RX/TX IRQs are disabled when either a RX, TX or - * both RX/TX DMA interrupt has been requested. The work-task, custom - * application handler or custom ISR handler is responsible to re-enable - * DMA interrupts. - */ -#define DMAFLAG2_IRQD_SRC 0x01000000 /* Disable triggering RX/TX source */ -#define DMAFLAG2_IRQD_NONE 0x00c00000 /* Never disable RX/TX IRQ in ISR */ -#define DMAFLAG2_IRQD_BOTH 0x00000000 /* Always disable both RX/TX sources */ -#define DMAFLAG2_IRQD_MASK 0x01c00000 /* Mask of options */ -#define DMAFLAG2_IRQD_BIT 22 - -#define DMAFLAG2_MASK (DMAFLAG2_TXIE | DMAFLAG2_RXIE | DMAFLAG2_IRQD_MASK) - -struct grspw_dma_config { - int flags; /* DMA config flags, see DMAFLAG1&2_* options */ - int rxmaxlen; /* RX Max Packet Length */ - int rx_irq_en_cnt; /* Enable RX IRQ every cnt descriptors */ - int tx_irq_en_cnt; /* Enable TX IRQ every cnt descriptors */ -}; - -/* Statistics per DMA channel */ -struct grspw_dma_stats { - /* IRQ Statistics */ - int irq_cnt; /* Number of DMA IRQs generated by channel */ - - /* Descriptor Statistics */ - int tx_pkts; /* Number of Transmitted packets */ - int tx_err_link; /* Number of Transmitted packets with Link Error*/ - int rx_pkts; /* Number of Received packets */ - int rx_err_trunk; /* Number of Received Truncated packets */ - int rx_err_endpkt; /* Number of Received packets with bad ending */ - - /* Diagnostics to help developers sizing their number buffers to avoid - * out-of-buffers or other phenomenons. - */ - int send_cnt_min; /* Minimum number of packets in TX SEND Q */ - int send_cnt_max; /* Maximum number of packets in TX SEND Q */ - int tx_sched_cnt_min; /* Minimum number of packets in TX SCHED Q */ - int tx_sched_cnt_max; /* Maximum number of packets in TX SCHED Q */ - int sent_cnt_max; /* Maximum number of packets in TX SENT Q */ - int tx_work_cnt; /* Times the work thread processed TX BDs */ - int tx_work_enabled; /* No. RX BDs enabled by work thread */ - - int ready_cnt_min; /* Minimum number of packets in RX READY Q */ - int ready_cnt_max; /* Maximum number of packets in RX READY Q */ - int rx_sched_cnt_min; /* Minimum number of packets in RX SCHED Q */ - int rx_sched_cnt_max; /* Maximum number of packets in RX SCHED Q */ - int recv_cnt_max; /* Maximum number of packets in RX RECV Q */ - int rx_work_cnt; /* Times the work thread processed RX BDs */ - int rx_work_enabled; /* No. RX BDs enabled by work thread */ -}; - -/* ISR message sending call back. Compatible with rtems_message_queue_send(). - * The 'buf' parameter has a pointer to a WORK-TASK message defined by the - * WORK_* macros below. The message indicates what GRSPW device operations - * are pending, thus what caused the interrupt. - * - * \param data defined by grspw_work_config.msgisr_arg, default a rtems_id. - * \param buf Pointer to a 32-bit message word - * \param n Always 4 (byte size of buf). - */ -typedef int (*grspw_msgqisr_t)(void *data, unsigned int *buf, unsigned int n); - -/* Work message definitions, the int sent to *buf - * Bits 31..24: reserved. - * Bits 23..16: GRSPW device number message is associated with. - * Bit 15: reserved. - * Bit 14: work-task shall delete message queue on exit. - * Bit 13: work-task shall exit and delete itself. - * Bit 12: link error - shut down all DMA operations (stop DMA channels). - * Bit 11..8: Indicats DMA error on DMA channel 3..0. - * Bit 7..0: Indicats RX and/or TX packets completed on channel 3..0. - */ -#define WORK_NONE 0 -#define WORK_SHUTDOWN 0x1000 /* Signal shut down */ -#define WORK_QUIT_TASK 0x2000 /* Work task shall exit (delete itself) */ -#define WORK_FREE_MSGQ 0x4000 /* Delete MsgQ (valid when WORK_QUIT_TASK) */ -#define WORK_DMA(chan, rxtx) (((rxtx) & 0x3) << ((chan) * 2)) -#define WORK_DMA_TX(chan) WORK_DMA(chan, 1) -#define WORK_DMA_RX(chan) WORK_DMA(chan, 2) -#define WORK_DMA_ER(chan) (0x1 << ((chan) + 8)) -#define WORK_DMA_MASK 0xfff /* max 4 channels all work */ -#define WORK_DMA_TX_MASK 0x055 /* max 4 channels TX work */ -#define WORK_DMA_RX_MASK 0x0aa /* max 4 channels RX work */ -#define WORK_DMA_ER_MASK 0xf00 /* max 4 channels Error work */ -#define WORK_DMA_CHAN_MASK(chan) (WORK_DMA_ER(chan) | WORK_DMA(chan, 0x3)) -#define WORK_CORE_BIT 16 -#define WORK_CORE_MASK 0x00ff0000 -#define WORK_CORE(device) ((device) << WORK_CORE_BIT) - -/* Message Q used to send messages to work task */ -struct grspw_work_config { - grspw_msgqisr_t msgisr; - void *msgisr_arg; /* example: rtems_id to Msg Q */ -}; - -extern void grspw_initialize_user( - /* Callback every time a GRSPW device is found. Args: DeviceIndex */ - void *(*devfound)(int), - /* Callback every time a GRSPW device is removed. Args: - * int = DeviceIndex - * void* = Return Value from devfound() - */ - void (*devremove)(int,void*) - ); - -/* Creates a MsgQ (optional) and spawns a worker task associated with the - * message Q. The task can also be associated with a custom msgQ if *msgQ. - * is non-zero. - * - * \param prio Task priority, set to -1 for default. - * \param stack Task stack size, set to 0 for default. - * \param msgQ pMsgQ=NULL: illegal, - * pMsqQ==0: create new MsgQ with task and place in *pMsgQ, - * *pmsqQ!=0: pointer to MsgQ used for task. - * \param msgMax Maximum number of messages, set to 0 for default. - * \return 0 on failure, task id on success. - */ -extern rtems_id grspw_work_spawn(int prio, int stack, rtems_id *pMsgQ, int msgMax); - -/* Free task associated with message queue and optionally also the message - * queue itself. The message queue is deleted by the work task and is therefore - * delayed until it the work task resumes its execution. - */ -extern rtems_status_code grspw_work_free(rtems_id msgQ, int freeMsgQ); - -/* Configure a GRSPW device Work task and Message Q set up. - * This affects messages to: - * - DMA AHB error interrupt handling (mandatory) - * - Link status interrupt handling (optional) - * - RX DMA, defaults to common msgQ (configured per DMA channel) - */ -extern void grspw_work_cfg(void *d, struct grspw_work_config *wc); - -/* Work-task function, called only from the work task. The function is provided - * as a way for the user to create its own work tasks. - * The argument determines which message queue the task shall read its - * work jobs from. - * - * The messages are always 32-bit words and follows the format defined by the - * WORK_* macros above. - */ -extern void grspw_work_func(rtems_id msgQ); - -enum grspw_worktask_ev { - WORKTASK_EV_NONE = 0, - WORKTASK_EV_QUIT = 1, - WORKTASK_EV_SHUTDOWN = 2, - WORKTASK_EV_DMA_STOP = 3, -}; - -/* Weak function to let user override. Function called every time one of the - * events above is handled by the work-task. The message 'msg' is the current - * message being processed by the work-task. - * The user can for example add custom code to invoke on a DMA error, link - * error or monitor when the work-task exits after a call to grspw_work_free(). - */ -extern void grspw_work_event(enum grspw_worktask_ev ev, unsigned int msg); - -#ifdef RTEMS_SMP -/* Set ISR interrupt affinity. The LEON IRQCtrl requires that the cpumask shall - * always have one bit set. - */ -extern int grspw_isr_affinity(void *d, const cpu_set_t *cpus); -#endif - -extern int grspw_dev_count(void); -extern void *grspw_open(int dev_no); -extern int grspw_close(void *d); -extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw); -extern void grspw_stats_read(void *d, struct grspw_core_stats *sts); -extern void grspw_stats_clr(void *d); - -/* Set and Read current node address configuration. The dma_nacfg[N] field - * represents the configuration for DMA Channel N. - * - * Set cfg->promiscous to -1 in order to only read current configuration. - */ -extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg); - -/*** Link Control interface ***/ -/* Read Link State */ -extern spw_link_state_t grspw_link_state(void *d); -/* options [in/out]: set to -1 to only read current config - * - * CLKDIV register contain: - * bits 7..0 : Clock Div RUN (only run-state) - * bits 15..8 : Clock Div During Startup (all link states except run-state) - */ -extern void grspw_link_ctrl(void *d, int *options, int *stscfg, int *clkdiv); -/* Read the current value of the status register */ -extern unsigned int grspw_link_status(void *d); -/* Clear bits in the status register */ -extern void grspw_link_status_clr(void *d, unsigned int clearmask); - -/*** Time Code Interface ***/ -/* Generate Tick-In (increment Time Counter, Send Time Code) */ -extern void grspw_tc_tx(void *d); -/* Control Timcode settings of core */ -extern void grspw_tc_ctrl(void *d, int *options); -/* Assign ISR Function to TimeCode RX IRQ */ -extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data); -/* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value - * TCTRL = bits 7 and 6 - * TIMECNT = bits 5 to 0 - */ -extern void grspw_tc_time(void *d, int *time); - -/*** Interrupt-code Interface ***/ -struct spwpkt_ic_config { - unsigned int tomask; - unsigned int aamask; - unsigned int scaler; - unsigned int isr_reload; - unsigned int ack_reload; -}; -/* Function Interrupt-Code ISR callback prototype. Called when respective - * interrupt handling option has been enabled by grspw_ic_ctrl(), the - * arguments rxirq, rxack and intto are read from the registers of the - * GRSPW core read by the GRSPW ISR, they are individually valid only when - * repective handling been turned on. - * - * data - Custom data provided by user - * rxirq - Interrupt-Code Recevie register of the GRSPW core read by ISR - * (only defined if IQ bit enabled through grspw_ic_ctrl()) - * rxack - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR - * (only defined if AQ bit enabled through grspw_ic_ctrl()) - * intto - Interrupt Tick-out Recevie register of the GRSPW core read by ISR - * (only defined if TQ bit enabled through grspw_ic_ctrl()) - */ -typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq, - unsigned int rxack, unsigned int intto); -/* Control Interrupt-code settings of core - * Write if 'options' not pointing to -1, always read current value - */ -extern void grspw_ic_ctrl(void *d, unsigned int *options); -/* Write (rw&1 == 1) configuration parameters to registers and/or, - * Read (rw&2 == 1) configuration parameters from registers, in that sequence. - */ -extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg); -/* Read or Write Interrupt-code status registers. - * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write. - * If *ptr is NULL no operation. - */ -extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack, - unsigned int *intto); -/* Generate Tick-In for the given Interrupt-code - * Returns zero on success and non-zero on failure - * - * Interrupt code bits (ic): - * Bit 5 - ACK if 1 - * Bits 4-0 Interrupt-code number - */ -extern int grspw_ic_tickin(void *d, int ic); -/* Assign handler function to Interrupt-code timeout IRQ */ -extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data); - -/*** RMAP Control Interface ***/ -/* Set (not -1) and/or read RMAP options. */ -extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey); -extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc); - -/*** SpW Port Control Interface ***/ - -/* Select port, if - * -1=The current selected port is returned - * 0=Port 0 - * 1=Port 1 - * Other positive values=Both Port0 and Port1 - */ -extern int grspw_port_ctrl(void *d, int *port); -/* Returns Number ports available in hardware */ -extern int grspw_port_count(void *d); -/* Returns the current active port */ -extern int grspw_port_active(void *d); - -/*** DMA Interface ***/ -extern void *grspw_dma_open(void *d, int chan_no); -extern int grspw_dma_close(void *c); - -extern int grspw_dma_start(void *c); -extern void grspw_dma_stop(void *c); - -/* Enable interrupt manually */ -extern unsigned int grspw_dma_enable_int(void *c, int rxtx, int force); - -/* Return Current DMA Control & Status Register */ -extern unsigned int grspw_dma_ctrlsts(void *c); - -/* Schedule List of packets for transmission at some point in - * future. - * - * 1. Move transmitted packets to SENT List (SCHED->SENT) - * 2. Add the requested packets to the SEND List (USER->SEND) - * 3. Schedule as many packets as possible for transmission (SEND->SCHED) - * - * Call this function with pkts=NULL to just do step 1 and 3. This may be - * required in Polling-mode. - * - * The above steps 1 and 3 may be skipped by setting 'opts': - * bit0 = 1: Skip Step 1. - * bit1 = 1: Skip Step 3. - * Skipping both step 1 and 3 may be usefull when IRQ is enabled, then - * the work queue will be totaly responsible for handling descriptors. - * - * The fastest solution in retreiving sent TX packets and sending new frames - * is to call: - * A. grspw_dma_tx_reclaim(opts=0) - * B. grspw_dma_tx_send(opts=1) - * - * NOTE: the TXPKT_FLAG_TX flag must not be set. - * - * Return Code - * -1 Error - * 0 Successfully added pkts to send/sched list - * 1 DMA stopped. No operation. - */ -extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count); - -/* Reclaim TX packet buffers that has previously been scheduled for transmission - * with grspw_dma_tx_send(). - * - * 1. Move transmitted packets to SENT List (SCHED->SENT) - * 2. Move all SENT List to pkts list (SENT->USER) - * 3. Schedule as many packets as possible for transmission (SEND->SCHED) - * - * The above steps 1 may be skipped by setting 'opts': - * bit0 = 1: Skip Step 1. - * bit1 = 1: Skip Step 3. - * - * The fastest solution in retreiving sent TX packets and sending new frames - * is to call: - * A. grspw_dma_tx_reclaim(opts=2) (Skip step 3) - * B. grspw_dma_tx_send(opts=1) (Skip step 1) - * - * Return Code - * -1 Error - * 0 Successful. pkts list filled with all packets from sent list - * 1 Same as 0, but indicates that DMA stopped - */ -extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count); - -/* Get current number of Packets in respective TX Queue. */ -extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent, int *hw); - -#define GRSPW_OP_AND 0 -#define GRSPW_OP_OR 1 -/* Block until send_cnt or fewer packets are Queued in "Send and Scheduled" Q, - * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition - * is met. - * If a link error occurs and the Stop on Link error is defined, this function - * will also return to caller. - * The timeout argument is used to return after timeout ticks, regardless of - * the other conditions. If timeout is zero, the function will wait forever - * until the condition is satisfied. - * - * NOTE: if IRQ of TX descriptors are not enabled conditions are never - * checked, this may hang infinitely unless a timeout has been specified - * - * Return Code - * -1 Error - * 0 Returing to caller because specified conditions are now fullfilled - * 1 DMA stopped - * 2 Timeout, conditions are not met - * 3 Another task is already waiting. Service is Busy. - */ -extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout); - -/* Get received RX packet buffers that has previously been scheduled for - * reception with grspw_dma_rx_prepare(). - * - * 1. Move Scheduled packets to RECV List (SCHED->RECV) - * 2. Move all RECV packet to the callers list (RECV->USER) - * 3. Schedule as many free packet buffers as possible (READY->SCHED) - * - * The above steps 1 may be skipped by setting 'opts': - * bit0 = 1: Skip Step 1. - * bit1 = 1: Skip Step 3. - * - * The fastest solution in retreiving received RX packets and preparing new - * packet buffers for future receive, is to call: - * A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3) - * B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1) - * - * Return Code - * -1 Error - * 0 Successfully filled pkts list with packets from recv list. - * 1 DMA stopped - */ -extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count); - -/* Add more RX packet buffers for future for reception. The received packets - * can later be read out with grspw_dma_rx_recv(). - * - * 1. Move Received packets to RECV List (SCHED->RECV) - * 2. Add the "free/ready" packet buffers to the READY List (USER->READY) - * 3. Schedule as many packets as possible (READY->SCHED) - * - * The above steps 1 may be skipped by setting 'opts': - * bit0 = 1: Skip Step 1. - * bit1 = 1: Skip Step 3. - * - * The fastest solution in retreiving received RX packets and preparing new - * packet buffers for future receive, is to call: - * A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3) - * B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1) - * - * Return Code - * -1 Error - * 0 Successfully added packet buffers from pkt list into the ready queue - * 1 DMA stopped - */ -extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count); - -/* Get current number of Packets in respective RX Queue. */ -extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv, int *hw); - -/* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR), - * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q, - * condition is met. - * If a link error occurs and the Stop on Link error is defined, this function - * will also return to caller, however with an error. - * The timeout argument is used to return after timeout ticks, regardless of - * the other conditions. If timeout is zero, the function will wait forever - * until the condition is satisfied. - * - * NOTE: if IRQ of RX descriptors are not enabled conditions are never - * checked, this may hang infinitely unless a timeout has been specified - * - * Return Code - * -1 Error - * 0 Returing to caller because specified conditions are now fullfilled - * 1 DMA stopped - * 2 Timeout, conditions are not met - * 3 Another task is already waiting. Service is Busy. - */ -extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout); - -extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg); -extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg); - -extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts); -extern void grspw_dma_stats_clr(void *c); - -/* Register GRSPW packet driver to Driver Manager */ -void grspw2_register_drv (void); - -/*** GRSPW SpaceWire Packet List Handling Routines ***/ - -static inline void grspw_list_clr(struct grspw_list *list) -{ - list->head = NULL; - list->tail = NULL; -} - -static inline int grspw_list_is_empty(struct grspw_list *list) -{ - return (list->head == NULL); -} - -/* Return Number of entries in list */ -static inline int grspw_list_cnt(struct grspw_list *list) -{ - struct grspw_pkt *lastpkt = NULL, *pkt = list->head; - int cnt = 0; - while ( pkt ) { - cnt++; - lastpkt = pkt; - pkt = pkt->next; - } - if ( lastpkt && (list->tail != lastpkt) ) - return -1; - return cnt; -} - -static inline void -grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt) -{ - pkt->next = NULL; - if ( list->tail == NULL ) { - list->head = pkt; - } else { - list->tail->next = pkt; - } - list->tail = pkt; -} - -static inline void -grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt) -{ - pkt->next = list->head; - if ( list->head == NULL ) { - list->tail = pkt; - } - list->head = pkt; -} - -static inline void -grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist) -{ - if (grspw_list_is_empty(alist)) { - return; - } - alist->tail->next = NULL; - if ( list->tail == NULL ) { - list->head = alist->head; - } else { - list->tail->next = alist->head; - } - list->tail = alist->tail; -} - -static inline void -grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist) -{ - if (grspw_list_is_empty(alist)) { - return; - } - if ( list->head == NULL ) { - list->tail = alist->tail; - alist->tail->next = NULL; - } else { - alist->tail->next = list->head; - } - list->head = alist->head; -} - -/* Remove dlist (delete-list) from head of list */ -static inline void -grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist) -{ - if (grspw_list_is_empty(dlist)) { - return; - } - list->head = dlist->tail->next; - if ( list->head == NULL ) { - list->tail = NULL; - } - dlist->tail->next = NULL; -} - -/* Take A number of entries from head of list 'list' and put the entires - * to rlist (result list). - */ -static inline int -grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max) -{ - int cnt; - struct grspw_pkt *pkt, *last; - - pkt = list->head; - - if ( (max < 1) || (pkt == NULL) ) { - grspw_list_clr(rlist); - return 0; - } - - cnt = 0; - rlist->head = pkt; - last = pkt; - while ((cnt < max) && pkt) { - last = pkt; - pkt = pkt->next; - cnt++; - } - rlist->tail = last; - grspw_list_remove_head_list(list, rlist); - return cnt; -} - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grspw_router.h b/c/src/lib/libbsp/sparc/shared/include/grspw_router.h deleted file mode 100644 index 2fab8d5f6c..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grspw_router.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * GRSPW ROUTER APB-Register Driver. - * - * COPYRIGHT (c) 2010-2017. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRSPW_ROUTER_H__ -#define __GRSPW_ROUTER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Maximum number of ROUTER devices supported by driver */ -#define ROUTER_MAX 2 - -#define ROUTER_ERR_OK 0 -#define ROUTER_ERR_EINVAL -1 -#define ROUTER_ERR_ERROR -2 -#define ROUTER_ERR_TOOMANY -3 -#define ROUTER_ERR_IMPLEMENTED -4 - -/* Hardware Information */ -struct router_hw_info { - uint8_t nports_spw; - uint8_t nports_amba; - uint8_t nports_fifo; - int8_t srouting; - int8_t pnp_enable; - int8_t timers_avail; - int8_t pnp_avail; - uint8_t ver_major; - uint8_t ver_minor; - uint8_t ver_patch; - uint8_t iid; - - /* Router capabilities */ - uint8_t amba_port_fifo_size; - uint8_t spw_port_fifo_size; - uint8_t rmap_maxdlen; - int8_t aux_async; - int8_t aux_dist_int_support; - int8_t dual_port_support; - int8_t dist_int_support; - int8_t spwd_support; - uint8_t pktcnt_support; - uint8_t charcnt_support; -}; - -#define ROUTER_FLG_CFG 0x01 -#define ROUTER_FLG_IID 0x02 -#define ROUTER_FLG_IDIV 0x04 -#define ROUTER_FLG_TPRES 0x08 -#define ROUTER_FLG_TRLD 0x10 -#define ROUTER_FLG_ALL 0x1f /* All Above Flags */ - -struct router_config { - uint32_t flags; /* Determine what configuration should be updated */ - - /* Router Configuration Register */ - uint32_t config; - - /* Set Instance ID */ - uint8_t iid; - - /* SpaceWire Link Initialization Clock Divisor */ - uint8_t idiv; - - /* Timer Prescaler */ - uint32_t timer_prescaler; -}; - -/* Routing table address control */ -struct router_route_acontrol { - uint32_t control[31]; - uint32_t control_logical[224]; -}; - -/* Routing table port mapping */ -struct router_route_portmap { - uint32_t pmap[31]; /* Port Setup for ports 1-31 */ - uint32_t pmap_logical[224]; /* Port setup for locgical addresses 32-255 */ -}; - -/* Routing table */ -#define ROUTER_ROUTE_FLG_MAP 0x01 -#define ROUTER_ROUTE_FLG_CTRL 0x02 -#define ROUTER_ROUTE_FLG_ALL 0x3 /* All Above Flags */ -struct router_routing_table { - uint32_t flags; /* Determine what configuration should be updated */ - - struct router_route_acontrol acontrol; - struct router_route_portmap portmap; -}; - -/* Set/Get Port Control/Status */ -#define ROUTER_PORT_FLG_SET_CTRL 0x01 -#define ROUTER_PORT_FLG_GET_CTRL 0x02 -#define ROUTER_PORT_FLG_SET_STS 0x04 -#define ROUTER_PORT_FLG_GET_STS 0x08 -#define ROUTER_PORT_FLG_SET_CTRL2 0x10 -#define ROUTER_PORT_FLG_GET_CTRL2 0x20 -#define ROUTER_PORT_FLG_SET_TIMER 0x40 -#define ROUTER_PORT_FLG_GET_TIMER 0x80 -#define ROUTER_PORT_FLG_SET_PKTLEN 0x100 -#define ROUTER_PORT_FLG_GET_PKTLEN 0x200 -struct router_port { - uint32_t flag; - /* Port control */ - uint32_t ctrl; - /* Port status */ - uint32_t sts; - /* Port control 2 */ - uint32_t ctrl2; - /* Timer Reload */ - uint32_t timer_reload; - /* Maximum packet length */ - uint32_t packet_length; -}; - -/* Register GRSPW Router driver to Driver Manager */ -void router_register_drv(void); - -extern void *router_open(unsigned int dev_no); -extern int router_close(void *d); -extern int router_print(void *d); -extern int router_hwinfo_get(void *d, struct router_hw_info *hwinfo); - -/* Router general config */ -extern int router_config_set(void *d, struct router_config *cfg); -extern int router_config_get(void *d, struct router_config *cfg); - -/* Routing table config */ -extern int router_routing_table_set(void *d, - struct router_routing_table *cfg); -extern int router_routing_table_get(void *d, - struct router_routing_table *cfg); - -/* - * ROUTER PCTRL register fields - */ -#define PCTRL_RD (0xff << PCTRL_RD_BIT) -#define PCTRL_ST (0x1 << PCTRL_ST_BIT) -#define PCTRL_SR (0x1 << PCTRL_SR_BIT) -#define PCTRL_AD (0x1 << PCTRL_AD_BIT) -#define PCTRL_LR (0x1 << PCTRL_LR_BIT) -#define PCTRL_PL (0x1 << PCTRL_PL_BIT) -#define PCTRL_TS (0x1 << PCTRL_TS_BIT) -#define PCTRL_IC (0x1 << PCTRL_IC_BIT) -#define PCTRL_ET (0x1 << PCTRL_ET_BIT) -#define PCTRL_NP (0x1 << PCTRL_NP_BIT) -#define PCTRL_PS (0x1 << PCTRL_PS_BIT) -#define PCTRL_BE (0x1 << PCTRL_BE_BIT) -#define PCTRL_DI (0x1 << PCTRL_DI_BIT) -#define PCTRL_TR (0x1 << PCTRL_TR_BIT) -#define PCTRL_PR (0x1 << PCTRL_PR_BIT) -#define PCTRL_TF (0x1 << PCTRL_TF_BIT) -#define PCTRL_RS (0x1 << PCTRL_RS_BIT) -#define PCTRL_TE (0x1 << PCTRL_TE_BIT) -#define PCTRL_CE (0x1 << PCTRL_CE_BIT) -#define PCTRL_AS (0x1 << PCTRL_AS_BIT) -#define PCTRL_LS (0x1 << PCTRL_LS_BIT) -#define PCTRL_LD (0x1 << PCTRL_LD_BIT) - -#define PCTRL_RD_BIT 24 -#define PCTRL_ST_BIT 21 -#define PCTRL_SR_BIT 20 -#define PCTRL_AD_BIT 19 -#define PCTRL_LR_BIT 18 -#define PCTRL_PL_BIT 17 -#define PCTRL_TS_BIT 16 -#define PCTRL_IC_BIT 15 -#define PCTRL_ET_BIT 14 -#define PCTRL_NP_BIT 13 -#define PCTRL_PS_BIT 12 -#define PCTRL_BE_BIT 11 -#define PCTRL_DI_BIT 10 -#define PCTRL_TR_BIT 9 -#define PCTRL_PR_BIT 8 -#define PCTRL_TF_BIT 7 -#define PCTRL_RS_BIT 6 -#define PCTRL_TE_BIT 5 -#define PCTRL_CE_BIT 3 -#define PCTRL_AS_BIT 2 -#define PCTRL_LS_BIT 1 -#define PCTRL_LD_BIT 0 - -/* - * ROUTER PCTRL2 register fields - */ -#define PCTRL2_SM (0xff << PCTRL2_SM_BIT) -#define PCTRL2_SV (0xff << PCTRL2_SV_BIT) -#define PCTRL2_OR (0x1 << PCTRL2_OR_BIT) -#define PCTRL2_UR (0x1 << PCTRL2_UR_BIT) -#define PCTRL2_AT (0x1 << PCTRL2_AT_BIT) -#define PCTRL2_AR (0x1 << PCTRL2_AR_BIT) -#define PCTRL2_IT (0x1 << PCTRL2_IT_BIT) -#define PCTRL2_IR (0x1 << PCTRL2_IR_BIT) -#define PCTRL2_SD (0x1f << PCTRL2_SD_BIT) -#define PCTRL2_SC (0x1f << PCTRL2_SC_BIT) - -#define PCTRL2_SM_BIT 24 -#define PCTRL2_SV_BIT 16 -#define PCTRL2_OR_BIT 15 -#define PCTRL2_UR_BIT 14 -#define PCTRL2_AT_BIT 12 -#define PCTRL2_AR_BIT 11 -#define PCTRL2_IT_BIT 10 -#define PCTRL2_IR_BIT 9 -#define PCTRL2_SD_BIT 1 -#define PCTRL2_SC_BIT 0 - -/* Router Set/Get Port configuration */ -extern int router_port_ioc(void *d, int port, struct router_port *cfg); - -/* Read-modify-write Port Control register */ -extern int router_port_ctrl_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value); -/* Read-modify-write Port Control2 register */ -extern int router_port_ctrl2_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value); -/* Read Port Control register */ -extern int router_port_ctrl_get(void *d, int port, uint32_t *ctrl); -/* Read Port Control2 register */ -extern int router_port_ctrl2_get(void *d, int port, uint32_t *ctrl2); -/* Write Port Control Register */ -extern int router_port_ctrl_set(void *d, int port, uint32_t mask, uint32_t ctrl); -/* Write Port Control2 Register */ -extern int router_port_ctrl2_set(void *d, int port, uint32_t mask, uint32_t ctrl2); -/* Set Timer Reload Value for a specific port */ -extern int router_port_treload_set(void *d, int port, uint32_t reload); -/* Get Timer Reload Value for a specific port */ -extern int router_port_treload_get(void *d, int port, uint32_t *reload); -/* Get Maximum packet length for a specific port */ -extern int router_port_maxplen_get(void *d, int port, uint32_t *length); -/* Set Maximum packet length for a specific port */ -extern int router_port_maxplen_set(void *d, int port, uint32_t length); - -/* - * ROUTER PSTSCFG register fields - */ -#define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT) -#define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT) -#define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT) -#define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT) -#define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT) -#define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT) -#define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT) -#define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT) -#define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT) -#define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT) -#define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT) -#define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT) -#define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT) -#define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT) -#define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \ - PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \ - PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \ - PSTSCFG_ME | PSTSCFG_CP) -#define PSTSCFG_WCLEAR2 (PSTSCFG_CE | PSTSCFG_CP) - -#define PSTSCFG_EO_BIT 31 -#define PSTSCFG_EE_BIT 30 -#define PSTSCFG_PL_BIT 29 -#define PSTSCFG_TT_BIT 28 -#define PSTSCFG_PT_BIT 27 -#define PSTSCFG_HC_BIT 26 -#define PSTSCFG_PI_BIT 25 -#define PSTSCFG_CE_BIT 24 -#define PSTSCFG_EC_BIT 20 -#define PSTSCFG_TS_BIT 18 -#define PSTSCFG_ME_BIT 17 -#define PSTSCFG_IP_BIT 7 -#define PSTSCFG_CP_BIT 4 -#define PSTSCFG_PC_BIT 0 - -/* - * ROUTER PSTS register fields - */ -#define PSTS_PT (0x3 << PSTS_PT_BIT) -#define PSTS_PL (0x1 << PSTS_PL_BIT) -#define PSTS_TT (0x1 << PSTS_TT_BIT) -#define PSTS_RS (0x1 << PSTS_RS_BIT) -#define PSTS_SR (0x1 << PSTS_SR_BIT) -#define PSTS_LR (0x1 << PSTS_LR_BIT) -#define PSTS_SP (0x1 << PSTS_SP_BIT) -#define PSTS_AC (0x1 << PSTS_AC_BIT) -#define PSTS_TS (0x1 << PSTS_TS_BIT) -#define PSTS_ME (0x1 << PSTS_ME_BIT) -#define PSTS_TF (0x1 << PSTS_TF_BIT) -#define PSTS_RE (0x1 << PSTS_RE_BIT) -#define PSTS_LS (0x7 << PSTS_LS_BIT) -#define PSTS_IP (0x1f << PSTS_IP_BIT) -#define PSTS_PR (0x1 << PSTS_PR_BIT) -#define PSTS_PB (0x1 << PSTS_PB_BIT) -#define PSTS_IA (0x1 << PSTS_IA_BIT) -#define PSTS_CE (0x1 << PSTS_CE_BIT) -#define PSTS_ER (0x1 << PSTS_ER_BIT) -#define PSTS_DE (0x1 << PSTS_DE_BIT) -#define PSTS_PE (0x1 << PSTS_PE_BIT) -#define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \ - PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \ - PSTS_ER | PSTS_DE | PSTS_PE) - -#define PSTS_PT_BIT 30 -#define PSTS_PL_BIT 29 -#define PSTS_TT_BIT 28 -#define PSTS_RS_BIT 27 -#define PSTS_SR_BIT 26 -#define PSTS_LR_BIT 22 -#define PSTS_SP_BIT 21 -#define PSTS_AC_BIT 20 -#define PSTS_TS_BIT 18 -#define PSTS_ME_BIT 17 -#define PSTS_TF_BIT 16 -#define PSTS_RE_BIT 15 -#define PSTS_LS_BIT 12 -#define PSTS_IP_BIT 7 -#define PSTS_PR_BIT 6 -#define PSTS_PB_BIT 5 -#define PSTS_IA_BIT 4 -#define PSTS_CE_BIT 3 -#define PSTS_ER_BIT 2 -#define PSTS_DE_BIT 1 -#define PSTS_PE_BIT 0 - -/* Check Port Status register and clear errors if there are */ -extern int router_port_status(void *d, int port, uint32_t *sts, uint32_t clrmsk); - -#define ROUTER_LINK_STATUS_ERROR_RESET 0 -#define ROUTER_LINK_STATUS_ERROR_WAIT 1 -#define ROUTER_LINK_STATUS_READY 2 -#define ROUTER_LINK_STATUS_STARTED 3 -#define ROUTER_LINK_STATUS_CONNECTING 4 -#define ROUTER_LINK_STATUS_RUN_STATE 5 -/* Get Link status */ -extern int router_port_link_status(void *d, int port); -/* Operate a Link */ -extern int router_port_enable(void *d, int port); -extern int router_port_disable(void *d, int port); -extern int router_port_link_stop(void *d, int port); -extern int router_port_link_start(void *d, int port); -extern int router_port_link_receive_spill(void *d, int port); -extern int router_port_link_transmit_reset(void *d, int port); - -/* Get port credit counter register */ -extern int router_port_cred_get(void *d, int port, uint32_t *cred); - -/* - * ROUTER RTACTRL register fields - */ -#define RTACTRL_SR (0x1 << RTACTRL_SR_BIT) -#define RTACTRL_EN (0x1 << RTACTRL_EN_BIT) -#define RTACTRL_PR (0x1 << RTACTRL_PR_BIT) -#define RTACTRL_HD (0x1 << RTACTRL_HD_BIT) - -#define RTACTRL_SR_BIT 3 -#define RTACTRL_EN_BIT 2 -#define RTACTRL_PR_BIT 1 -#define RTACTRL_HD_BIT 0 - -/* Individual route modification */ -#define ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE (0x1 << 16) -#define ROUTER_ROUTE_PACKETDISTRIBUTION_DISABLE (0x0 << 16) -#define ROUTER_ROUTE_SPILLIFNOTREADY_ENABLE RTACTRL_SR -#define ROUTER_ROUTE_SPILLIFNOTREADY_DISABLE 0 -#define ROUTER_ROUTE_ENABLE RTACTRL_EN -#define ROUTER_ROUTE_DISABLE 0 -#define ROUTER_ROUTE_PRIORITY_HIGH RTACTRL_PR -#define ROUTER_ROUTE_PRIORITY_LOW 0 -#define ROUTER_ROUTE_HEADERDELETION_ENABLE RTACTRL_HD -#define ROUTER_ROUTE_HEADERDELETION_DISABLE 0 -struct router_route { - uint8_t from_address; - uint8_t to_port[32]; - int count; - int options; -}; -extern int router_route_set(void *d, struct router_route *route); -extern int router_route_get(void *d, struct router_route *route); - -/* Router configuration port write enable */ -extern int router_write_enable(void *d); -extern int router_write_disable(void *d); - -/* Router reset */ -extern int router_reset(void *d); - -/* Set Instance ID */ -extern int router_instance_set(void *d, uint8_t iid); -/* Get Instance ID */ -extern int router_instance_get(void *d, uint8_t *iid); - -/* Set SpaceWire Link Initialization Clock Divisor */ -extern int router_idiv_set(void *d, uint8_t idiv); -/* Get SpaceWire Link Initialization Clock Divisor */ -extern int router_idiv_get(void *d, uint8_t *idiv); - -/* Set Timer Prescaler */ -extern int router_tpresc_set(void *d, uint32_t prescaler); -/* Get Timer Prescaler */ -extern int router_tpresc_get(void *d, uint32_t *prescaler); - -/* Set/get Router configuration */ -extern int router_cfgsts_set(void *d, uint32_t cfgsts); -extern int router_cfgsts_get(void *d, uint32_t *cfgsts); - -/* Router timecode */ -extern int router_tc_enable(void *d); -extern int router_tc_disable(void *d); -extern int router_tc_reset(void *d); -extern int router_tc_get(void *d); - -/* Router Interrupts */ -/* - * ROUTER IMASK register fields - */ -#define IMASK_PE (0x1 << IMASK_PE_BIT) -#define IMASK_SR (0x1 << IMASK_SR_BIT) -#define IMASK_RS (0x1 << IMASK_RS_BIT) -#define IMASK_TT (0x1 << IMASK_TT_BIT) -#define IMASK_PL (0x1 << IMASK_PL_BIT) -#define IMASK_TS (0x1 << IMASK_TS_BIT) -#define IMASK_AC (0x1 << IMASK_AC_BIT) -#define IMASK_RE (0x1 << IMASK_RE_BIT) -#define IMASK_IA (0x1 << IMASK_IA_BIT) -#define IMASK_LE (0x1 << IMASK_LE_BIT) -#define IMASK_ME (0x1 << IMASK_ME_BIT) -#define IMASK_ALL ( IMASK_PE | IMASK_SR | IMASK_RS | IMASK_TT \ - IMASK_PL | IMASK_TS | IMASK_AC | IMASK_RE | IMASK_IA \ - IMASK_LE | IMASK_ME) - -#define IMASK_PE_BIT 10 -#define IMASK_SR_BIT 9 -#define IMASK_RS_BIT 8 -#define IMASK_TT_BIT 7 -#define IMASK_PL_BIT 6 -#define IMASK_TS_BIT 5 -#define IMASK_AC_BIT 4 -#define IMASK_RE_BIT 3 -#define IMASK_IA_BIT 2 -#define IMASK_LE_BIT 1 -#define IMASK_ME_BIT 0 - -#define ROUTER_INTERRUPT_ALL IMASK_ALL -#define ROUTER_INTERRUPT_SPWPNP_ERROR IMASK_PE -#define ROUTER_INTERRUPT_SPILLED IMASK_SR -#define ROUTER_INTERRUPT_RUNSTATE IMASK_RS -#define ROUTER_INTERRUPT_TC_TRUNCATION IMASK_TT -#define ROUTER_INTERRUPT_PACKET_TRUNCATION IMASK_PL -#define ROUTER_INTERRUPT_TIMEOUT IMASK_TS -#define ROUTER_INTERRUPT_CFGPORT IMASK_AC -#define ROUTER_INTERRUPT_RMAP_ERROR IMASK_RE -#define ROUTER_INTERRUPT_INVALID_ADDRESS IMASK_IA -#define ROUTER_INTERRUPT_LINK_ERROR IMASK_LE -#define ROUTER_INTERRUPT_MEMORY_ERROR IMASK_ME -extern int router_port_interrupt_unmask(void *d, int port); -extern int router_port_interrupt_mask(void *d, int port); -extern int router_interrupt_unmask(void *d, int options); -extern int router_interrupt_mask(void *d, int options); - -/* Router Interrupt code generation */ -/* - * ROUTER ICODEGEN register fields - */ -#define ICODEGEN_UA (0x1 << ICODEGEN_UA_BIT) -#define ICODEGEN_AH (0x1 << ICODEGEN_AH_BIT) -#define ICODEGEN_IT (0x1 << ICODEGEN_IT_BIT) -#define ICODEGEN_TE (0x1 << ICODEGEN_TE_BIT) -#define ICODEGEN_EN (0x1 << ICODEGEN_EN_BIT) -#define ICODEGEN_IN (0x1f << ICODEGEN_IN_BIT) - -#define ICODEGEN_UA_BIT 20 -#define ICODEGEN_AH_BIT 19 -#define ICODEGEN_IT_BIT 18 -#define ICODEGEN_TE_BIT 17 -#define ICODEGEN_EN_BIT 16 -#define ICODEGEN_IN_BIT 0 - -#define ROUTER_ICODEGEN_ITYPE_EDGE ICODEGEN_IT -#define ROUTER_ICODEGEN_ITYPE_LEVEL 0 -#define ROUTER_ICODEGEN_AUTOUNACK_ENABLE ICODEGEN_UA -#define ROUTER_ICODEGEN_AUTOUNACK_DISABLE 0 -#define ROUTER_ICODEGEN_AUTOACK_ENABLE ICODEGEN_AH -#define ROUTER_ICODEGEN_AUTOACK_DISABLE 0 -extern int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer, - int options); -extern int router_icodegen_disable(void *d); - -/* Router interrupt change timers */ -extern int router_isrctimer_set(void *d, uint32_t reloadvalue); -extern int router_isrctimer_get(void *d, uint32_t *reloadvalue); - -/* Router interrupt timers */ -extern int router_isrtimer_set(void *d, uint32_t reloadvalue); -extern int router_isrtimer_get(void *d, uint32_t *reloadvalue); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/grtc.h b/c/src/lib/libbsp/sparc/shared/include/grtc.h deleted file mode 100644 index 3ee1fa547c..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grtc.h +++ /dev/null @@ -1,155 +0,0 @@ -/* GRTC Telecommand (TC) decoder driver interface - * - * COPYRIGHT (c) 2007. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRTC_H__ -#define __GRTC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define GRTC_IOC_UNUSED 0 - -/* Driver operation controlling commands */ -#define GRTC_IOC_START 1 -#define GRTC_IOC_STOP 2 -#define GRTC_IOC_ISSTARTED 3 -#define GRTC_IOC_SET_BLOCKING_MODE 4 /* Raw mode only */ -#define GRTC_IOC_SET_TIMEOUT 5 /* Raw mode only */ - -#define GRTC_IOC_ADD_BUFF 16 /* Frame mode only */ -#define GRTC_IOC_RECV 17 /* Frame mode only */ - -/* Available only in STOPPED mode */ -#define GRTC_IOC_SET_MODE 32 /* Set frame mode (ioctl) or raw mode (read) */ -#define GRTC_IOC_SET_BUF_PARAM 33 -#define GRTC_IOC_SET_CONFIG 34 -#define GRTC_IOC_POOLS_SETUP 35 /* Frame mode only */ - -/* Available in both running and stopped mode */ -#define GRTC_IOC_GET_CONFIG 64 -#define GRTC_IOC_GET_BUF_PARAM 65 -#define GRTC_IOC_GET_HW_STATUS 66 -#define GRTC_IOC_ASSIGN_FRM_POOL 67 -#define GRTC_IOC_GET_CLCW_ADR 68 /* Get address of CLCWRx1 */ -#define GRTC_IOC_GET_STATS 69 /* Get statistics, note that most of the stats are only avilable in FRAME mode */ -#define GRTC_IOC_CLR_STATS 70 /* Clear statistics */ - -/* Available only in RUNNING mode */ - -/* Args to GRTC_IOC_GET_BUF_PARAMS */ -#define GRTC_BUF_MAXLEN (0x100*1024) -#define GRTC_BUF_MASK 0xfffffc00 -struct grtc_ioc_buf_params { - unsigned int length; /* Length of new buffer in multiples of 1kbyte blocks */ - void *custom_buffer; /* If set zero driver will allocate with malloc, set LSB to 1 to indicate remote address */ -}; - -/* Args to GRTC_IOC_SET_BLOCKING_MODE */ -enum { - GRTC_BLKMODE_POLL = 0, /* Never block (polling mode) */ - GRTC_BLKMODE_BLK = 1, /* Block until at least 1 byte can be read */ - GRTC_BLKMODE_COMPLETE = 2 /* Block until all data requested has be read */ -}; - -/* Argument of GRTC_IOC_SET_CONFIG and GRTC_IOC_GET_CONFIG - * Pointer to: - */ -struct grtc_ioc_config { - int psr_enable; - int nrzm_enable; - int pss_enable; - int crc_calc; /* Enable Software CRC calculation (only Frame mode) */ -}; - -/* Argument of GRTC_IOC_GET_HW_STATUS: - * Pointer to a grtc_ioc_hw_status structure that will be filled - * in by driver. - */ -struct grtc_ioc_hw_status { - unsigned int sir; - unsigned int far; - unsigned int clcw1; - unsigned int clcw2; - unsigned int phir; - unsigned int str; -}; - -struct grtc_hdr { - unsigned short flags_scid; - unsigned short vc_len; - unsigned char seqnum; -} __attribute__((packed)); - -/* Frame pool, all frames in pool have the same buffer length (frame mode only) */ -struct grtc_frame { - struct grtc_frame *next; /* Next frame in list */ - unsigned short len; /* Length of frame extracted */ - unsigned short reserved; /* Reserved */ - struct grtc_frame_pool *pool; /* The frame pool this frame belongs to */ - - /* The Frame content */ - struct grtc_hdr hdr; /* Primary Header */ - unsigned char data[3]; /* Frame payload */ -} __attribute__((packed)); - -/* GRTC_IOC_RECV argument, single linked list of received frames */ -struct grtc_list { - struct grtc_frame *head; /* First frame in list */ - struct grtc_frame *tail; /* Last frame in list */ - int cnt; /* Number of frames in list */ -}; - -struct grtc_ioc_pools_setup { - unsigned int pool_cnt; /* Number of pools */ - unsigned int pool_frame_len[1]; /* Array of 'pool_cnt' length: Frame length of frames in a pool - * Lengths must be sorted, starting with the smallest frame pool. - */ -}; - -struct grtc_ioc_assign_frm_pool { - unsigned int frame_len; /* The length of the pool to insert the frame into */ - struct grtc_frame *frames; /* Frames to assign to a pool */ -}; - -enum { - GRTC_MODE_RAW = 0, - GRTC_MODE_FRAME = 1 -}; - -/* TC driver stats collected during receiving. The statistics is only available - * in FRAME mode. In RAW mode the user interprets the incoming frames and is - * therefore responsible for generating the staticstics. - */ -struct grtc_ioc_stats { - unsigned long long frames_recv; /* Total number of non-erroneous frames received */ - /* Errors related to incoming data */ - unsigned int err; /* total number of errors */ - unsigned int err_hdr; /* number of errors in Header */ - unsigned int err_payload; /* Number of errors in payload */ - unsigned int err_ending; /* Number of errors in end (Filler, end marker) */ - unsigned int err_abandoned; /* Number of abandoned frames, NOT IMPLEMENTED */ - /* Errors related to the handling of incoming frames */ - unsigned int dropped; /* Number of dropped frames TC driver */ - unsigned int dropped_no_buf; /* Number of dropped frame caused by no buffers were available */ - unsigned int dropped_too_long; /* Number of dropped frames that was larger than any buffer available for driver */ -}; - -/* Register GRTC driver at driver manager */ -void grtc_register_drv(void); - -/* Register GRTC RMAP driver at driver manager */ -void grtc_rmap_register_drv (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __GRTC_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/grtm.h b/c/src/lib/libbsp/sparc/shared/include/grtm.h deleted file mode 100644 index 625f8389b7..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/grtm.h +++ /dev/null @@ -1,245 +0,0 @@ -/* GRTM Telemetry (TM) driver interface - * - * COPYRIGHT (c) 2007. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __GRTM_H__ -#define __GRTM_H__ - -#include <rtems.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define GRTM_IOC_UNUSED 0 - -/* Driver operation controlling commands */ -#define GRTM_IOC_START 1 -#define GRTM_IOC_STOP 2 -#define GRTM_IOC_ISSTARTED 3 -#define GRTM_IOC_SET_BLOCKING_MODE 4 -#define GRTM_IOC_SET_TIMEOUT 5 - -/* Available only in STOPPED mode */ -#define GRTM_IOC_SET_CONFIG 32 - -/* Available in both running and stopped mode */ -#define GRTM_IOC_RECLAIM 64 -#define GRTM_IOC_GET_CONFIG 65 -#define GRTM_IOC_GET_HW_IMPL 66 -#define GRTM_IOC_GET_HW_STATUS 67 /* Not implemented */ -#define GRTM_IOC_GET_OCFREG 68 -#define GRTM_IOC_GET_STATS 69 -#define GRTM_IOC_CLR_STATS 70 - -/* Available only in RUNNING mode */ -#define GRTM_IOC_SEND 96 - -/* Args to GRTC_IOC_SET_BLOCKING_MODE */ -enum { - GRTM_BLKMODE_POLL = 0, /* Never block (polling mode) */ - GRTM_BLKMODE_BLK = 1, /* Block until at least 1 byte can be read */ -}; - -/* Reed Solomon Encoder implemented */ -enum { - GRTM_RS_IMPL_NONE = 0, - GRTM_RS_IMPL_E16 = 1, /* E16 */ - GRTM_RS_IMPL_E8 = 2, /* E8 */ - GRTM_RS_IMPL_BOTH = 3 /* Both E8 and E16 */ - -}; - -struct grtm_ioc_hw { - char cs; /* Sub Carrier */ - char sp; /* Split-Phase Level */ - char ce; - char nrz; - char psr; - char te; - unsigned char rsdep; - unsigned char rs; - char aasm; - char fecf; - char ocf; - char evc; - char idle; - char fsh; - char mcg; - char iz; - char fhec; - char aos; - char cif; - char ocfb; - - unsigned short blk_size; /* Block Size */ - unsigned short fifo_size; /* FIFO Size */ - -}; - -/* Driver Mode */ -enum { - GRTM_MODE_TM = 0, /* TM */ - GRTM_MODE_AOS = 1 /* AOS */ -}; - -/* Physical layer Options */ -#define GRTM_IOC_PHY_SCF (1<<15) /* Sub Carrier Fall */ -#define GRTM_IOC_PHY_SF (1<<31) /* Symbol Fall */ - -/* Coding Sub-layer Options */ -#define GRTM_IOC_CODE_SC (1<<0) /* Enable Sub Carrier modulation */ -#define GRTM_IOC_CODE_SP (1<<1) /* Enable Split-Phase (SP) level modulation */ -#define GRTM_IOC_CODE_CE (1<<5) /* Enable Convolutional Encoding */ -#define GRTM_IOC_CODE_NRZ (1<<6) /* Enable Non-Return-to-Zero mark encoding */ -#define GRTM_IOC_CODE_PSR (1<<7) /* Enable Pseudo-Randomizer */ -#define GRTM_IOC_CODE_RS8 (1<<11) /* Reed-solomon Encoder to use: 0=E16, 1=E8 */ -#define GRTM_IOC_CODE_RS (1<<15) /* Enable Reed-Solomon Encoder */ -#define GRTM_IOC_CODE_AASM (1<<16) /* Enable Alternative attached synchronization marker */ -#define GRTM_IOC_CODE_ALL (GRTM_IOC_CODE_SC|GRTM_IOC_CODE_SP|GRTM_IOC_CODE_CE| \ - GRTM_IOC_CODE_NRZ|GRTM_IOC_CODE_PSR|GRTM_IOC_CODE_RS8|\ - GRTM_IOC_CODE_RS|GRTM_IOC_CODE_AASM) - -enum { - GRTM_CERATE_00 = 0, /* Rate 1/2, no puncturing */ - GRTM_CERATE_02 = 2, /* Rate 1/2, punctured */ - GRTM_CERATE_04 = 4, /* Rate 2/3, punctured */ - GRTM_CERATE_05 = 5, /* Rate 3/4, punctured */ - GRTM_CERATE_06 = 6, /* Rate 5/6, punctured */ - GRTM_CERATE_07 = 7, /* Rate 7/8, punctured */ -}; - -/* Options for Generating all frames */ -#define GRTM_IOC_ALL_FHEC 0x01 /* Enable Frame Header Error Control (Only AOS) */ -#define GRTM_IOC_ALL_FECF 0x02 /* Enable Transfer Frame CRC */ -#define GRTM_IOC_ALL_IZ 0x04 /* Enable Insert Zone */ -#define GRTM_IOC_ALL_ALL (GRTM_IOC_ALL_FHEC|GRTM_IOC_ALL_FECF|GRTM_IOC_ALL_IZ) - -/* Master Frame Generation Options */ -#define GRTM_IOC_MF_OW 0x01 /* Over Write OCF bits 16 and 17 */ -#define GRTM_IOC_MF_OCF 0x02 /* Enable Operation Control Field (OCF) for master channel */ -#define GRTM_IOC_MF_FSH 0x04 /* Enable MC_FSH for master channel */ -#define GRTM_IOC_MF_MC 0x08 /* Enable Master channel counter generation */ -#define GRTM_IOC_MF_ALL (GRTM_IOC_MF_OW|GRTM_IOC_MF_OCF|GRTM_IOC_MF_FSH|GRTM_IOC_MF_MC) - -/* Idle Frames Generation Options */ -#define GRTM_IOC_IDLE_MC 0x01 /* Enable Master Channel (MC) counter generation (TM Only) */ -#define GRTM_IOC_IDLE_VCC 0x02 /* Enable Virtual Channel counter cycle generation (AOS Only)*/ -#define GRTM_IOC_IDLE_FSH 0x04 /* Enable Frame Secondary Header (FSH) for idle frames (TM Only) */ -#define GRTM_IOC_IDLE_EVC 0x08 /* Enable Extended Virtual Channel Counter Generation */ -#define GRTM_IOC_IDLE_OCF 0x10 /* Enable OCF/CLCW in idle frame */ -#define GRTM_IOC_IDLE_EN 0x20 /* Enable Idle frame generation */ -#define GRTM_IOC_IDLE_ALL (GRTM_IOC_IDLE_MC|GRTM_IOC_IDLE_VCC|GRTM_IOC_IDLE_FSH| \ - GRTM_IOC_IDLE_EVC|GRTM_IOC_IDLE_OCF|GRTM_IOC_IDLE_EN) - -/* Argument of GRTM_IOC_SET_CONFIG and GRTM_IOC_GET_CONFIG. - * Driver and Hardware configuration. - * - * Pointer to: - */ -struct grtm_ioc_config { - - /* Mode AOS or TM */ - unsigned char mode; /* 0=TM, 1=AOS */ - - unsigned short frame_length; /* Length of every frame transmitted */ - unsigned short limit; /* Number of data bytes fetched by DMA before transmission starts */ - unsigned int as_marker; /* Attached Synchronization Marker */ - - /* Physical layer options */ - unsigned short phy_subrate; /* Sub Carrier rate - sub carrier devision factor - 1 */ - unsigned short phy_symbolrate; /* Symbol Rate division factor - 1 */ - unsigned char phy_opts; /* Mask of GRTM_IOC_PHY_XXXX */ - - /* Coding sub-layer Options */ - unsigned char code_rsdep; /* Coding sub-layer Reed-Solomon interleave depth (3-bit) */ - unsigned char code_ce_rate; /* Convolutional encoding rate, select one of GRTM_CERATE_00 ... GRTM_CERATE_07 */ - unsigned char code_csel; /* */ - unsigned int code_opts; /* Mask of GRTM_IOC_CODE_XXXX */ - - /* All Frames Generation */ - unsigned char all_izlen; /* FSH/IZ Length (5-bit) */ - unsigned char all_opts; /* Mask of GRTM_IOC_ALL_XXXX */ - - /* Master Frame Generation */ - unsigned char mf_opts; /* Mask of GRTM_IOC_MF_XXXX */ - - /* Idle frame Generation */ - unsigned short idle_scid; - unsigned char idle_vcid; - unsigned char idle_opts; /* Mask of GRTM_IOC_IDLE_XXXX */ - - /* Interrupt options */ - unsigned int enable_cnt; /* Number of frames in between Interrupt is generated, Zero disables interrupt */ - int isr_desc_proc; /* Enable ISR to process descriptors */ - int blocking; /* Blocking mode select (POLL,BLK..) */ - rtems_interval timeout; /* Blocking mode timeout */ -}; - -struct grtm_frame; - -struct grtm_list { - struct grtm_frame *head; /* First Frame in list */ - struct grtm_frame *tail; /* Last Frame in list */ -}; - -#define GRTM_FLAGS_SENT 0x01 -#define GRRM_FLAGS_ERR 0x02 - -#define GRTM_FLAGS_TRANSLATE (1<<31) /* Translate frame payload address from CPU address to remote bus (the bus GRTM is resident on) */ -#define GRTM_FLAGS_TRANSLATE_AND_REMEMBER (1<<30) /* As GRTM_FLAGS_TRANSLATE, however if the translated payload address equals the payload address - * the GRTM_FLAGS_TRANSLATE_AND_REMEMBER bit is cleared and the GRTM_FLAGS_TRANSLATE bit is set */ -#define GRTM_FLAGS_COPY_DATA (1<<29) /* Where available: Transfer Frame payload to target, may be used for SpaceWire, where the GRTM driver transfer - * the payload to a buffer on the SpaceWire target. - */ - -#define GRTM_FLAGS_TS (1<<14) -#define GRTM_FLAGS_VCE (1<<9) -#define GRTM_FLAGS_MCB (1<<8) -#define GRTM_FLAGS_FSHB (1<<7) -#define GRTM_FLAGS_OCFB (1<<6) -#define GRTM_FLAGS_FHECB (1<<5) -#define GRTM_FLAGS_IZB (1<<4) -#define GRTM_FLAGS_FECFB (1<<3) - -#define GRTM_FLAGS_MASK (GRTM_FLAGS_TS|GRTM_FLAGS_VCE|GRTM_FLAGS_MCB|\ - GRTM_FLAGS_FSHB|GRTM_FLAGS_OCFB|GRTM_FLAGS_FHECB|\ - GRTM_FLAGS_IZB|GRTM_FLAGS_FECFB) - -/* The GRTM software representation of a Frame */ -struct grtm_frame { - /* Options and status */ - unsigned int flags; /* bypass options, and sent/error status */ - - struct grtm_frame *next; /* Next packet in chain */ - - unsigned int *payload; /* The Headers and Payload, Frame data and header must be word aligned */ -}; - -#define FRAME_SIZE(payloadlen) (sizeof(struct grtm_frame)+payloadlen) - -struct grtm_ioc_stats { - unsigned long long frames_sent; - unsigned int err_underrun; - unsigned int err_tx; - unsigned int err_ahb; - unsigned int err_transfer_frame; -}; - -/* Register GRTM driver at driver manager */ -void grtm_register_drv(void); - -/* Register GRTM RMAP driver at driver manager */ -void grtm_rmap_register_drv (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __GRTM_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/i2cmst.h b/c/src/lib/libbsp/sparc/shared/include/i2cmst.h deleted file mode 100644 index 3eee717524..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/i2cmst.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * @file - * @ingroup sparc_bsp - * @defgroup i2c I2C-master - * @ingroup i2c - * @brief Driver for GRLIB port of OpenCores I2C-master - */ - -/* - * COPYRIGHT (c) 2007 Cobham Gaisler AB - * with parts from the RTEMS MPC83xx I2C driver (c) 2007 Embedded Brains GmbH. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _I2CMST_H -#define _I2CMST_H - -#include <rtems/libi2c.h> -#include <ambapp.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* I2C-master operational registers */ - -typedef struct gr_i2cmst_regs { - volatile unsigned int prescl; /* Prescale register */ - volatile unsigned int ctrl; /* Control register */ - volatile unsigned int tdrd; /* Transmit and Receive registers */ - volatile unsigned int cmdsts; /* Command and Status registers */ -} gr_i2cmst_regs_t; - -/* Control (CTRL) register */ -#define GRI2C_CTRL_EN 0x00000080 /* Enable core */ -#define GRI2C_CTRL_IEN 0x00000040 /* Interrupt enable */ - -/* Command (CMD) register */ -#define GRI2C_CMD_STA 0x00000080 /* Generate START condition */ -#define GRI2C_CMD_STO 0x00000040 /* Generate STOP condition */ -#define GRI2C_CMD_RD 0x00000020 /* Read from slave */ -#define GRI2C_CMD_WR 0x00000010 /* Write to slave */ -#define GRI2C_CMD_ACK 0x00000008 /* Acknowledge */ -#define GRI2C_CMD_IACK 0x00000001 /* Interrupt acknowledge */ - -/* Status (STS) register */ -#define GRI2C_STS_RXACK 0x00000080 /* Receive acknowledge */ -#define GRI2C_STS_BUSY 0x00000040 /* I2C-bus busy */ -#define GRI2C_STS_AL 0x00000020 /* Arbitration lost */ -#define GRI2C_STS_TIP 0x00000002 /* Transfer in progress */ -#define GRI2C_STS_IF 0x00000001 /* Interrupt flag */ - -#define GRI2C_STATUS_IDLE 0x00000000 - -/* Register I2CMST driver to Driver Manager */ -void i2cmst_register_drv (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _I2CMST_H */ diff --git a/c/src/lib/libbsp/sparc/shared/include/l2c.h b/c/src/lib/libbsp/sparc/shared/include/l2c.h deleted file mode 100644 index 52473ddf2a..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/l2c.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * GRLIB L2CACHE Driver - * - * COPYRIGHT (c) 2017 - * Cobham Gaisler AB - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * OVERVIEW - * ======== - * This driver controls the L2CACHE device located - * at an on-chip AMBA. - */ - -#ifndef __L2CACHE_H__ -#define __L2CACHE_H__ - -#include <stdint.h> -#include <stdio.h> - -#ifdef __cplusplus -extern "C" { -#endif - -extern void l2cache_register_drv(void); - -#define L2CACHE_ERR_OK 0 -#define L2CACHE_ERR_NOINIT -1 -#define L2CACHE_ERR_EINVAL -2 -#define L2CACHE_ERR_TOOMANY -3 -#define L2CACHE_ERR_ERROR -4 - -/* L2C Flush options */ -#define L2CACHE_OPTIONS_FLUSH_WAIT (0x1 << 2) -#define L2CACHE_OPTIONS_FLUSH_INVALIDATE (0x3 << 0) -#define L2CACHE_OPTIONS_FLUSH_WRITEBACK (0x2 << 0) -#define L2CACHE_OPTIONS_FLUSH_INV_WBACK (0x1 << 0) -#define L2CACHE_OPTIONS_FLUSH_NONE (0 << 0) - -/* L2C Status */ -#define L2CACHE_STATUS_ENABLED 1 -#define L2CACHE_STATUS_SPLIT_ENABLED (0x1 << 1) -#define L2CACHE_STATUS_EDAC_ENABLED (0x1 << 2) -#define L2CACHE_STATUS_REPL (0x3 << L2CACHE_STATUS_REPL_BIT) -#define L2CACHE_STATUS_REPL_BIT 3 -#define L2CACHE_STATUS_WRITETHROUGH (0x1 << 5) -#define L2CACHE_STATUS_LOCK (0xf << L2CACHE_STATUS_LOCK_BIT) -#define L2CACHE_STATUS_LOCK_BIT 6 -#define L2CACHE_STATUS_SCRUB_ENABLED (0x1 << 10) -#define L2CACHE_STATUS_INT (0xf << L2CACHE_STATUS_INT_BIT) -#define L2CACHE_STATUS_INT_BIT 11 -#define L2CACHE_STATUS_INT_BCKEND (0x1 << 11) -#define L2CACHE_STATUS_INT_WPHIT (0x1 << 12) -#define L2CACHE_STATUS_INT_UEE (0x1 << 13) -#define L2CACHE_STATUS_INT_CEE (0x1 << 14) -#define L2CACHE_STATUS_SCRUB_DELAY (0xffff << L2CACHE_STATUS_SCRUB_DELAY_BIT) -#define L2CACHE_STATUS_SCRUB_DELAY_BIT 15 -#define L2CACHE_STATUS_SIGN_BIT 31 - -/* status helper macros */ -#define L2CACHE_ENABLED(status) (status & L2CACHE_STATUS_ENABLED) -#define L2CACHE_DISABLED(status) (!(status & L2CACHE_STATUS_ENABLED)) -#define L2CACHE_SPLIT_ENABLED(status) (status & L2CACHE_STATUS_SPLIT_ENABLED) -#define L2CACHE_SPLIT_DISABLED(status) \ - (!(status & L2CACHE_STATUS_SPLIT_ENABLED)) -#define L2CACHE_EDAC_ENABLED(status) (status & L2CACHE_STATUS_EDAC_ENABLED) -#define L2CACHE_EDAC_DISABLED(status) (!(status & L2CACHE_STATUS_EDAC_ENABLED)) -#define L2CACHE_REPL(status) \ - ((status & L2CACHE_STATUS_REPL) >> L2CACHE_STATUS_REPL_BIT) -#define L2CACHE_WRITETHROUGH(status) (status & L2CACHE_STATUS_WRITETHROUGH) -#define L2CACHE_WRITEBACK(status) (!(status & L2CACHE_STATUS_WRITETHROUGH)) -#define L2CACHE_LOCKED_WAYS(status) \ - ((status & L2CACHE_STATUS_LOCK) >> L2CACHE_STATUS_LOCK_BIT) -#define L2CACHE_SCRUB_ENABLED(status) (status & L2CACHE_STATUS_SCRUB_ENABLED) -#define L2CACHE_SCRUB_DISABLED(status) \ - (!(status & L2CACHE_STATUS_SCRUB_ENABLED)) -#define L2CACHE_SCRUB_DELAY(status) \ - ((status & L2CACHE_STATUS_SCRUB_DELAY) >> L2CACHE_STATUS_SCRUB_DELAY_BIT) -#define L2CACHE_INT_ENABLED(status) (status & L2CACHE_STATUS_INT) -#define L2CACHE_INT_DISABLED(status) (!(status & L2CACHE_STATUS_INT)) -extern int l2cache_status(void); - -/* L2C Setup */ -extern int l2cache_enable(int flush); -extern int l2cache_disable(int flush); - -extern int l2cache_split_enable(void); -extern int l2cache_split_disable(void); - -extern int l2cache_edac_enable(int flush); -extern int l2cache_edac_disable(int flush); - -extern int l2cache_scrub_enable(int delay); -extern int l2cache_scrub_disable(void); -extern int l2cache_scrub_line(int way, int index); - -extern int l2cache_writethrough(int flush); -extern int l2cache_writeback(int flush); - -#define L2CACHE_OPTIONS_REPL_INDEX_WAY_BIT (2) -#define L2CACHE_OPTIONS_REPL_MASTERIDX_MOD (3 << 0) -#define L2CACHE_OPTIONS_REPL_MASTERIDX_IDX (2 << 0) -#define L2CACHE_OPTIONS_REPL_RANDOM (1 << 0) -#define L2CACHE_OPTIONS_REPL_LRU (0 << 0) -extern int l2cache_replacement(int options, int flush); - -/* L2C Flush */ -extern int l2cache_flush(int flush); -extern int l2cache_flush_address(uint32_t addr, int size, int flush); -extern int l2cache_flush_line(int way, int index, int flush); -extern int l2cache_flush_way(int way, int flush); - -/* L2C Lock way */ -#define L2CACHE_OPTIONS_DIRTY (0x1 << 2) -#define L2CACHE_OPTIONS_VALID (0x1 << 1) -#define L2CACHE_OPTIONS_FETCH (0x1 << 0) -#define L2CACHE_OPTIONS_DISABLE 2 -#define L2CACHE_OPTIONS_ENABLE 1 -#define L2CACHE_OPTIONS_NONE 0 -extern int l2cache_lock_way(uint32_t tag, int options, int flush, int enable); -extern int l2cache_unlock(void); - -/* L2C Fill a way */ -extern int l2cache_fill_way(int way, uint32_t tag, int options, int flush); - -/* L2C MTRR */ -#define L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH (0x1 << 2) -#define L2CACHE_OPTIONS_MTRR_ACCESS_UNCACHED (0x0 << 2) -#define L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE (0x1 << 1) -#define L2CACHE_OPTIONS_MTRR_WRITEPROT_DISABLE (0x0 << 1) -extern int l2cache_mtrr_enable(int id, uint32_t addr, uint32_t mask, - int options, int flush); -extern int l2cache_mtrr_disable(int id); - -/* L2C Debug print */ -extern int l2cache_print(void); - -/* L2C Interrupts */ -/* Function Interrupt-Code ISR callback prototype. - * arg - Custom arg provided by user - * addr - Cacheline addr that generated the error - * status - Error status register of the L2CACHE core - */ -typedef void (*l2cache_isr_t)(void *arg, uint32_t addr, uint32_t status); -#define L2CACHE_INTERRUPT_ALL (0xf << 0) -#define L2CACHE_INTERRUPT_BACKENDERROR (0x1 << 3) -#define L2CACHE_INTERRUPT_WPROTHIT (0x1 << 2) -#define L2CACHE_INTERRUPT_UNCORRERROR (0x1 << 1) -#define L2CACHE_INTERRUPT_CORRERROR (0x1 << 0) -extern int l2cache_isr_register( l2cache_isr_t isr, void * arg, int options); -extern int l2cache_isr_unregister(void); -extern int l2cache_interrupt_mask(int options); -extern int l2cache_interrupt_unmask(int options); - -/* L2C error interface */ -#define L2CACHE_STATUS_MULTIPLEERRORS 2 -#define L2CACHE_STATUS_NEWERROR 1 -#define L2CACHE_STATUS_NOERROR 0 -extern int l2cache_error_status(uint32_t * addr, uint32_t * status); - -/*#define TEST_L2CACHE*/ -#ifdef TEST_L2CACHE -/* Used for internal testing */ -/* - * L2CACHE Tag private data struture - */ -struct l2cache_tag { - uint32_t tag; - int valid; - int dirty; - int lru; -}; - -/* - * L2CACHE Line private data struture - */ -struct l2cache_dataline { - uint32_t data[16]; - int words; -}; -extern int l2cache_get_index( uint32_t addr); -extern uint32_t l2cache_get_tag( uint32_t addr); - -extern int l2cache_diag_tag( int way, int index, struct l2cache_tag * tag); -extern int l2cache_diag_line( int way, int index, - struct l2cache_dataline * dataline); - -#define L2CACHE_HIT 1 -#define L2CACHE_MISS 0 -extern int l2cache_lookup(uint32_t addr, int * way); - -extern int l2cache_error_inject_address( uint32_t addr, uint32_t mask); -#endif /* TEST_L2CACHE */ - -#ifdef __cplusplus -} -#endif - -#endif /* __L2CACHE_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/l4stat.h b/c/src/lib/libbsp/sparc/shared/include/l4stat.h deleted file mode 100644 index 94fbe4b095..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/l4stat.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * L4STAT APB-Register Driver. - * - * COPYRIGHT (c) 2017. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __L4STAT_H__ -#define __L4STAT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define L4STAT_ERR_OK 0 -#define L4STAT_ERR_EINVAL -1 -#define L4STAT_ERR_ERROR -2 -#define L4STAT_ERR_TOOMANY -3 -#define L4STAT_ERR_IMPLEMENTED -4 - -/* Register L4STAT driver to Driver Manager */ -void l4stat_register_drv (void); - -extern int l4stat_counter_print(unsigned int counter); - -/* - * L4STAT CCTRL register fields - */ -#define CCTRL_NCPU (0xf << CCTRL_NCPU_BIT) -#define CCTRL_NCNT_L3STAT (0x1ff << CCTRL_NCNT_BIT) -#define CCTRL_NCNT (0x1f << CCTRL_NCNT_BIT) -#define CCTRL_MC (0x1 << CCTRL_MC_BIT) -#define CCTRL_IA (0x1 << CCTRL_IA_BIT) -#define CCTRL_DS (0x1 << CCTRL_DS_BIT) -#define CCTRL_EE (0x1 << CCTRL_EE_BIT) -#define CCTRL_AE (0x1 << CCTRL_AE_BIT) -#define CCTRL_EL (0x1 << CCTRL_EL_BIT) -#define CCTRL_CD (0x1 << CCTRL_CD_BIT) -#define CCTRL_SU (0x3 << CCTRL_SU_BIT) -#define CCTRL_CL (0x1 << CCTRL_CL_BIT) -#define CCTRL_EN (0x1 << CCTRL_EN_BIT) -#define CCTRL_EVENTID (0xff << CCTRL_EVENTID_BIT) -#define CCTRL_CPUAHBM (0xf << CCTRL_CPUAHBM_BIT) - -#define CCTRL_NCPU_BIT 28 -#define CCTRL_NCNT_BIT 23 -#define CCTRL_MC_BIT 22 -#define CCTRL_IA_BIT 21 -#define CCTRL_DS_BIT 20 -#define CCTRL_EE_BIT 19 -#define CCTRL_AE_BIT 18 -#define CCTRL_EL_BIT 17 -#define CCTRL_CD_BIT 16 -#define CCTRL_SU_BIT 14 -#define CCTRL_CL_BIT 13 -#define CCTRL_EN_BIT 12 -#define CCTRL_EVENTID_BIT 4 -#define CCTRL_CPUAHBM_BIT 0 - -#define L4STAT_OPTIONS_EVENT_LEVEL_ENABLE CCTRL_EL -#define L4STAT_OPTIONS_EVENT_LEVEL_DISABLE 0 -#define L4STAT_OPTIONS_MAXIMUM_DURATION CCTRL_CD -#define L4STAT_OPTIONS_SUPERVISOR_MODE_FILTER (0x1 << CCTRL_SU_BIT) -#define L4STAT_OPTIONS_USER_MODE_FILTER (0x2 << CCTRL_SU_BIT) -#define L4STAT_OPTIONS_NO_FILTER 0 -#define L4STAT_OPTIONS_CLEAR_ON_READ CCTRL_CL - -extern int l4stat_counter_enable(unsigned int counter, int event, int cpu, int options); -extern int l4stat_counter_disable(unsigned int counter); -extern int l4stat_counter_set(unsigned int counter, uint32_t val); -extern int l4stat_counter_get(unsigned int counter, uint32_t *val); - -static inline int l4stat_counter_clear(unsigned int counter) -{ - return l4stat_counter_set(counter, 0); -} - -extern int l4stat_counter_max_set(unsigned int counter, uint32_t val); -extern int l4stat_counter_max_get(unsigned int counter, uint32_t *val); -extern int l4stat_tstamp_set(uint32_t val); -extern int l4stat_tstamp_get(uint32_t *val); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/mctrl.h b/c/src/lib/libbsp/sparc/shared/include/mctrl.h deleted file mode 100644 index db449cb11a..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/mctrl.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Memory Controller driver interface - * - * COPYRIGHT (c) 2015. - * Cobham Gaisler. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __MCTRL_H__ -#define __MCTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Register MEMCTRL driver to Driver manager */ -void mctrl_register_drv (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/memscrub.h b/c/src/lib/libbsp/sparc/shared/include/memscrub.h deleted file mode 100644 index 1e55d8e127..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/memscrub.h +++ /dev/null @@ -1,172 +0,0 @@ -/* MEMSCRUB driver interface - * - * COPYRIGHT (c) 2017. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __MEMSCRUB_H__ -#define __MEMSCRUB_H__ - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define MEMSCRUB_ERR_OK 0 -#define MEMSCRUB_ERR_EINVAL -1 -#define MEMSCRUB_ERR_ERROR -2 - -extern void memscrub_register_drv(void); - -/* - * MEMORYSCRUBBER CONFIG register fields - */ -#define CONFIG_DELAY_BIT 8 -#define CONFIG_IRQD_BIT 7 -#define CONFIG_SERA_BIT 5 -#define CONFIG_LOOP_BIT 4 -#define CONFIG_MODE_BIT 2 -#define CONFIG_ES_BIT 1 -#define CONFIG_SCEN_BIT 0 - -#define CONFIG_DELAY (0xff << CONFIG_DELAY_BIT) -#define CONFIG_IRQD (0x1 << CONFIG_IRQD_BIT) -#define CONFIG_SERA (0x1 << CONFIG_SERA_BIT) -#define CONFIG_LOOP (0x1 << CONFIG_LOOP_BIT) -#define CONFIG_MODE (0x3 << CONFIG_MODE_BIT) -#define CONFIG_ES (0x1 << CONFIG_ES_BIT) -#define CONFIG_SCEN (0x1 << CONFIG_SCEN_BIT) -#define CONFIG_MODE_SCRUB (0x0 << CONFIG_MODE_BIT) -#define CONFIG_MODE_REGEN (0x1 << CONFIG_MODE_BIT) -#define CONFIG_MODE_INIT (0x2 << CONFIG_MODE_BIT) - -#define MEMSCRUB_OPTIONS_INTERRUPTDONE_ENABLE CONFIG_IRQD -#define MEMSCRUB_OPTIONS_INTERRUPTDONE_DISABLE 0 -#define MEMSCRUB_OPTIONS_EXTERNALSTART_ENABLE CONFIG_ES -#define MEMSCRUB_OPTIONS_EXTERNALSTART_DISABLE 0 -#define MEMSCRUB_OPTIONS_LOOPMODE_ENABLE CONFIG_LOOP -#define MEMSCRUB_OPTIONS_LOOPMODE_DISABLE 0 -#define MEMSCRUB_OPTIONS_SECONDARY_MEMRANGE_ENABLE CONFIG_SERA -#define MEMSCRUB_OPTIONS_SECONDARY_MEMRANGE_DISABLE 0 - -/* Scrubbing modes */ -extern int memscrub_init_start(uint32_t value, uint8_t delay, int options); -extern int memscrub_scrub_start(uint8_t delay, int options); -extern int memscrub_regen_start(uint8_t delay, int options); -extern int memscrub_stop(void); -extern int memscrub_active(void); - -/* Set/get memory ranges */ -extern int memscrub_range_set(uint32_t start, uint32_t end); -extern int memscrub_range_get(uint32_t * start, uint32_t * end); -extern int memscrub_secondary_range_set(uint32_t start, uint32_t end); -extern int memscrub_secondary_range_get(uint32_t * start, uint32_t * end); - -/* Interrupts */ -/* MEMSCRUB Interrupts */ -/* Function Interrupt-Code ISR callback prototype. - * arg - Custom arg provided by user - * access - AHB Access that failed - * ahbstatus - AHB status register of the MEMSCRUB core - * status - status register of the MEMSCRUB core - */ -typedef void (*memscrub_isr_t)(void *arg, uint32_t ahbaccess, - uint32_t ahbstatus, uint32_t scrubstatus); -extern int memscrub_isr_register(memscrub_isr_t isr, void * data); -extern int memscrub_isr_unregister(void); - -extern int memscrub_error_status(uint32_t *ahbaccess, uint32_t *ahbstatus, - uint32_t *scrubstatus); - -/* Set the different error thresholds. */ - -/* - * MEMORYSCRUBBER AHBS register fields - */ -#define AHBS_CECNT_BIT 22 -#define AHBS_UECNT_BIT 14 -#define AHBS_DONE_BIT 13 -#define AHBS_SEC_BIT 11 -#define AHBS_SBC_BIT 10 -#define AHBS_CE_BIT 9 -#define AHBS_NE_BIT 8 -#define AHBS_HW_BIT 7 -#define AHBS_HM_BIT 3 -#define AHBS_HS_BIT 0 - -#define AHBS_CECNT (0x3ff << AHBS_CECNT_BIT) -#define AHBS_UECNT (0xff << AHBS_UECNT_BIT) -#define AHBS_DONE (1 << AHBS_DONE_BIT) -#define AHBS_SEC (1 << AHBS_SEC_BIT) -#define AHBS_SBC (1 << AHBS_SBC_BIT) -#define AHBS_CE (1 << AHBS_CE_BIT) -#define AHBS_NE (1 << AHBS_NE_BIT) -#define AHBS_HW (1 << AHBS_HW_BIT) -#define AHBS_HM (0xf << AHBS_HM_BIT) -#define AHBS_HS (0x7 << AHBS_HS_BIT) - -/* - * MEMORYSCRUBBER STAT register fields - */ -#define STAT_RUNCOUNT_BIT 22 -#define STAT_BLKCOUNT_BIT 14 -#define STAT_DONE_BIT 13 -#define STAT_BURSTLEN_BIT 1 -#define STAT_ACTIVE_BIT 0 - -#define STAT_RUNCOUNT (0x3ff << STAT_RUNCOUNT_BIT) -#define STAT_BLKCOUNT (0xff << STAT_BLKCOUNT_BIT) -#define STAT_DONE (0x1 << STAT_DONE_BIT) -#define STAT_BURSTLEN (0xf << STAT_BURSTLEN_BIT) -#define STAT_ACTIVE (0x1 << STAT_ACTIVE_BIT) - -/* - * MEMORYSCRUBBER AHBERC register fields - */ -#define AHBERC_CECNTT_BIT 22 -#define AHBERC_UECNTT_BIT 14 -#define AHBERC_CECTE_BIT 1 -#define AHBERC_UECTE_BIT 0 - -#define AHBERC_CECNTT (0x3ff << AHBERC_CECNTT_BIT) -#define AHBERC_UECNTT (0xff << AHBERC_UECNTT_BIT) -#define AHBERC_CECTE (0x1 << AHBERC_CECTE_BIT) -#define AHBERC_UECTE (0x1 << AHBERC_UECTE_BIT) - -/* - * MEMORYSCRUBBER ETHRES register fields - */ -#define ETHRES_RECT_BIT 22 -#define ETHRES_BECT_BIT 14 -#define ETHRES_RECTE_BIT 1 -#define ETHRES_BECTE_BIT 0 - -#define ETHRES_RECT (0x3ff << ETHRES_RECT_BIT) -#define ETHRES_BECT (0xff << ETHRES_BECT_BIT) -#define ETHRES_RECTE (0x1 << ETHRES_RECTE_BIT) -#define ETHRES_BECTE (0x1 << ETHRES_BECTE_BIT) - -#define MEMSCRUB_OPTIONS_AHBERROR_CORTHRES_ENABLE AHBERC_CECTE -#define MEMSCRUB_OPTIONS_AHBERROR_CORTHRES_DISABLE 0 -#define MEMSCRUB_OPTIONS_AHBERROR_UNCORTHRES_ENABLE AHBERC_UECTE -#define MEMSCRUB_OPTIONS_AHBERROR_UNCORTHRES_DISABLE 0 -#define MEMSCRUB_OPTIONS_SCRUBERROR_RUNTHRES_ENABLE ETHRES_RECTE -#define MEMSCRUB_OPTIONS_SCRUBERROR_RUNTHRES_DISABLE 0 -#define MEMSCRUB_OPTIONS_SCRUBERROR_BLOCKTHRES_ENABLE ETHRES_BECTE -#define MEMSCRUB_OPTIONS_SCRUBERROR_BLOCKTHRES_DISABLE 0 -extern int memscrub_ahberror_setup(int uethres, int cethres, int options); -extern int memscrub_scruberror_setup(int blkthres, int runthres, - int options); - -extern int memscrub_scrub_position(uint32_t * position); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/network_interface_add.h b/c/src/lib/libbsp/sparc/shared/include/network_interface_add.h deleted file mode 100644 index b04a96f003..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/network_interface_add.h +++ /dev/null @@ -1,47 +0,0 @@ -/* Network interface register help function - * - * COPYRIGHT (c) 2008. - * Cobham Gaisler AB. - * - * This function adds a network interface to the - * rtems_bsdnet_config.ifconfig linked list of interfaces. - * The interface configuration is taken from the user defined - * array interface_configs. This function is useful for PnP - * systems when an unknown number of interfaces are available. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __NETWORK_INTERFACE_ADD_H__ -#define __NETWORK_INTERFACE_ADD_H__ - -#include <rtems/rtems_bsdnet.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Interface configuration description */ -struct ethernet_config { - char *ip_addr; /* IP address */ - char *ip_netmask; /* IP Netmask */ - char eth_adr[6]; /* Ethernet hardware MAC address */ -}; - -/* Array with configurations for all interfaces in the system - * Must be defined by the user. - */ -extern struct ethernet_config interface_configs[]; - -/* Routine adding interface to rtems_bsdnet_config.ifconfig linked - * list of interfaces. - */ -int network_interface_add(struct rtems_bsdnet_ifconfig *interface); - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_NETWORKCONFIG_H_ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/occan.h b/c/src/lib/libbsp/sparc/shared/include/occan.h deleted file mode 100644 index 0bf34dee48..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/occan.h +++ /dev/null @@ -1,165 +0,0 @@ -/** - * @file - * @ingroup can - * @brief Gaisler wrapper to OpenCores CAN - driver interface - */ - -/* - * COPYRIGHT (c) 2007. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __OCCAN_DRIVER_H__ -#define __OCCAN_DRIVER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* CAN MESSAGE */ -typedef struct { - char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */ - char rtr; /* RTR - Remote Transmission Request */ - char sshot; /* single shot */ - unsigned char len; - unsigned char data[8]; - unsigned int id; -} CANMsg; - -typedef struct { - /* tx/rx stats */ - unsigned int rx_msgs; - unsigned int tx_msgs; - - /* Error Interrupt counters */ - unsigned int err_warn; - unsigned int err_dovr; - unsigned int err_errp; - unsigned int err_arb; - unsigned int err_bus; - - /**** BUS ERRORS (err_arb) ****/ - - /* ALC 4-0 */ - unsigned int err_arb_bitnum[32]; /* At what bit arbitration is lost */ - - /******************************/ - - /**** BUS ERRORS (err_bus) ****/ - - /* ECC 7-6 */ - unsigned int err_bus_bit; /* Bit error */ - unsigned int err_bus_form; /* Form Error */ - unsigned int err_bus_stuff; /* Stuff Error */ - unsigned int err_bus_other; /* Other Error */ - - /* ECC 5 */ - unsigned int err_bus_rx; /* Errors during Reception */ - unsigned int err_bus_tx; /* Errors during Transmission */ - - /* ECC 4:0 */ - unsigned int err_bus_segs[32]; /* Segment (Where in frame error occured) - * See OCCAN_SEG_* defines for indexes - */ - - /******************************/ - - - /* total number of interrupts */ - unsigned int ints; - - /* software monitoring hw errors */ - unsigned int tx_buf_error; - - /* Software fifo overrun */ - unsigned int rx_sw_dovr; - -} occan_stats; - -/* indexes into occan_stats.err_bus_segs[index] */ -#define OCCAN_SEG_ID28 0x02 /* ID field bit 28:21 */ -#define OCCAN_SEG_ID20 0x06 /* ID field bit 20:18 */ -#define OCCAN_SEG_ID17 0x07 /* ID field bit 17:13 */ -#define OCCAN_SEG_ID12 0x0f /* ID field bit 12:5 */ -#define OCCAN_SEG_ID4 0x0e /* ID field bit 4:0 */ - -#define OCCAN_SEG_START 0x03 /* Start of Frame */ -#define OCCAN_SEG_SRTR 0x04 /* Bit SRTR */ -#define OCCAN_SEG_IDE 0x05 /* Bit IDE */ -#define OCCAN_SEG_RTR 0x0c /* Bit RTR */ -#define OCCAN_SEG_RSV0 0x09 /* Reserved bit 0 */ -#define OCCAN_SEG_RSV1 0x0d /* Reserved bit 1 */ - -#define OCCAN_SEG_DLEN 0x0b /* Data Length code */ -#define OCCAN_SEG_DFIELD 0x0a /* Data Field */ - -#define OCCAN_SEG_CRC_SEQ 0x08 /* CRC Sequence */ -#define OCCAN_SEG_CRC_DELIM 0x18 /* CRC Delimiter */ - -#define OCCAN_SEG_ACK_SLOT 0x19 /* Acknowledge slot */ -#define OCCAN_SEG_ACK_DELIM 0x1b /* Acknowledge delimiter */ -#define OCCAN_SEG_EOF 0x1a /* End Of Frame */ -#define OCCAN_SEG_INTERMISSION 0x12 /* Intermission */ -#define OCCAN_SEG_ACT_ERR 0x11 /* Active error flag */ -#define OCCAN_SEG_PASS_ERR 0x16 /* Passive error flag */ -#define OCCAN_SEG_DOMINANT 0x13 /* Tolerate dominant bits */ -#define OCCAN_SEG_EDELIM 0x17 /* Error delimiter */ -#define OCCAN_SEG_OVERLOAD 0x1c /* overload flag */ - - -#define CANMSG_OPT_RTR 0x40 /* RTR Frame */ -#define CANMSG_OPT_EXTENDED 0x80 /* Exteneded frame */ -#define CANMSG_OPT_SSHOT 0x01 /* Single Shot, no retry */ - -#define OCCAN_IOC_START 1 -#define OCCAN_IOC_STOP 2 - -#define OCCAN_IOC_GET_CONF 3 -#define OCCAN_IOC_GET_STATS 4 -#define OCCAN_IOC_GET_STATUS 5 - -#define OCCAN_IOC_SET_SPEED 6 -#define OCCAN_IOC_SPEED_AUTO 7 -#define OCCAN_IOC_SET_LINK 8 -#define OCCAN_IOC_SET_FILTER 9 -#define OCCAN_IOC_SET_BLK_MODE 10 -#define OCCAN_IOC_SET_BUFLEN 11 -#define OCCAN_IOC_SET_BTRS 12 - - -struct occan_afilter { - unsigned char code[4]; - unsigned char mask[4]; - int single_mode; -}; - -#define OCCAN_STATUS_RESET 0x01 -#define OCCAN_STATUS_OVERRUN 0x02 -#define OCCAN_STATUS_WARN 0x04 -#define OCCAN_STATUS_ERR_PASSIVE 0x08 -#define OCCAN_STATUS_ERR_BUSOFF 0x10 -#define OCCAN_STATUS_QUEUE_ERROR 0x80 - -#define OCCAN_BLK_MODE_RX 0x1 -#define OCCAN_BLK_MODE_TX 0x2 - -void occan_register_drv (void); - - -#define OCCAN_SPEED_500K 500000 -#define OCCAN_SPEED_250K 250000 -#define OCCAN_SPEED_125K 125000 -#define OCCAN_SPEED_75K 75000 -#define OCCAN_SPEED_50K 50000 -#define OCCAN_SPEED_25K 25000 -#define OCCAN_SPEED_10K 10000 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/pcif.h b/c/src/lib/libbsp/sparc/shared/include/pcif.h deleted file mode 100644 index 0221fcdd50..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/pcif.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef __PCIF_H__ -#define __PCIF_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Register the PCIF PCI host driver to the Driver Manager */ -extern void pcif_register_drv(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/satcan.h b/c/src/lib/libbsp/sparc/shared/include/satcan.h deleted file mode 100644 index ab9f5e0cd4..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/satcan.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Header file for RTEMS SATCAN FPGA driver - * - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __SATCAN_H__ -#define __SATCAN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Config structure passed to SatCAN_init(..) */ -typedef struct { - /* Configuration */ - int nodeno; - int dps; - /* Callback functions */ - void (*ahb_irq_callback)(void); - void (*pps_irq_callback)(void); - void (*m5_irq_callback)(void); - void (*m4_irq_callback)(void); - void (*m3_irq_callback)(void); - void (*m2_irq_callback)(void); - void (*m1_irq_callback)(void); - void (*sync_irq_callback)(void); - void (*can_irq_callback)(unsigned int fifo); -} satcan_config; - -#define SATCAN_HEADER_SIZE 4 -#define SATCAN_HEADER_NMM_POS 3 -#define SATCAN_PAYLOAD_SIZE 8 - -/* SatCAN message */ -typedef struct { - unsigned char header[SATCAN_HEADER_SIZE]; /* Header of SatCAN message */ - unsigned char payload[SATCAN_PAYLOAD_SIZE]; /* Payload of SatCAN message */ -} satcan_msg; - -/* SatCAN modify register structure */ -typedef struct { - unsigned int reg; - unsigned int val; -} satcan_regmod; - -/* Driver interface */ -int satcan_register(satcan_config *conf); - -/* SatCAN interrupt IDs */ -#define SATCAN_IRQ_NONACT_TO_ACT 0 -#define SATCAN_IRQ_ACTIVE_TO_NONACT 1 -#define SATCAN_IRQ_STR1_TO_DPS 2 -#define SATCAN_IRQ_DPS_TO_STR1 3 -#define SATCAN_IRQ_STR2_TO_DPS 4 -#define SATCAN_IRQ_DPS_TO_STR2 5 -#define SATCAN_IRQ_STR3_TO_DPS 6 -#define SATCAN_IRQ_DPS_TO_STR3 7 -#define SATCAN_IRQ_PLD1_TO_DPS 8 -#define SATCAN_IRQ_DPS_TO_PLD1 9 -#define SATCAN_IRQ_PLD2_TO_DPS 10 -#define SATCAN_IRQ_DPS_TO_PLD2 11 -#define SATCAN_IRQ_SYNC 16 -#define SATCAN_IRQ_TIME_MARKER1 17 -#define SATCAN_IRQ_TIME_MARKER2 18 -#define SATCAN_IRQ_TIME_MARKER3 19 -#define SATCAN_IRQ_TIME_MARKER4 20 -#define SATCAN_IRQ_TIME_MARKER5 21 -#define SATCAN_IRQ_EOD1 22 -#define SATCAN_IRQ_EOD2 23 -#define SATCAN_IRQ_TOD 24 -#define SATCAN_IRQ_CRITICAL 25 - -/* IOC */ -#define SATCAN_IOC_DMA_2K 1 /* Use DMA area for 2K messages */ -#define SATCAN_IOC_DMA_8K 2 /* Use DMA area for 8K messages */ -#define SATCAN_IOC_GET_REG 3 /* Provides direct read access to all core registers */ -#define SATCAN_IOC_SET_REG 4 /* Provides direct write access to all core registers */ -#define SATCAN_IOC_OR_REG 5 /* Provides direct read access to all core registers */ -#define SATCAN_IOC_AND_REG 6 /* Provides direct write access to all core registers */ -#define SATCAN_IOC_EN_TX1_DIS_TX2 7 /* Enable DMA TX channel 1, Disable DMA TX channel 2 */ -#define SATCAN_IOC_EN_TX2_DIS_TX1 8 /* Enable DMA TX channel 2, Disable DMA TX channel 1 */ -#define SATCAN_IOC_GET_DMA_MODE 9 /* Returns the current DMA mode */ -#define SATCAN_IOC_SET_DMA_MODE 10 /* Sets the DMA mode */ -#define SATCAN_IOC_ACTIVATE_DMA 11 /* Directly activate DMA channel */ -#define SATCAN_IOC_DEACTIVATE_DMA 12 /* Directly deactivate DMA channel */ -#define SATCAN_IOC_DMA_STATUS 13 /* Returns status of directly activated DMA */ -#define SATCAN_IOC_GET_DOFFSET 14 /* Get TX DMA offset */ -#define SATCAN_IOC_SET_DOFFSET 15 /* Set TX DMA offset */ -#define SATCAN_IOC_GET_TIMEOUT 16 /* Set TX DMA timeout */ -#define SATCAN_IOC_SET_TIMEOUT 17 /* Get TX DMA timeout */ - - -/* Values used to select core register with IOC_SET_REG/IOC_GET_REG */ -#define SATCAN_SWRES 0 /* Software reset */ -#define SATCAN_INT_EN 1 /* Interrupt enable */ -#define SATCAN_FIFO 3 /* FIFO read */ -#define SATCAN_FIFO_RES 4 /* FIFO reset */ -#define SATCAN_TSTAMP 5 /* Current time stamp */ -#define SATCAN_CMD0 6 /* Command register 0 */ -#define SATCAN_CMD1 7 /* Command register 1 */ -#define SATCAN_START_CTC 8 /* Start cycle time counter */ -#define SATCAN_RAM_BASE 9 /* RAM offset address */ -#define SATCAN_STOP_CTC 10 /* Stop cycle time counter / DPS active status */ -#define SATCAN_DPS_ACT 10 /* Stop cycle time counter / DPS active status */ -#define SATCAN_PLL_RST 11 /* DPLL reset */ -#define SATCAN_PLL_CMD 12 /* DPLL command */ -#define SATCAN_PLL_STAT 13 /* DPLL status */ -#define SATCAN_PLL_OFF 14 /* DPLL offset */ -#define SATCAN_DMA 15 /* DMA channel enable */ -#define SATCAN_DMA_TX_1_CUR 16 /* DMA channel 1 TX current address */ -#define SATCAN_DMA_TX_1_END 17 /* DMA channel 1 TX end address */ -#define SATCAN_DMA_TX_2_CUR 18 /* DMA channel 2 TX current address */ -#define SATCAN_DMA_TX_2_END 19 /* DMA channel 2 TX end address */ -#define SATCAN_RX 20 /* CAN RX enable / Filter start ID */ -#define SATCAN_FILTER_START 20 /* CAN RX enable / Filter start ID */ -#define SATCAN_FILTER_SETUP 21 /* Filter setup / Filter stop ID */ -#define SATCAN_FILTER_STOP 21 /* Filter setup / Filter stop ID */ -#define SATCAN_WCTRL 32 /* Wrapper status/control register */ -#define SATCAN_WIPEND 33 /* Wrapper interrupt pending register */ -#define SATCAN_WIMASK 34 /* Wrapper interrupt mask register */ -#define SATCAN_WAHBADDR 35 /* Wrapper AHB address register */ - - -/* Values used to communicate DMA mode */ -#define SATCAN_DMA_MODE_USER 0 -#define SATCAN_DMA_MODE_SYSTEM 1 - -/* Values used to directly activate DMA channel */ -#define SATCAN_DMA_ENABLE_TX1 1 -#define SATCAN_DMA_ENABLE_TX2 2 - -#ifdef __cplusplus -} -#endif - -#endif /* __SATCAN_H__ */ diff --git a/c/src/lib/libbsp/sparc/shared/include/spictrl.h b/c/src/lib/libbsp/sparc/shared/include/spictrl.h deleted file mode 100644 index 98922fbd30..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/spictrl.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * SPICTRL SPI Driver interface. - * - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __SPICTRL_H__ -#define __SPICTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -extern void spictrl_register_drv (void); - -/*** REGISTER LAYOUT ***/ -struct spictrl_regs { - volatile unsigned int capability; /* 0x00 */ - volatile unsigned int resv[7]; /* 0x04 */ - volatile unsigned int mode; /* 0x20 */ - volatile unsigned int event; /* 0x24 */ - volatile unsigned int mask; /* 0x28 */ - volatile unsigned int command; /* 0x2c */ - volatile unsigned int tx; /* 0x30 */ - volatile unsigned int rx; /* 0x34 */ - volatile unsigned int slvsel; /* 0x38 */ - volatile unsigned int am_slvsel; /* 0x3c */ - volatile unsigned int am_cfg; /* 0x40 */ - volatile unsigned int am_period; /* 0x44 */ - int reserved0[2]; - volatile unsigned int am_mask[4]; /* 0x50-0x5C */ - int reserved1[(0x200-0x60)/4]; - volatile unsigned int am_tx[128]; /* 0x200-0x3FC */ - volatile unsigned int am_rx[128]; /* 0x400-0x5FC */ -}; - -/* -- About automated periodic transfer mode -- - * - * Core must support this feature. - * - * The SPI core must be configured in periodic mode before - * writing the data into the transfer FIFO which will be used - * mutiple times in different transfers, it will also make - * the receive FIFO to be updated. - * - * In periodic mode the following sequence is performed, - * 1. start() - * 2. ioctl(CONFIG, &config) - Enable periodic mode - * 3. set_address() - * 4. write() - Fills TX FIFO, this has some constraints - * 5. ioctl(START) - Starts the periodic transmission of the TX FIFO - * 6. read() - Read one response of the tranistted data. It will - * hang until data is available. If hanging is not an - * options use ioctl(STATUS) - * 7. go back to 6. - * - * 8. ioctl(STOP) - Stop to set up a new periodic or normal transfer - * 9. stop() - * - * Note that the the read length must equal the total write length. - */ - -/* Custom SPICTRL driver ioctl commands */ -#define SPICTRL_IOCTL_PERIOD_START 5000 /* Start automated periodic transfer mode */ -#define SPICTRL_IOCTL_PERIOD_STOP 5001 /* Stop to SPI core from doing periodic transfers */ -#define SPICTRL_IOCTL_CONFIG 5002 /* Configure Periodic transfer mode (before calling write() and START) */ -#define SPICTRL_IOCTL_STATUS 5003 /* Get status */ - -#define SPICTRL_IOCTL_PERIOD_READ 5005 /* Write transmit registers and mask register - * (only in automatic periodic mode) - * Note that it is probably prefferred to read - * the received words using the read() using - * operations instead. - */ -#define SPICTRL_IOCTL_PERIOD_WRITE 5006 /* Read receive registers and mask register - * (only in automatic periodic mode) */ -#define SPICTRL_IOCTL_REGS 5007 /* Get SPICTRL Register */ - -/* SPICTRL_IOCTL_CONFIG argument */ -struct spictrl_ioctl_config { - int clock_gap; /* Clock GAP between */ - unsigned int flags; /* Normal mode flags */ - int periodic_mode; /* 1=Enables Automated periodic transfers if supported by hardware */ - unsigned int period; /* Number of clocks between automated transfers are started */ - unsigned int period_flags; /* Options */ - unsigned int period_slvsel; /* Slave Select when transfer is not active, default is 0xffffffff */ -}; -#define SPICTRL_FLAGS_TAC 0x10 - -#define SPICTRL_PERIOD_FLAGS_ERPT 0x80 /* Trigger start-period from external signal */ -#define SPICTRL_PERIOD_FLAGS_SEQ 0x40 -#define SPICTRL_PERIOD_FLAGS_STRICT 0x20 -#define SPICTRL_PERIOD_FLAGS_OVTB 0x10 -#define SPICTRL_PERIOD_FLAGS_OVDB 0x08 -#define SPICTRL_PERIOD_FLAGS_ASEL 0x04 -#define SPICTRL_PERIOD_FLAGS_EACT 0x01 - -/* SPICTRL_IOCTL_PERIOD_READ and SPICTRL_IOCTL_PERIOD_WRITE Argument data structure - * - * Note that the order of reading the mask registers are different for read/write - * operation. See options notes. - */ -struct spictrl_period_io { - int options; /* READ: bit0=Read Mask Registers into masks[]. - * bit1=Read Receive registers according to masks[] - * (after reading masks). - * - * WRITE: bit0=Update Mask accoring to masks[]. - * bit1=Update Transmit registers according to masks[]. - * (before reading masks) - */ - unsigned int masks[4]; - - void *data; /* Data read sequentially according to masks[] bit. */ -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/spwcuc.h b/c/src/lib/libbsp/sparc/shared/include/spwcuc.h deleted file mode 100644 index e420367640..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/spwcuc.h +++ /dev/null @@ -1,188 +0,0 @@ -/* SPWCUC - SpaceWire - CCSDS unsegmented Code Transfer Protocol GRLIB core - * register driver interface. - * - * COPYRIGHT (c) 2009. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __SPWCUC_H__ -#define __SPWCUC_H__ - -#define PKT_INIT_IRQ 0x1 -#define PKT_ERR_IRQ 0x2 -#define PKT_RX_IRQ 0x4 -#define WRAP_ERR_IRQ 0x8 -#define WRAP_IRQ 0x10 -#define SYNC_ERR_IRQ 0x20 -#define SYNC_IRQ 0x40 -#define TOL_ERR_IRQ 0x80 -#define TICK_RX_ERR_IRQ 0x100 -#define TICK_RX_WRAP_IRQ 0x200 -#define TICK_RX_IRQ 0x400 -#define TICK_TX_WRAP_IRQ 0x800 -#define TICK_TX_IRQ 0x1000 - -/* SPWCUC Register layout */ -struct spwcuc_regs { - volatile unsigned int config; /* 00 */ - volatile unsigned int status; /* 04 */ - volatile unsigned int control; /* 08 */ - volatile unsigned int unused0; /* 0c */ - volatile unsigned int dla; /* 10 */ - volatile unsigned int pid; /* 14 */ - volatile unsigned int offset; /* 18 */ - volatile unsigned int unused1; /* 1c */ - volatile unsigned int pkt_ct; /* 20 */ - volatile unsigned int pkt_ft; /* 24 */ - volatile unsigned int pkt_pf_crc; /* 28 */ - volatile unsigned int unused2; /* 2c */ - volatile unsigned int etct; /* 30 */ - volatile unsigned int etft; /* 34 */ - volatile unsigned int etct_next; /* 38 */ - volatile unsigned int etft_next; /* 3c */ - volatile unsigned int unused3[8]; /* 40-5c */ - volatile unsigned int pimsr; /* 60 */ - volatile unsigned int pimr; /* 64 */ - volatile unsigned int pisr; /* 68 */ - volatile unsigned int pir; /* 6c */ - volatile unsigned int imr; /* 70 */ - volatile unsigned int picr; /* 74 */ -}; - -struct spwcuc_cfg { - unsigned char sel_out; /* Bits 3-0 enable time code transmission on respective output */ - unsigned char sel_in; /* Select SpW to receive time codes on, 0-3 */ - unsigned char mapping; /* Define mapping of time code time info into T-field, 0-31 */ - unsigned char tolerance; /* Define SpaceWire time code reception tolerance, 0-31 */ - unsigned char tid; /* Define CUC P-Field time code identification, 1 = Level 1, 2 = Level 2 */ - unsigned char ctf; /* If 1 check time code flags to be all zero */ - unsigned char cp; /* If 1 check P-Field time code id against tid */ - - unsigned char txen; /* Enable SpaceWire time code transmission */ - unsigned char rxen; /* Enable SpaceWire time code reception */ - unsigned char pktsyncen; /* Enable SpaceWire time CUC packet sync */ - unsigned char pktiniten; /* Enable SpaceWire time CUC packet init */ - unsigned char pktrxen; /* Enable SpaceWire time CUC packet reception */ - - unsigned char dla; /* SpaceWire destination logical address */ - unsigned char dla_mask; /* SpaceWire destination logical address mask */ - unsigned char pid; /* SpaceWire protocol ID */ - - unsigned int offset; /* Packet reception offset */ -}; - -/* SPWCUC Statistics gathered by driver */ -struct spwcuc_stats { - - /* IRQ Stats */ - unsigned int nirqs; - unsigned int tick_tx; - unsigned int tick_tx_wrap; - unsigned int tick_rx; - unsigned int tick_rx_wrap; - unsigned int tick_rx_error; - unsigned int tolerr; - unsigned int sync; - unsigned int syncerr; - unsigned int wrap; - unsigned int wraperr; - unsigned int pkt_rx; - unsigned int pkt_err; - unsigned int pkt_init; -}; - -/* Function ISR callback prototype - * - * pimr - PIMR/PIR register of the SPWCUC core read by ISR - * data - Custom data provided by user - */ -typedef void (*spwcuc_isr_t)(unsigned int pimr, void *data); - -/* Open a SPWCUC device by minor number. A SPWCUC device can only by opened - * once. The handle returned must be used as the input parameter 'spwcuc' in - * the rest of the calls in the function interface. - */ -extern void *spwcuc_open(int minor); - -/* Close a previously opened SPWCUC device */ -extern void spwcuc_close(void *spwcuc); - -/* Reset SPWCUC Core */ -extern int spwcuc_reset(void *spwcuc); - -/* Enable Interrupts at Interrupt controller */ -extern void spwcuc_int_enable(void *spwcuc); - -/* Disable Interrupts at Interrupt controller */ -extern void spwcuc_int_disable(void *spwcuc); - -/* Clear Statistics gathered by the driver */ -extern void spwcuc_clr_stats(void *spwcuc); - -/* Get Statistics gathered by the driver. The statistics are stored into - * the location pointed to by 'stats'. - */ -extern void spwcuc_get_stats(void *spwcuc, struct spwcuc_stats *stats); - -/* Register an Interrupt handler and custom data, the function call is - * removed by setting func to NULL. - * - * The driver's interrupt handler is installed on open(), however the user - * callback called from the driver's ISR is installed using this function. - */ -extern void spwcuc_int_register(void *spwcuc, spwcuc_isr_t func, void *data); - -/* Configure the spwcuc core. The configuration is taken from the data - * structure pointed to by 'cfg'. See data structure spwcuc_cfg fields. - */ -extern void spwcuc_config(void *spwcuc, struct spwcuc_cfg *cfg); - -/* Return elapsed coarse time */ -extern unsigned int spwcuc_get_et_coarse(void *spwcuc); - -/* Return elapsed fine time */ -extern unsigned int spwcuc_get_et_fine(void *spwcuc); - -/* Return elapsed time (coarse and fine) 64-bit value */ -extern unsigned long long spwcuc_get_et(void *spwcuc); - -/* Return next elapsed coarse time (for use when sending SpW time packet) */ -extern unsigned int spwcuc_get_next_et_coarse(void *spwcuc); - -/* Return next elapsed fine time (for use when sending SpW time packet) */ -extern unsigned int spwcuc_get_next_et_fine(void *spwcuc); - -/* Return next elapsed time (for use when sending SpW time packet) */ -extern unsigned long long spwcuc_get_next_et(void *spwcuc); - -/* Force/Set the elapsed time (coarse 32-bit and fine 24-bit) by writing the - * T-Field Time Packet Registers then the FORCE bit. - */ -extern void spwcuc_force_et(void *spwcuc, unsigned long long time); - -/* Return received (from time packet) elapsed coarse time */ -extern unsigned int spwcuc_get_tp_et_coarse(void *spwcuc); - -/* Return received (from time packet) elapsed fine time */ -extern unsigned int spwcuc_get_tp_et_fine(void *spwcuc); - -/* Return received (from time packet) elapsed time (coarse and fine) */ -extern unsigned long long spwcuc_get_tp_et(void *spwcuc); - -/* Clear interrupts */ -extern void spwcuc_clear_irqs(void *spwcuc, int irqs); - -/* Enable interrupts */ -extern void spwcuc_enable_irqs(void *spwcuc, int irqs); - -/* Get Register */ -extern struct spwcuc_regs *spwcuc_get_regs(void *spwcuc); - -/* Register the SPWCUC Driver to the Driver Manager */ -extern void spwcuc_register(void); - -#endif diff --git a/c/src/lib/libbsp/sparc/shared/include/tlib.h b/c/src/lib/libbsp/sparc/shared/include/tlib.h deleted file mode 100644 index debb8c8215..0000000000 --- a/c/src/lib/libbsp/sparc/shared/include/tlib.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Timer Library (TLIB) - * - * The Library rely on timer drivers, the timer presented by the - * timer driver must look like a down-counter timer, which generates - * interrupt (if configured) when underflown. - * - * If Timer hardware is an up-counter the Timer driver must recalculate - * into values that would match as if it was a down-counter. - * - * COPYRIGHT (c) 2011. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __TLIB_H__ -#define __TLIB_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -struct tlib_dev; - -typedef void (*tlib_isr_t)(void *data); - -enum { - TLIB_FLAGS_BROADCAST = 0x01 -}; - -struct tlib_drv { - /*** Functions ***/ - void (*reset)(struct tlib_dev *hand); - void (*get_freq)( - struct tlib_dev *hand, - unsigned int *basefreq, - unsigned int *tickrate); - int (*set_freq)(struct tlib_dev *hand, unsigned int tickrate); - void (*irq_reg)(struct tlib_dev *hand, tlib_isr_t func, void *data, int flags); - void (*irq_unreg)(struct tlib_dev *hand, tlib_isr_t func,void *data); - void (*start)(struct tlib_dev *hand, int once); - void (*stop)(struct tlib_dev *hand); - void (*restart)(struct tlib_dev *hand); - void (*get_counter)(struct tlib_dev *hand, unsigned int *counter); - int (*custom)(struct tlib_dev *hand, int cmd, void *arg); - int (*int_pend)(struct tlib_dev *hand, int ack); - void (*get_widthmask)(struct tlib_dev *hand, unsigned int *widthmask); -}; - -struct tlib_dev { - struct tlib_dev *next; - char status; /* 0=closed, 1=open, 2=timer started */ - char index; /* Timer Index */ - tlib_isr_t isr_func; - void *isr_data; - struct tlib_drv *drv; -}; - -#ifdef RTEMS_DRVMGR_STARTUP -/* Clock Driver Timer register function. Only used when the TLIB-Clock - * driver is used. A specific Timer is registered as the System Clock - * timer. - */ -extern void Clock_timer_register(int timer_number); -#endif - -/* Register Timer. Called by Timer Drivers in order to register - * a Timer to the Timer Library. The registration order determines - * the Timer Number used in tlib_open() to identify a specific - * Timer. - */ -extern int tlib_dev_reg(struct tlib_dev *newdev); - -/* Allocate a Timer. - * - * A Timer handle is returned identifying the timer in later calls. - */ -extern void *tlib_open(int timer_no); - -/* Close Timer */ -extern void tlib_close(void *hand); - -/* Returns Number of Timers currently registered to Timer Library */ -extern int tlib_ntimer(void); - -static inline void tlib_reset(void *hand) -{ - struct tlib_dev *dev = hand; - - dev->drv->reset(dev); -} -/* Get Frequencies: - * - Base Frequency (unchangable base freq rate of timer, prescaler, clkinput) - * - Current Tick Rate [in multiples of Base Frequency] - */ -static inline void tlib_get_freq( - void *hand, - unsigned int *basefreq, - unsigned int *tickrate) -{ - struct tlib_dev *dev = hand; - - dev->drv->get_freq(dev, basefreq, tickrate); -} - -/* Set current Tick Rate in number of "Base-Frequency ticks" */ -static inline int tlib_set_freq(void *hand, unsigned int tickrate) -{ - struct tlib_dev *dev = hand; - - return dev->drv->set_freq(dev, tickrate); -} - -/* Register ISR at Timer ISR */ -static inline void tlib_irq_unregister(void *hand) -{ - struct tlib_dev *dev = hand; - - if ( dev->isr_func ) { - dev->drv->irq_unreg(dev, dev->isr_func, dev->isr_data); - dev->isr_func = NULL; - } -} - -/* Register ISR at Timer ISR */ -static inline void tlib_irq_register(void *hand, tlib_isr_t func, void *data, int flags) -{ - struct tlib_dev *dev = hand; - - /* Unregister previous ISR if installed */ - tlib_irq_unregister(hand); - dev->isr_func = func; - dev->isr_data = data; - dev->drv->irq_reg(dev, func, data, flags); -} - -/* Start Timer, ISRs will be generated if enabled. - * - * once determines if timer should restart (=0) on underflow automatically, - * or stop when underflow is reached (=1). - */ -static inline void tlib_start(void *hand, int once) -{ - struct tlib_dev *dev = hand; - - dev->drv->start(dev, once); -} - -/* Stop Timer, no more ISRs will be generated */ -static inline void tlib_stop(void *hand) -{ - struct tlib_dev *dev = hand; - - dev->drv->stop(dev); -} - -/* Restart/Reload Timer, may be usefull if a Watchdog Timer */ -static inline void tlib_restart(void *hand) -{ - struct tlib_dev *dev = hand; - - dev->drv->restart(dev); -} - -/* Get current counter value (since last tick) */ -static inline void tlib_get_counter(void *hand, unsigned int *counter) -{ - struct tlib_dev *dev = hand; - - dev->drv->get_counter(dev, counter); -} - -/* Do a custom operation */ -static inline void tlib_custom(void *hand, int cmd, void *arg) -{ - struct tlib_dev *dev = hand; - - dev->drv->custom(dev, cmd, arg); -} - -static inline int tlib_interrupt_pending(void *hand, int ack) -{ - struct tlib_dev *dev = hand; - - return dev->drv->int_pend(dev, ack); -} - -static inline void tlib_get_widthmask(void *hand, unsigned int *widthmask) -{ - struct tlib_dev *dev = hand; - - dev->drv->get_widthmask(dev, widthmask); -} - -#ifdef __cplusplus -} -#endif - -#endif |