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-rw-r--r--c/src/lib/libbsp/powerpc/virtex/Makefile.am23
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/configure.ac4
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/include/bsp.h84
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/include/opbintctrl.h75
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/include/tm27.h1
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/include/xparameters_dflt.h192
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/irq/irq.h94
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/network/xiltemac.h375
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/preinstall.am100
-rw-r--r--c/src/lib/libbsp/powerpc/virtex/startup/bsp_specs (renamed from c/src/lib/libbsp/powerpc/virtex/bsp_specs)0
10 files changed, 6 insertions, 942 deletions
diff --git a/c/src/lib/libbsp/powerpc/virtex/Makefile.am b/c/src/lib/libbsp/powerpc/virtex/Makefile.am
index 9b6de34f50..232ec7b190 100644
--- a/c/src/lib/libbsp/powerpc/virtex/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/virtex/Makefile.am
@@ -4,29 +4,16 @@ EXTRA_DIST =
include $(top_srcdir)/../../../../automake/compile.am
include $(top_srcdir)/../../bsp.am
-include_bspdir = $(includedir)/bsp
+dist_project_lib_DATA = startup/bsp_specs
-dist_project_lib_DATA = bsp_specs
-
-include_HEADERS = include/bsp.h
-include_HEADERS += include/tm27.h
-include_HEADERS += include/xparameters_dflt.h
if HAS_NETWORKING
-include_HEADERS += network/xiltemac.h
endif
-nodist_include_HEADERS = include/bspopts.h
-nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
-
-include_bsp_HEADERS =
-
DISTCLEANFILES = include/bspopts.h
noinst_PROGRAMS =
-include_bsp_HEADERS += ../shared/include/linker-symbols.h
-
EXTRA_DIST += start/start.S
start.$(OBJEXT): start/start.S
$(CPPASCOMPILE) -o $@ -c $<
@@ -38,7 +25,7 @@ rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S
project_lib_DATA += rtems_crti.$(OBJEXT)
# Link commands
-project_lib_DATA += startup/linkcmds
+project_lib_DATA += linkcmds
dist_project_lib_DATA += ../shared/startup/linkcmds.base
noinst_LIBRARIES = libbsp.a
@@ -60,10 +47,6 @@ libbsp_a_SOURCES += console/consolelite.c ../../shared/console.c \
../../shared/console_read.c ../../shared/console_write.c
# irq
-include_bsp_HEADERS += ../../shared/include/irq-generic.h
-include_bsp_HEADERS += ../../shared/include/irq-info.h
-include_bsp_HEADERS += include/opbintctrl.h
-include_bsp_HEADERS += irq/irq.h
libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c
libbsp_a_SOURCES += ../../shared/src/irq-generic.c
libbsp_a_SOURCES += ../../shared/src/irq-info.c
@@ -98,5 +81,5 @@ if HAS_NETWORKING
libbsp_a_LIBADD += network.rel
endif
-include $(srcdir)/preinstall.am
include $(top_srcdir)/../../../../automake/local.am
+include $(srcdir)/../../../../../../bsps/powerpc/virtex/headers.am
diff --git a/c/src/lib/libbsp/powerpc/virtex/configure.ac b/c/src/lib/libbsp/powerpc/virtex/configure.ac
index 323d9759ed..8c910b5b3a 100644
--- a/c/src/lib/libbsp/powerpc/virtex/configure.ac
+++ b/c/src/lib/libbsp/powerpc/virtex/configure.ac
@@ -4,6 +4,8 @@ AC_PREREQ([2.69])
AC_INIT([rtems-c-src-lib-libbsp-powerpc-virtex],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
AC_CONFIG_SRCDIR([make/custom/virtex.cfg])
RTEMS_TOP(../../../../../..)
+RTEMS_SOURCE_TOP
+RTEMS_BUILD_TOP
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
@@ -45,7 +47,7 @@ RTEMS_BSP_CLEANUP_OPTIONS
# Explicitly list all Makefiles here
AC_CONFIG_FILES([
Makefile
-startup/linkcmds
+linkcmds:startup/linkcmds.in
])
RTEMS_PPC_EXCEPTIONS
diff --git a/c/src/lib/libbsp/powerpc/virtex/include/bsp.h b/c/src/lib/libbsp/powerpc/virtex/include/bsp.h
deleted file mode 100644
index 2f61ee2517..0000000000
--- a/c/src/lib/libbsp/powerpc/virtex/include/bsp.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* bsp.h
- *
- * This include file contains all GEN405 board IO definitions.
- *
- * derived from helas403/include/bsp.h:
- * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp
- * Author: Thomas Doerfler <td@imd.m.isar.de>
- * IMD Ingenieurbuero fuer Microcomputertechnik
- *
- * COPYRIGHT (c) 1998 by IMD
- *
- * Changes from IMD are covered by the original distributions terms.
- * This file has been derived from the papyrus BSP.
- *
- * Author: Andrew Bray <andy@i-cubed.co.uk>
- *
- * COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of i-cubed limited not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * i-cubed limited makes no representations about the suitability
- * of this software for any purpose.
- *
- * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef LIBBSP_POWERPC_VIRTEX_BSP_H
-#define LIBBSP_POWERPC_VIRTEX_BSP_H
-
-#include <bspopts.h>
-
-#ifdef ASM
-/* Definition of where to store registers in alignment handler */
-#define ALIGN_REGS 0x0140
-
-#else
-#include <rtems.h>
-#include <bsp/irq.h>
-#include <bsp/vectors.h>
-#include <bsp/default-initial-extension.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define BSP_FEATURE_IRQ_EXTENSION
-
-#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN
-
-/* miscellaneous stuff assumed to exist */
-extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */
-
-/* Network Defines */
-#if 1 /* EB/doe changes */
-#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
-#else
-#include "xiltemac.h"
-#define RTEMS_BSP_NETWORK_DRIVER_NAME XILTEMAC_DRIVER_PREFIX
-#endif
-struct rtems_bsdnet_ifconfig;
-extern int xilTemac_driver_attach(struct rtems_bsdnet_ifconfig*, int );
-#define RTEMS_BSP_NETWORK_DRIVER_ATTACH xilTemac_driver_attach
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ASM */
-
-#endif
diff --git a/c/src/lib/libbsp/powerpc/virtex/include/opbintctrl.h b/c/src/lib/libbsp/powerpc/virtex/include/opbintctrl.h
deleted file mode 100644
index 4ade0e48f8..0000000000
--- a/c/src/lib/libbsp/powerpc/virtex/include/opbintctrl.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* opbintctrl.h
- *
- * This file contains definitions and declarations for the
- * Xilinx Off Processor Bus (OPB) Interrupt Controller
- *
- * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
- * COPYRIGHT (c) 2005 by Linn Products Ltd, Scotland
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _INCLUDE_OPBINTCTRL_H
-#define _INCLUDE_OPBINTCTRL_H
-
-#include <rtems.h>
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-#include <rtems/irq.h>
-#include <bspopts.h>
-#include RTEMS_XPARAMETERS_H
-
-#define USE_GREG_INTERRUPTS
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* extern XIntc InterruptController;
- */
-
-
-/* Maximum number of IRQs. Defined in vhdl model */
-#define OPB_INTC_IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
-
-/* Width of INTC registers. Defined in vhdl model */
-#define OPB_INTC_REGISTER_WIDTH 32
-
-/* Base Register address and register offsets. Defined in vhdl model */
-#define OPB_INTC_BASE XPAR_INTC_SINGLE_BASEADDR
-
-
-
-
-
-/* Interrupt Status Register */
-#define OPB_INTC_ISR 0x0
-/* Interrupt Pending Register (ISR && IER) */
-#define OPB_INTC_IPR 0x4
-/* Interrupt Enable Register */
-#define OPB_INTC_IER 0x8
-/* Interrupt Acknowledge Register */
-#define OPB_INTC_IAR 0xC
-/* Set Interrupt Enable (same as read/mask/write to IER) */
-#define OPB_INTC_SIE 0x10
-/* Clear Interrupt Enable (same as read/mask/write to IER) */
-#define OPB_INTC_CIE 0x14
-/* Interrupt Vector Address (highest priority vector number from IPR) */
-#define OPB_INTC_IVR 0x18
-/* Master Enable Register */
-#define OPB_INTC_MER 0x1C
-
-/* Master Enable Register: Hardware Interrupt Enable */
-#define OPB_INTC_MER_HIE 0x2
-
-/* Master Enable Register: Master IRQ Enable */
-#define OPB_INTC_MER_ME 0x1
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _INCLUDE_OPBINTCTRL_H */
diff --git a/c/src/lib/libbsp/powerpc/virtex/include/tm27.h b/c/src/lib/libbsp/powerpc/virtex/include/tm27.h
deleted file mode 100644
index 0dfa7bf628..0000000000
--- a/c/src/lib/libbsp/powerpc/virtex/include/tm27.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <rtems/tm27-default.h>
diff --git a/c/src/lib/libbsp/powerpc/virtex/include/xparameters_dflt.h b/c/src/lib/libbsp/powerpc/virtex/include/xparameters_dflt.h
deleted file mode 100644
index b31cb26fe8..0000000000
--- a/c/src/lib/libbsp/powerpc/virtex/include/xparameters_dflt.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by libgen.
-* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
-* DO NOT EDIT.
-*
-* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
-*
-* Description: Driver parameters
-*
-*******************************************************************/
-
-#define STDIN_BASEADDRESS 0x40600000
-#define STDOUT_BASEADDRESS 0x40600000
-
-/******************************************************************/
-
-/* Definitions for driver PLBARB */
-#define XPAR_XPLBARB_NUM_INSTANCES 1
-
-/* Definitions for peripheral PLB */
-#define XPAR_PLB_BASEADDR 0x00000000
-#define XPAR_PLB_HIGHADDR 0x00000000
-#define XPAR_PLB_DEVICE_ID 0
-#define XPAR_PLB_PLB_NUM_MASTERS 3
-
-
-/******************************************************************/
-
-/* Definitions for driver OPBARB */
-#define XPAR_XOPBARB_NUM_INSTANCES 1
-
-/* Definitions for peripheral OPB */
-#define XPAR_OPB_BASEADDR 0xFFFFFFFF
-#define XPAR_OPB_HIGHADDR 0x00000000
-#define XPAR_OPB_DEVICE_ID 0
-#define XPAR_OPB_NUM_MASTERS 1
-
-
-/******************************************************************/
-
-/* Definitions for driver UARTLITE */
-#define XPAR_XUARTLITE_NUM_INSTANCES 1
-
-/* Definitions for peripheral CONSOLE */
-#define XPAR_CONSOLE_BASEADDR 0x40600000
-#define XPAR_CONSOLE_HIGHADDR 0x4060FFFF
-#define XPAR_CONSOLE_DEVICE_ID 0
-#define XPAR_CONSOLE_BAUDRATE 115200
-#define XPAR_CONSOLE_USE_PARITY 0
-#define XPAR_CONSOLE_ODD_PARITY 0
-#define XPAR_CONSOLE_DATA_BITS 8
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIO */
-#define XPAR_XGPIO_NUM_INSTANCES 3
-
-/* Definitions for peripheral LEDS */
-#define XPAR_LEDS_BASEADDR 0x40000000
-#define XPAR_LEDS_HIGHADDR 0x4000FFFF
-#define XPAR_LEDS_DEVICE_ID 0
-#define XPAR_LEDS_INTERRUPT_PRESENT 0
-#define XPAR_LEDS_IS_DUAL 0
-
-
-/* Definitions for peripheral PBLEDS */
-#define XPAR_PBLEDS_BASEADDR 0x40020000
-#define XPAR_PBLEDS_HIGHADDR 0x4002FFFF
-#define XPAR_PBLEDS_DEVICE_ID 1
-#define XPAR_PBLEDS_INTERRUPT_PRESENT 0
-#define XPAR_PBLEDS_IS_DUAL 0
-
-
-/* Definitions for peripheral PUSHBUTTONS */
-#define XPAR_PUSHBUTTONS_BASEADDR 0x40040000
-#define XPAR_PUSHBUTTONS_HIGHADDR 0x4004FFFF
-#define XPAR_PUSHBUTTONS_DEVICE_ID 2
-#define XPAR_PUSHBUTTONS_INTERRUPT_PRESENT 1
-#define XPAR_PUSHBUTTONS_IS_DUAL 0
-
-
-/******************************************************************/
-
-/* Definitions for driver TMRCTR */
-#define XPAR_XTMRCTR_NUM_INSTANCES 1
-
-/* Definitions for peripheral OPBTIMER */
-#define XPAR_OPBTIMER_BASEADDR 0x41C00000
-#define XPAR_OPBTIMER_HIGHADDR 0x41C0FFFF
-#define XPAR_OPBTIMER_DEVICE_ID 0
-
-
-/******************************************************************/
-
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_XINTC_USE_DCR 0
-/* Definitions for driver INTC */
-#define XPAR_XINTC_NUM_INSTANCES 1
-
-/* Definitions for peripheral INTC */
-#define XPAR_INTC_BASEADDR 0x41200000
-#define XPAR_INTC_HIGHADDR 0x4120FFFF
-#define XPAR_INTC_DEVICE_ID 0
-#define XPAR_INTC_KIND_OF_INTR 0x00000000
-
-
-/******************************************************************/
-
-#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
-#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
-#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_INTC_DEVICE_ID
-#define XPAR_OPBTIMER_INTERRUPT_MASK 0X000001
-#define XPAR_INTC_OPBTIMER_INTERRUPT_INTR 0
-#define XPAR_ETHERNET_IP2INTC_IRPT_MASK 0X000002
-#define XPAR_INTC_ETHERNET_IP2INTC_IRPT_INTR 1
-#define XPAR_PUSHBUTTONS_IP2INTC_IRPT_MASK 0X000004
-#define XPAR_INTC_PUSHBUTTONS_IP2INTC_IRPT_INTR 2
-
-/******************************************************************/
-
-/* Definitions for driver DDR */
-#define XPAR_XDDR_NUM_INSTANCES 1
-
-/* Definitions for peripheral DDR_SDRAM_64MX32 */
-#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF
-#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000
-#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0
-#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0
-
-
-/******************************************************************/
-
-/* Definitions for peripheral DDR_SDRAM_64MX32 */
-#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000
-#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF
-
-/******************************************************************/
-
-
-/* Definitions for peripheral HARD_TEMAC_0 */
-#define XPAR_HARD_TEMAC_0_PHY_TYPE 1
-
-
-/******************************************************************/
-
-/* Definitions for driver TEMAC */
-#define XPAR_XTEMAC_NUM_INSTANCES 1
-
-/* Definitions for peripheral ETHERNET */
-#define XPAR_ETHERNET_DEVICE_ID 0
-#define XPAR_ETHERNET_BASEADDR 0x81200000
-#define XPAR_ETHERNET_HIGHADDR 0x8120FFFF
-#define XPAR_ETHERNET_RXFIFO_DEPTH 32768
-#define XPAR_ETHERNET_TXFIFO_DEPTH 32768
-#define XPAR_ETHERNET_MAC_FIFO_DEPTH 64
-#define XPAR_ETHERNET_DMA_TYPE 1
-#define XPAR_ETHERNET_TX_DRE_TYPE 0
-#define XPAR_ETHERNET_RX_DRE_TYPE 0
-#define XPAR_ETHERNET_INCLUDE_TX_CSUM 0
-#define XPAR_ETHERNET_INCLUDE_RX_CSUM 0
-
-
-/******************************************************************/
-
-
-/* Definitions for peripheral FLASH */
-#define XPAR_FLASH_NUM_BANKS_MEM 1
-
-
-/******************************************************************/
-
-/* Definitions for peripheral FLASH */
-#define XPAR_FLASH_MEM0_BASEADDR 0x06000000
-#define XPAR_FLASH_MEM0_HIGHADDR 0x067FFFFF
-
-/******************************************************************/
-
-
-/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
-#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000
-#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff
-
-
-/******************************************************************/
-
-#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
-
-/******************************************************************/
-
diff --git a/c/src/lib/libbsp/powerpc/virtex/irq/irq.h b/c/src/lib/libbsp/powerpc/virtex/irq/irq.h
deleted file mode 100644
index 1ce5b68b98..0000000000
--- a/c/src/lib/libbsp/powerpc/virtex/irq/irq.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*===============================================================*\
-| Project: RTEMS virtex BSP |
-+-----------------------------------------------------------------+
-| Copyright (c) 2007 |
-| Embedded Brains GmbH |
-| Obere Lagerstr. 30 |
-| D-82178 Puchheim |
-| Germany |
-| rtems@embedded-brains.de |
-+-----------------------------------------------------------------+
-| The license and distribution terms for this file may be |
-| found in the file LICENSE in this distribution or at |
-| |
-| http://www.rtems.org/license/LICENSE. |
-| |
-+-----------------------------------------------------------------+
-| this file declares constants of the interrupt controller |
-\*===============================================================*/
-#ifndef VIRTEX_IRQ_IRQ_H
-#define VIRTEX_IRQ_IRQ_H
-
-#include <rtems/irq.h>
-#include <rtems/irq-extension.h>
-#include <bsp/opbintctrl.h>
-
-/*
- * the following definitions specify the indices used
- * to interface the interrupt handler API
- */
-
-/*
- * Peripheral IRQ handlers related definitions
- */
-#define BSP_OPBINTC_PER_IRQ_NUMBER XPAR_INTC_MAX_NUM_INTR_INPUTS
-#define BSP_OPBINTC_IRQ_LOWEST_OFFSET 0
-#define BSP_OPBINTC_IRQ_MAX_OFFSET (BSP_OPBINTC_IRQ_LOWEST_OFFSET\
- +BSP_OPBINTC_PER_IRQ_NUMBER-1)
-
-#define BSP_IS_OPBINTC_IRQ(irqnum) \
- (((irqnum) >= BSP_OPBINTC_IRQ_LOWEST_OFFSET) && \
- ((irqnum) <= BSP_OPBINTC_IRQ_MAX_OFFSET))
-/*
- * Processor IRQ handlers related definitions
- */
-#define BSP_PROCESSOR_IRQ_NUMBER 3
-#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_OPBINTC_IRQ_MAX_OFFSET+1)
-#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
- +BSP_PROCESSOR_IRQ_NUMBER-1)
-
-#define BSP_IS_PROCESSOR_IRQ(irqnum) \
- (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \
- ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
-/*
- * Summary
- */
-#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
-#define BSP_LOWEST_OFFSET BSP_OPBINTC_IRQ_LOWEST_OFFSET
-#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET
-
-#define BSP_IS_VALID_IRQ(irqnum) \
- (BSP_IS_PROCESSOR_IRQ(irqnum) \
- || BSP_IS_OPBINTC_IRQ(irqnum))
-
-#define BSP_INTERRUPT_VECTOR_MIN 0
-#define BSP_INTERRUPT_VECTOR_MAX BSP_PROCESSOR_IRQ_MAX_OFFSET
-
-#ifndef ASM
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * index table for the module specific handlers, a few entries are only placeholders
- */
- typedef enum {
- BSP_OPBINTC_IRQ_FIRST = BSP_OPBINTC_IRQ_LOWEST_OFFSET,
- /*
- * Note: for this BSP, the peripheral names are derived
- * from the Xilinx parameter file
- */
- BSP_OPBINTC_IRQ_LAST = BSP_OPBINTC_IRQ_MAX_OFFSET,
- BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0,
- BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1,
- BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
- } rtems_irq_symbolic_name;
-
-#define BSP_OPBINTC_XPAR(xname) (BSP_OPBINTC_IRQ_LOWEST_OFFSET+xname)
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* ASM */
-
-#endif /* VIRTEX_IRQ_IRQ_H */
diff --git a/c/src/lib/libbsp/powerpc/virtex/network/xiltemac.h b/c/src/lib/libbsp/powerpc/virtex/network/xiltemac.h
deleted file mode 100644
index 185b89bdc1..0000000000
--- a/c/src/lib/libbsp/powerpc/virtex/network/xiltemac.h
+++ /dev/null
@@ -1,375 +0,0 @@
-/*
- * Driver for plb inteface of the xilinx temac 3.00a
- *
- * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
- * Copyright (c) 2007 Linn Products Ltd, Scotland.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef _XILINX_TEMAC_
-#define _XILINX_TEMAC_
-#include <rtems/irq.h>
-
-
-#define XILTEMAC_DRIVER_PREFIX "xiltemac"
-
-#define DRIVER_PREFIX XILTEMAC_DRIVER_PREFIX
-
-
-/** IPIF interrupt and reset registers
- */
-#define XTE_DISR_OFFSET 0x00000000 /**< Device interrupt status */
-#define XTE_DIPR_OFFSET 0x00000004 /**< Device interrupt pending */
-#define XTE_DIER_OFFSET 0x00000008 /**< Device interrupt enable */
-#define XTE_DIIR_OFFSET 0x00000018 /**< Device interrupt ID */
-#define XTE_DGIE_OFFSET 0x0000001C /**< Device global interrupt enable */
-#define XTE_IPISR_OFFSET 0x00000020 /**< IP interrupt status */
-#define XTE_IPIER_OFFSET 0x00000028 /**< IP interrupt enable */
-#define XTE_DSR_OFFSET 0x00000040 /**< Device software reset (write) */
-
-/** IPIF transmit fifo
- */
-#define XTE_PFIFO_TX_BASE_OFFSET 0x00002000 /**< Packet FIFO Tx channel */
-#define XTE_PFIFO_TX_VACANCY_OFFSET 0x00002004 /**< Packet Fifo Tx Vacancy */
-#define XTE_PFIFO_TX_DATA_OFFSET 0x00002100 /**< IPIF Tx packet fifo port */
-
-/** IPIF receive fifo
- */
-#define XTE_PFIFO_RX_BASE_OFFSET 0x00002010 /**< Packet FIFO Rx channel */
-#define XTE_PFIFO_RX_VACANCY_OFFSET 0x00002014 /**< Packet Fifo Rx Vacancy */
-#define XTE_PFIFO_RX_DATA_OFFSET 0x00002200 /**< IPIF Rx packet fifo port */
-
-/** IPIF fifo masks
- */
-#define XTE_PFIFO_COUNT_MASK 0x00FFFFFF
-
-/** IPIF transmit and recieve DMA offsets
- */
-#define XTE_DMA_SEND_OFFSET 0x00002300 /**< DMA Tx channel */
-#define XTE_DMA_RECV_OFFSET 0x00002340 /**< DMA Rx channel */
-
-/** IPIF IPIC_TO_TEMAC Core Registers
- */
-#define XTE_CR_OFFSET 0x00001000 /**< Control */
-#define XTE_TPLR_OFFSET 0x00001004 /**< Tx packet length (FIFO) */
-#define XTE_TSR_OFFSET 0x00001008 /**< Tx status (FIFO) */
-#define XTE_RPLR_OFFSET 0x0000100C /**< Rx packet length (FIFO) */
-#define XTE_RSR_OFFSET 0x00001010 /**< Receive status */
-#define XTE_IFGP_OFFSET 0x00001014 /**< Interframe gap */
-#define XTE_TPPR_OFFSET 0x00001018 /**< Tx pause packet */
-
-/** TEMAC Core Registers
- * These are registers defined within the device's hard core located in the
- * processor block. They are accessed with the host interface. These registers
- * are addressed offset by XTE_HOST_IPIF_OFFSET or by the DCR base address
- * if so configured.
- */
-#define XTE_HOST_IPIF_OFFSET 0x00003000 /**< Offset of host registers when
- memory mapped into IPIF */
-#define XTE_ERXC0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000200) /**< Rx configuration word 0 */
-#define XTE_ERXC1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000240) /**< Rx configuration word 1 */
-#define XTE_ETXC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000280) /**< Tx configuration */
-#define XTE_EFCC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000002C0) /**< Flow control configuration */
-#define XTE_ECFG_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000300) /**< EMAC configuration */
-#define XTE_EGMIC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000320) /**< RGMII/SGMII configuration */
-#define XTE_EMC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000340) /**< Management configuration */
-#define XTE_EUAW0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000380) /**< Unicast address word 0 */
-#define XTE_EUAW1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000384) /**< Unicast address word 1 */
-#define XTE_EMAW0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000388) /**< Multicast address word 0 */
-#define XTE_EMAW1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x0000038C) /**< Multicast address word 1 */
-#define XTE_EAFM_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000390) /**< Promisciuous mode */
-#define XTE_EIRS_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003A0) /**< IRstatus */
-#define XTE_EIREN_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003A4) /**< IRenable */
-#define XTE_EMIID_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003B0) /**< MIIMwrData */
-#define XTE_EMIIC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003B4) /**< MiiMcnt */
-
-/* Register masks. The following constants define bit locations of various
- * control bits in the registers. Constants are not defined for those registers
- * that have a single bit field representing all 32 bits. For further
- * information on the meaning of the various bit masks, refer to the HW spec.
- */
-
-/** Interrupt status bits for top level interrupts
- * These bits are associated with the XTE_DISR_OFFSET, XTE_DIPR_OFFSET,
- * and XTE_DIER_OFFSET registers.
- */
-#define XTE_DXR_SEND_FIFO_MASK 0x00000040 /**< Send FIFO channel */
-#define XTE_DXR_RECV_FIFO_MASK 0x00000020 /**< Receive FIFO channel */
-#define XTE_DXR_RECV_DMA_MASK 0x00000010 /**< Receive DMA channel */
-#define XTE_DXR_SEND_DMA_MASK 0x00000008 /**< Send DMA channel */
-#define XTE_DXR_CORE_MASK 0x00000004 /**< Core */
-#define XTE_DXR_DPTO_MASK 0x00000002 /**< Data phase timeout */
-#define XTE_DXR_TERR_MASK 0x00000001 /**< Transaction error */
-
-/** Interrupt status bits for MAC interrupts
- * These bits are associated with XTE_IPISR_OFFSET and XTE_IPIER_OFFSET
- * registers.
- */
-#define XTE_IPXR_XMIT_DONE_MASK 0x00000001 /**< Tx complete */
-#define XTE_IPXR_RECV_DONE_MASK 0x00000002 /**< Rx complete */
-#define XTE_IPXR_AUTO_NEG_MASK 0x00000004 /**< Auto negotiation complete */
-#define XTE_IPXR_RECV_REJECT_MASK 0x00000008 /**< Rx packet rejected */
-#define XTE_IPXR_XMIT_SFIFO_EMPTY_MASK 0x00000010 /**< Tx status fifo empty */
-#define XTE_IPXR_RECV_LFIFO_EMPTY_MASK 0x00000020 /**< Rx length fifo empty */
-#define XTE_IPXR_XMIT_LFIFO_FULL_MASK 0x00000040 /**< Tx length fifo full */
-#define XTE_IPXR_RECV_LFIFO_OVER_MASK 0x00000080 /**< Rx length fifo overrun
- Note that this signal is
- no longer asserted by HW
- */
-#define XTE_IPXR_RECV_LFIFO_UNDER_MASK 0x00000100 /**< Rx length fifo underrun */
-#define XTE_IPXR_XMIT_SFIFO_OVER_MASK 0x00000200 /**< Tx status fifo overrun */
-#define XTE_IPXR_XMIT_SFIFO_UNDER_MASK 0x00000400 /**< Tx status fifo underrun */
-#define XTE_IPXR_XMIT_LFIFO_OVER_MASK 0x00000800 /**< Tx length fifo overrun */
-#define XTE_IPXR_XMIT_LFIFO_UNDER_MASK 0x00001000 /**< Tx length fifo underrun */
-#define XTE_IPXR_RECV_PFIFO_ABORT_MASK 0x00002000 /**< Rx packet rejected due to
- full packet FIFO */
-#define XTE_IPXR_RECV_LFIFO_ABORT_MASK 0x00004000 /**< Rx packet rejected due to
- full length FIFO */
-
-#define XTE_IPXR_RECV_DROPPED_MASK \
- (XTE_IPXR_RECV_REJECT_MASK | \
- XTE_IPXR_RECV_PFIFO_ABORT_MASK | \
- XTE_IPXR_RECV_LFIFO_ABORT_MASK) /**< IPXR bits that indicate a dropped
- receive frame */
-#define XTE_IPXR_XMIT_ERROR_MASK \
- (XTE_IPXR_XMIT_SFIFO_OVER_MASK | \
- XTE_IPXR_XMIT_SFIFO_UNDER_MASK | \
- XTE_IPXR_XMIT_LFIFO_OVER_MASK | \
- XTE_IPXR_XMIT_LFIFO_UNDER_MASK) /**< IPXR bits that indicate transmit
- errors */
-
-#define XTE_IPXR_RECV_ERROR_MASK \
- (XTE_IPXR_RECV_DROPPED_MASK | \
- XTE_IPXR_RECV_LFIFO_UNDER_MASK) /**< IPXR bits that indicate receive
- errors */
-
-#define XTE_IPXR_FIFO_FATAL_ERROR_MASK \
- (XTE_IPXR_XMIT_SFIFO_OVER_MASK | \
- XTE_IPXR_XMIT_SFIFO_UNDER_MASK | \
- XTE_IPXR_XMIT_LFIFO_OVER_MASK | \
- XTE_IPXR_XMIT_LFIFO_UNDER_MASK | \
- XTE_IPXR_RECV_LFIFO_UNDER_MASK) /**< IPXR bits that indicate errors with
- one of the length or status FIFOs
- that is fatal in nature. These bits
- can only be cleared by a device
- reset */
-
-/** Software reset register (DSR)
- */
-#define XTE_DSR_RESET_MASK 0x0000000A /**< Write this value to DSR to
- reset entire core */
-
-
-/** Global interrupt enable register (DGIE)
- */
-#define XTE_DGIE_ENABLE_MASK 0x80000000 /**< Write this value to DGIE to
- enable interrupts from this
- device */
-
-/** Control Register (CR)
- */
-#define XTE_CR_HTRST_MASK 0x00000008 /**< Reset hard temac */
-#define XTE_CR_BCREJ_MASK 0x00000004 /**< Disable broadcast address
- filtering */
-#define XTE_CR_MCREJ_MASK 0x00000002 /**< Disable multicast address
- filtering */
-#define XTE_CR_HDUPLEX_MASK 0x00000001 /**< Enable half duplex operation */
-
-
-/** Transmit Packet Length Register (TPLR)
- */
-#define XTE_TPLR_TXPL_MASK 0x00003FFF /**< Tx packet length in bytes */
-
-
-/** Transmit Status Register (TSR)
- */
-#define XTE_TSR_TXED_MASK 0x80000000 /**< Excess deferral error */
-#define XTE_TSR_PFIFOU_MASK 0x40000000 /**< Packet FIFO underrun */
-#define XTE_TSR_TXA_MASK 0x3E000000 /**< Transmission attempts */
-#define XTE_TSR_TXLC_MASK 0x01000000 /**< Late collision error */
-#define XTE_TSR_TPCF_MASK 0x00000001 /**< Transmit packet complete
- flag */
-
-#define XTE_TSR_ERROR_MASK \
- (XTE_TSR_TXED_MASK | \
- XTE_TSR_PFIFOU_MASK | \
- XTE_TSR_TXLC_MASK) /**< TSR bits that indicate an
- error */
-
-
-/** Receive Packet Length Register (RPLR)
- */
-#define XTE_RPLR_RXPL_MASK 0x00003FFF /**< Rx packet length in bytes */
-
-
-/** Receive Status Register (RSR)
- */
-#define XTE_RSR_RPCF_MASK 0x00000001 /**< Receive packet complete
- flag */
-
-/** Interframe Gap Register (IFG)
- */
-#define XTE_IFG_IFGD_MASK 0x000000FF /**< IFG delay */
-
-
-/** Transmit Pause Packet Register (TPPR)
- */
-#define XTE_TPPR_TPPD_MASK 0x0000FFFF /**< Tx pause packet data */
-
-
-/** Receiver Configuration Word 1 (ERXC1)
- */
-#define XTE_ERXC1_RXRST_MASK 0x80000000 /**< Receiver reset */
-#define XTE_ERXC1_RXJMBO_MASK 0x40000000 /**< Jumbo frame enable */
-#define XTE_ERXC1_RXFCS_MASK 0x20000000 /**< FCS not stripped */
-#define XTE_ERXC1_RXEN_MASK 0x10000000 /**< Receiver enable */
-#define XTE_ERXC1_RXVLAN_MASK 0x08000000 /**< VLAN enable */
-#define XTE_ERXC1_RXHD_MASK 0x04000000 /**< Half duplex */
-#define XTE_ERXC1_RXLT_MASK 0x02000000 /**< Length/type check disable */
-#define XTE_ERXC1_ERXC1_MASK 0x0000FFFF /**< Pause frame source address
- bits [47:32]. Bits [31:0]
- are stored in register
- ERXC0 */
-
-
-/** Transmitter Configuration (ETXC)
- */
-#define XTE_ETXC_TXRST_MASK 0x80000000 /**< Transmitter reset */
-#define XTE_ETXC_TXJMBO_MASK 0x40000000 /**< Jumbo frame enable */
-#define XTE_ETXC_TXFCS_MASK 0x20000000 /**< Generate FCS */
-#define XTE_ETXC_TXEN_MASK 0x10000000 /**< Transmitter enable */
-#define XTE_ETXC_TXVLAN_MASK 0x08000000 /**< VLAN enable */
-#define XTE_ETXC_TXHD_MASK 0x04000000 /**< Half duplex */
-#define XTE_ETXC_TXIFG_MASK 0x02000000 /**< IFG adjust enable */
-
-
-/** Flow Control Configuration (EFCC)
- */
-#define XTE_EFCC_TXFLO_MASK 0x40000000 /**< Tx flow control enable */
-#define XTE_EFCC_RXFLO_MASK 0x20000000 /**< Rx flow control enable */
-
-
-/** EMAC Configuration (ECFG)
- */
-#define XTE_ECFG_LINKSPD_MASK 0xC0000000 /**< Link speed */
-#define XTE_ECFG_RGMII_MASK 0x20000000 /**< RGMII mode enable */
-#define XTE_ECFG_SGMII_MASK 0x10000000 /**< SGMII mode enable */
-#define XTE_ECFG_1000BASEX_MASK 0x08000000 /**< 1000BaseX mode enable */
-#define XTE_ECFG_HOSTEN_MASK 0x04000000 /**< Host interface enable */
-#define XTE_ECFG_TX16BIT 0x02000000 /**< 16 bit Tx client enable */
-#define XTE_ECFG_RX16BIT 0x01000000 /**< 16 bit Rx client enable */
-
-#define XTE_ECFG_LINKSPD_10 0x00000000 /**< XTE_ECFG_LINKSPD_MASK for
- 10 Mbit */
-#define XTE_ECFG_LINKSPD_100 0x40000000 /**< XTE_ECFG_LINKSPD_MASK for
- 100 Mbit */
-#define XTE_ECFG_LINKSPD_1000 0x80000000 /**< XTE_ECFG_LINKSPD_MASK for
- 1000 Mbit */
-
-/** EMAC RGMII/SGMII Configuration (EGMIC)
- */
-#define XTE_EGMIC_RGLINKSPD_MASK 0xC0000000 /**< RGMII link speed */
-#define XTE_EGMIC_SGLINKSPD_MASK 0x0000000C /**< SGMII link speed */
-#define XTE_EGMIC_RGSTATUS_MASK 0x00000002 /**< RGMII link status */
-#define XTE_EGMIC_RGHALFDUPLEX_MASK 0x00000001 /**< RGMII half duplex */
-
-#define XTE_EGMIC_RGLINKSPD_10 0x00000000 /**< XTE_EGMIC_RGLINKSPD_MASK
- for 10 Mbit */
-#define XTE_EGMIC_RGLINKSPD_100 0x40000000 /**< XTE_EGMIC_RGLINKSPD_MASK
- for 100 Mbit */
-#define XTE_EGMIC_RGLINKSPD_1000 0x80000000 /**< XTE_EGMIC_RGLINKSPD_MASK
- for 1000 Mbit */
-#define XTE_EGMIC_SGLINKSPD_10 0x00000000 /**< XTE_SGMIC_RGLINKSPD_MASK
- for 10 Mbit */
-#define XTE_EGMIC_SGLINKSPD_100 0x00000004 /**< XTE_SGMIC_RGLINKSPD_MASK
- for 100 Mbit */
-#define XTE_EGMIC_SGLINKSPD_1000 0x00000008 /**< XTE_SGMIC_RGLINKSPD_MASK
- for 1000 Mbit */
-
-/** EMAC Management Configuration (EMC)
- */
-#define XTE_EMC_MDIO_MASK 0x00000040 /**< MII management enable */
-#define XTE_EMC_CLK_DVD_MAX 0x3F /**< Maximum MDIO divisor */
-
-
-/** EMAC Unicast Address Register Word 1 (EUAW1)
- */
-#define XTE_EUAW1_MASK 0x0000FFFF /**< Station address bits [47:32]
- Station address bits [31:0]
- are stored in register
- EUAW0 */
-
-
-/** EMAC Multicast Address Register Word 1 (EMAW1)
- */
-#define XTE_EMAW1_CAMRNW_MASK 0x00800000 /**< CAM read/write control */
-#define XTE_EMAW1_CAMADDR_MASK 0x00030000 /**< CAM address mask */
-#define XTE_EUAW1_MASK 0x0000FFFF /**< Multicast address bits [47:32]
- Multicast address bits [31:0]
- are stored in register
- EMAW0 */
-#define XTE_EMAW1_CAMMADDR_SHIFT_MASK 16 /**< Number of bits to shift right
- to align with
- XTE_EMAW1_CAMADDR_MASK */
-
-
-/** EMAC Address Filter Mode (EAFM)
- */
-#define XTE_EAFM_EPPRM_MASK 0x80000000 /**< Promiscuous mode enable */
-
-
-/** EMAC MII Management Write Data (EMIID)
- */
-#define XTE_EMIID_MIIMWRDATA_MASK 0x0000FFFF /**< Data port */
-
-
-/** EMAC MII Management Control (EMIIC)
- */
-#define XTE_EMIID_MIIMDECADDR_MASK 0x0000FFFF /**< Address port */
-
-
-struct XilTemacStats
-{
- volatile uint32_t iInterrupts;
-
- volatile uint32_t iRxInterrupts;
- volatile uint32_t iRxRejectedInterrupts;
- volatile uint32_t iRxRejectedInvalidFrame;
- volatile uint32_t iRxRejectedDataFifoFull;
- volatile uint32_t iRxRejectedLengthFifoFull;
- volatile uint32_t iRxMaxDrained;
- volatile uint32_t iRxStrayEvents;
-
- volatile uint32_t iTxInterrupts;
- volatile uint32_t iTxMaxDrained;
-};
-
-#define MAX_UNIT_BYTES 50
-
-struct XilTemac
-{
- struct arpcom iArpcom;
- struct XilTemacStats iStats;
- struct ifnet* iIfp;
-
- char iUnitName[MAX_UNIT_BYTES];
-
- uint32_t iAddr;
- rtems_event_set iIoEvent;
-
- int iIsrVector;
-
-#if PPC_HAS_CLASSIC_EXCEPTIONS
- rtems_isr_entry iOldHandler;
-#else
- rtems_irq_connect_data iOldHandler;
-#endif
- int iIsPresent;
-};
-
-
-#endif /* _XILINX_EMAC_*/
diff --git a/c/src/lib/libbsp/powerpc/virtex/preinstall.am b/c/src/lib/libbsp/powerpc/virtex/preinstall.am
deleted file mode 100644
index 9263f7a4d1..0000000000
--- a/c/src/lib/libbsp/powerpc/virtex/preinstall.am
+++ /dev/null
@@ -1,100 +0,0 @@
-## Automatically generated by ampolish3 - Do not edit
-
-if AMPOLISH3
-$(srcdir)/preinstall.am: Makefile.am
- $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
-endif
-
-PREINSTALL_DIRS =
-DISTCLEANFILES += $(PREINSTALL_DIRS)
-
-all-am: $(PREINSTALL_FILES)
-
-PREINSTALL_FILES =
-CLEANFILES = $(PREINSTALL_FILES)
-
-all-local: $(TMPINSTALL_FILES)
-
-TMPINSTALL_FILES =
-CLEANFILES += $(TMPINSTALL_FILES)
-
-$(PROJECT_LIB)/$(dirstamp):
- @$(MKDIR_P) $(PROJECT_LIB)
- @: > $(PROJECT_LIB)/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
-
-$(PROJECT_INCLUDE)/$(dirstamp):
- @$(MKDIR_P) $(PROJECT_INCLUDE)
- @: > $(PROJECT_INCLUDE)/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
-
-$(PROJECT_INCLUDE)/bsp/$(dirstamp):
- @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
- @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-
-$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
-PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
-
-$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
-
-$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
-
-$(PROJECT_INCLUDE)/xparameters_dflt.h: include/xparameters_dflt.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/xparameters_dflt.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/xparameters_dflt.h
-
-if HAS_NETWORKING
-$(PROJECT_INCLUDE)/xiltemac.h: network/xiltemac.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/xiltemac.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/xiltemac.h
-endif
-$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
-
-$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
-
-$(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h
-
-$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
-TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
-
-$(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
-TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
-
-$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
-TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds
-
-$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
-PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
-
-$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
-
-$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
-
-$(PROJECT_INCLUDE)/bsp/opbintctrl.h: include/opbintctrl.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/opbintctrl.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/opbintctrl.h
-
-$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
-
diff --git a/c/src/lib/libbsp/powerpc/virtex/bsp_specs b/c/src/lib/libbsp/powerpc/virtex/startup/bsp_specs
index 6cb546f392..6cb546f392 100644
--- a/c/src/lib/libbsp/powerpc/virtex/bsp_specs
+++ b/c/src/lib/libbsp/powerpc/virtex/startup/bsp_specs
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-02 19:13:03 +0000