diff options
Diffstat (limited to 'c/src/lib/libbsp/powerpc/score603e/include')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/include/Makefile.in | 38 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/include/bsp.h | 261 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/include/chain.h | 362 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/include/coverhd.h | 139 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/include/gen1.h | 155 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/include/gen2.h | 276 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/score603e/include/tod.h | 38 |
7 files changed, 1269 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/score603e/include/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/include/Makefile.in new file mode 100644 index 0000000000..d206d1d37b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/Makefile.in @@ -0,0 +1,38 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +H_FILES = $(srcdir)/bsp.h $(srcdir)/coverhd.h $(srcdir)/chain.h \ + $(srcdir)/gen1.h $(srcdir)/gen2.h $(srcdir)/tod.h + +# +# Equate files are for including from assembly preprocessed by +# gm4 or gasp. No examples are provided except for those for +# other CPUs. The best way to generate them would be to +# provide a program which generates the constants used based +# on the C equivalents. +# +# If you add equate files, don't forget to uncomment the install line +# below. +# + +EQ_FILES = + +SRCS=$(H_FILES) $(EQ_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: $(SRCS) + $(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE) diff --git a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h new file mode 100644 index 0000000000..2888a1dc9a --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h @@ -0,0 +1,261 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __BSP_h +#define __BSP_h + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include <rtems.h> +#include <console.h> +#include <clockdrv.h> +#include <iosupp.h> + + +#if (SCORE603E_GENERATION == 1) +#include <gen1.h> +#elif (SCORE603E_GENERATION == 2) +#include <gen2.h> +#else +#error "Unknown Generation of Score603e" +#endif + + +/* + * The following macro calculates the Baud constant. For the Z8530 chip. + * + * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 + * for the Score603e ((10,000,000 / 16) / (2 * Baud Rate)) - 2 + */ +#define _Score603e_Z8530_Baud( _frequency, _clock_by, _baud_rate ) \ + ( (_frequency /( _clock_by * 2 * _baud_rate)) - 2) + +#define Score603e_Z8530_Chip1_Baud( _value ) \ + _Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \ + SCORE603E_85C30_1_CLOCK_X, _value ) + +#define Score603e_Z8530_Chip0_Baud( _value ) \ + _Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \ + SCORE603E_85C30_0_CLOCK_X, _value ) + +#define Initialize_Board_ctrl_register() \ + *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \ + SCORE603E_BRD_FLASH_DISABLE_MASK) \ + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( _handler ) \ + set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 ) + +#define Cause_tm27_intr() \ + do { \ + unsigned32 _clicks = 8; \ + asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + + +#define Clear_tm27_intr() \ + do { \ + unsigned32 _clicks = 0xffffffff; \ + asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + unsigned32 _msr = 0; \ + _ISR_Set_level( 0 ); \ + asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + + +/* Constants */ + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + + +/* + * Information placed in the linkcmds file. + */ + +extern int RAM_START; +extern int RAM_END; +extern int RAM_SIZE; + +extern int PROM_START; +extern int PROM_END; +extern int PROM_SIZE; + +extern int CLOCK_SPEED; +extern int CPU_PPC_CLICKS_PER_MS; + +extern int end; /* last address in the program */ + +/* + * How many libio files we want + */ + +#define BSP_LIBIO_MAX_FDS 20 + +/* functions */ + +void bsp_start( void ); + +void bsp_cleanup( void ); + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +/* + * spurious.c + */ +rtems_isr bsp_stub_handler( + rtems_vector_number trap +); +rtems_isr bsp_spurious_handler( + rtems_vector_number trap +); +void bsp_spurious_initialize(); + +/* + * genvec.c + */ +rtems_isr_entry set_EE_vector( + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector /* vector number */ +); +void initialize_external_exception_vector (); + +/* + * console.c + */ +void DEBUG_puts( char *string ); + +void BSP_fatal_return( void ); + +/* + * Hwr_init.c + */ +void init_PCI(); +void instruction_cache_enable (); +void data_cache_enable (); + + +void initialize_PCI_bridge (); +rtems_unsigned16 read_and_clear_irq (); +void set_irq_mask( + rtems_unsigned16 value +); +rtems_unsigned16 get_irq_mask(); + +/* + * universe.c + */ +void initialize_universe(); + +void set_irq_mask( + rtems_unsigned16 value +); + +rtems_unsigned16 get_irq_mask(); + +void unmask_irq( + rtems_unsigned16 irq_idx +); + +void init_irq_data_register(); + +rtems_unsigned16 read_and_clear_PMC_irq( + rtems_unsigned16 irq +); + +rtems_boolean Is_PMC_IRQ( + rtems_unsigned32 pmc_irq, + rtems_unsigned16 status_word +); + +rtems_unsigned16 read_and_clear_irq(); + +/* + * FPGA.c + */ +void initialize_PCI_bridge (); + +/* flash.c */ + +unsigned int SCORE603e_FLASH_Disable( + rtems_unsigned32 unused +); +unsigned int SCORE603e_FLASH_verify_enable(); +unsigned int SCORE603e_FLASH_Enable_writes( + rtems_unsigned32 area /* Unused */ +); + +#define Convert_Endian_32( _data ) \ + ( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) | \ + ((_data&0x00ff0000)>>8) | ((_data&0xff000000)>>24) ) + +#define Convert_Endian_16( _data ) \ + ( ((_data&0x00ff)<<8) | ((_data&0xff00)>>8) ) + +extern rtems_configuration_table BSP_Configuration; /* owned by BSP */ +extern rtems_cpu_table Cpu_table; /* owned by BSP */ +extern rtems_unsigned32 bsp_isr_level; + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/chain.h b/c/src/lib/libbsp/powerpc/score603e/include/chain.h new file mode 100644 index 0000000000..98cf2b1a86 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/chain.h @@ -0,0 +1,362 @@ +/* chain.h + * + * This include file contains all the constants and structures associated + * with doubly linked chains. This file actually just provides an + * interface to the chain object in rtems. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $ld: + */ + +#ifndef __CHAIN_h +#define __CHAIN_h + +#include <rtems.h> + +/* + * Chain_Initialize + * + * This routine initializes the_chain structure to manage the + * contiguous array of number_nodes nodes which starts at + * starting_address. Each node is of node_size bytes. + * + * Chain_Control *the_chain, * IN * + * void *starting_address, * IN * + * rtems_unsigned32 number_nodes, * IN * + * rtems_unsigned32 node_size * IN * + */ + +#define Chain_Initialize( the_chain, starting_address, \ + number_nodes, node_size ) \ + _Chain_Initialize( the_chain, starting_address, \ + number_nodes, node_size ) \ + + +/* + * Chain_Initialize_empty + * + * This routine initializes the specified chain to contain zero nodes. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Initialize_empty( the_chain ) \ + _Chain_Initialize_empty( the_chain ) + + +/* + * Chain_Are_nodes_equal + * + * This function returns TRUE if LEFT and RIGHT are equal, + * and FALSE otherwise. + * + * Chain_Node *left, * IN * + * Chain_Node *right * IN * + */ + +#define Chain_Are_nodes_equal( left, right ) \ + _Chain_Are_nodes_equal( left, right ) + + +/* + * Chain_Extract_unprotected + * + * This routine extracts the_node from the chain on which it resides. + * It does NOT disable interrupts to insure the atomicity of the + * extract operation. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Extract_unprotected( the_node ) \ + _Chain_Extract_unprotected( the_node ) + + +/* + * Chain_Extract + * + * This routine extracts the_node from the chain on which it resides. + * It disables interrupts to insure the atomicity of the + * extract operation. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Extract( the_node ) \ + _Chain_Extract( the_node ) + + +/* + * Chain_Get_unprotected + * + * This function removes the first node from the_chain and returns + * a pointer to that node. If the_chain is empty, then NULL is returned. + * It does NOT disable interrupts to insure the atomicity of the + * get operation. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Get_unprotected( the_chain ) \ + _Chain_Get_unprotected( the_chain ) + + +/* + * Chain_Get + * + * This function removes the first node from the_chain and returns + * a pointer to that node. If the_chain is empty, then NULL is returned. + * It disables interrupts to insure the atomicity of the + * get operation. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Get( the_chain ) \ + _Chain_Get( the_chain ) + + +/* + * Chain_Get_first_unprotected + * + * This function removes the first node from the_chain and returns + * a pointer to that node. It does NOT disable interrupts to insure + * the atomicity of the get operation. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Get_first_unprotected( the_chain ) \ + _Chain_Get_first_unprotected( the_chain ) + + +/* + * Chain_Insert_unprotected + * + * This routine inserts the_node on a chain immediately following + * after_node. It does NOT disable interrupts to insure the atomicity + * of the extract operation. + * + * Chain_Node *after_node, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Insert_unprotected( after_node, the_node ) \ + _Chain_Insert_unprotected( after_node, the_node ) + + +/* + * Chain_Insert + * + * This routine inserts the_node on a chain immediately following + * after_node. It disables interrupts to insure the atomicity + * of the extract operation. + * + * Chain_Node *after_node, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Insert( after_node, the_node ) \ + _Chain_Insert( after_node, the_node ) + + +/* + * Chain_Append_unprotected + * + * This routine appends the_node onto the end of the_chain. + * It does NOT disable interrupts to insure the atomicity of the + * append operation. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Append_unprotected( the_chain, the_node ) \ + _Chain_Append_unprotected( the_chain, the_node ) + + +/* + * Chain_Append + * + * This routine appends the_node onto the end of the_chain. + * It disables interrupts to insure the atomicity of the + * append operation. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Append( the_chain, the_node ) \ + _Chain_Append( the_chain, the_node ) + + +/* + * Chain_Prepend_unprotected + * + * This routine prepends the_node onto the front of the_chain. + * It does NOT disable interrupts to insure the atomicity of the + * prepend operation. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Prepend_unprotected( the_chain, the_node ) \ + _Chain_Prepend_unprotected( the_chain, the_node ) + + +/* + * Chain_Prepend + * + * This routine prepends the_node onto the front of the_chain. + * It disables interrupts to insure the atomicity of the + * prepend operation. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Prepend( the_chain, the_node ) \ + _Chain_Prepend( the_chain, the_node ) + + +/* + * Chain_Head + * + * This function returns a pointer to the first node on the chain. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Head( the_chain ) \ + _Chain_Head( the_chain ) + + +/* + * Chain_Tail + * + * This function returns a pointer to the last node on the chain. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Tail( the_chain ) \ + _Chain_Tail( the_chain ) + + +/* + * Chain_Is_head + * + * This function returns TRUE if the_node is the head of the_chain and + * FALSE otherwise. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_head( the_chain, the_node ) \ + _Chain_Is_head( the_chain, the_node ) + + +/* + * Chain_Is_tail + * + * This function returns TRUE if the_node is the tail of the_chain and + * FALSE otherwise. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_tail( the_chain, the_node ) \ + _Chain_Is_tail( the_chain, the_node ) + + +/* + * Chain_Is_first + * + * This function returns TRUE if the_node is the first node on a chain and + * FALSE otherwise. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_first( the_node ) \ + _Chain_Is_first( the_node ) + + +/* + * Chain_Is_last + * + * This function returns TRUE if the_node is the last node on a chain and + * FALSE otherwise. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_last( the_node ) \ + _Chain_Is_last( the_node ) + + +/* + * Chain_Is_empty + * + * This function returns TRUE if there are no nodes on the_chain and + * FALSE otherwise. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Is_empty( the_chain ) \ + _Chain_Is_empty( the_chain ) + + +/* + * Chain_Has_only_one_node + * + * This function returns TRUE if there is only one node on the_chain and + * FALSE otherwise. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Has_only_one_node( the_chain ) \ + _Chain_Has_only_one_node( the_chain ) + + +/* + * Chain_Is_null + * + * This function returns TRUE if the_chain is NULL and FALSE otherwise. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Is_null( the_chain ) \ + _Chain_Is_null( the_chain ) + + +/* + * Chain_Is_null_node + * + * This function returns TRUE if the_node is NULL and FALSE otherwise. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_null_node( the_node ) \ + _Chain_Is_null_node( the_node ) + + +#undef __RTEMS_APPLICATION__ +#include <rtems/score/chain.inl> +#define __RTEMS_APPLICATION__ +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h new file mode 100644 index 0000000000..69d300365c --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h @@ -0,0 +1,139 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include + * calling overhead including passing of arguments. + * + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +/* + * These are set to 0 for now. + * + * Units are 100ns. + * + * These numbers are of questionable use, as they are developed by calling + * the routine many times, thus getting its entry veneer into the (small) + * cache on the 403GA. This in general is not true of the RTEMS timing + * tests, which usually call a routine only once, thus having no cache loaded + * advantage. + * + * Whether the directive times are useful after deducting the function call + * overhead is also questionable. The user is more interested generally + * in the total cost of a directive, not the cost if the procedure call + * is inlined! (In general this is not true). + * + * Andrew Bray 18/08/1995 + * + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 +#define CALLING_OVERHEAD_TASK_CREATE 0 +#define CALLING_OVERHEAD_TASK_IDENT 0 +#define CALLING_OVERHEAD_TASK_START 0 +#define CALLING_OVERHEAD_TASK_RESTART 0 +#define CALLING_OVERHEAD_TASK_DELETE 0 +#define CALLING_OVERHEAD_TASK_SUSPEND 0 +#define CALLING_OVERHEAD_TASK_RESUME 0 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 +#define CALLING_OVERHEAD_TASK_MODE 0 +#define CALLING_OVERHEAD_TASK_GET_NOTE 0 +#define CALLING_OVERHEAD_TASK_SET_NOTE 0 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 +#define CALLING_OVERHEAD_CLOCK_GET 0 +#define CALLING_OVERHEAD_CLOCK_SET 0 +#define CALLING_OVERHEAD_CLOCK_TICK 0 + +#define CALLING_OVERHEAD_TIMER_CREATE 0 +#define CALLING_OVERHEAD_TIMER_IDENT 0 +#define CALLING_OVERHEAD_TIMER_DELETE 0 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 0 +#define CALLING_OVERHEAD_TIMER_RESET 0 +#define CALLING_OVERHEAD_TIMER_CANCEL 0 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 + +#define CALLING_OVERHEAD_EVENT_SEND 0 +#define CALLING_OVERHEAD_EVENT_RECEIVE 0 +#define CALLING_OVERHEAD_SIGNAL_CATCH 0 +#define CALLING_OVERHEAD_SIGNAL_SEND 0 +#define CALLING_OVERHEAD_PARTITION_CREATE 0 +#define CALLING_OVERHEAD_PARTITION_IDENT 0 +#define CALLING_OVERHEAD_PARTITION_DELETE 0 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 +#define CALLING_OVERHEAD_REGION_CREATE 0 +#define CALLING_OVERHEAD_REGION_IDENT 0 +#define CALLING_OVERHEAD_REGION_DELETE 0 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 +#define CALLING_OVERHEAD_PORT_CREATE 0 +#define CALLING_OVERHEAD_PORT_IDENT 0 +#define CALLING_OVERHEAD_PORT_DELETE 0 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 + +#define CALLING_OVERHEAD_IO_INITIALIZE 0 +#define CALLING_OVERHEAD_IO_OPEN 0 +#define CALLING_OVERHEAD_IO_CLOSE 0 +#define CALLING_OVERHEAD_IO_READ 0 +#define CALLING_OVERHEAD_IO_WRITE 0 +#define CALLING_OVERHEAD_IO_CONTROL 0 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/gen1.h b/c/src/lib/libbsp/powerpc/score603e/include/gen1.h new file mode 100644 index 0000000000..048c101382 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/gen1.h @@ -0,0 +1,155 @@ +/* Gen1.h + * + * This include file contains all Generation 1 board addreses + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __SCORE_GENERATION_1_h +#define __SCORE_GENERATION_1_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems.h> + +/* + * ISA/PCI I/O space. + */ +#define SCORE603E_VME_JUMPER_ADDR 0x00e20000 +#define SCORE603E_FLASH_BASE_ADDR 0x01000000 +#define SCORE603E_ISA_PCI_IO_BASE 0x80000000 +#define SCORE603E_TIMER_PORT_C 0x80000278 +#define SCORE603E_TIMER_INT_ACK 0x8000027a +#define SCORE603E_TIMER_PORT_B 0x8000027b +#define SCORE603E_TIMER_PORT_A 0x8000027c +#define SCORE603E_85C30_CTRL_1 ((volatile rtems_unsigned8 *)0x800002f8) +#define SCORE603E_85C30_INT_ACK ((volatile rtems_unsigned8 *)0x800002fa) +#define SCORE603E_85C30_CTRL_0 ((volatile rtems_unsigned8 *)0x800002fb) +#define SCORE603E_85C30_DATA_1 ((volatile rtems_unsigned8 *)0x800002fc) +#define SCORE603E_85C30_DATA_0 ((volatile rtems_unsigned8 *)0x800002ff) +#define SCORE603E_85C30_CTRL_3 ((volatile rtems_unsigned8 *)0x800003f8) +#define SCORE603E_85C30_CTRL_2 ((volatile rtems_unsigned8 *)0x800003fb) +#define SCORE603E_85C30_DATA_3 ((volatile rtems_unsigned8 *)0x800003fc) +#define SCORE603E_85C30_DATA_2 ((volatile rtems_unsigned8 *)0x800003ff) +#define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8 +#define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc + +#define SCORE603E_UNIVERSE_BASE 0x80030000 +#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000 +#define SCORE603E_PCI_MEM_BASE 0xc0000000 +#define SCORE603E_NVRAM_BASE 0xc00f0000 +#define SCORE603E_RTC_ADDRESS ((volatile unsigned char *)0xc00f1ff8) +#define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000 +#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000 + +#define SCORE603E_VME_A16_OFFSET 0x04000000 +#define SCORE603E_VME_A16_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET) + +#define SCORE603E_BOARD_CTRL_REG ((volatile rtems_unsigned32*)0x80000800) +#define SCORE603E_BRD_FLASH_DISABLE_MASK 0x02000000 + + /* + * Z85C30 Definations for the 232 interface. + */ +#define SCORE603E_85C30_0_CLOCK 10000000 /* 10,000,000 */ +#define SCORE603E_85C30_0_CLOCK_X 16 + +/* + * Z85C30 Definations for the 422 interface. + */ +#define SCORE603E_85C30_1_CLOCK 10000000 /* 10,000,000 */ +#define SCORE603E_85C30_1_CLOCK_X 16 + + +#define SCORE603E_UNIVERSE_CHIP_ID 0x000010E3 + +/* + * Score603e Interupt Definations. + */ + +/* + * First Score Unique IRQ + */ +#define Score_IRQ_First ( PPC_IRQ_LAST + 1 ) + +/* + * 82378ZB IRQ definations. + */ +#define SCORE603E_IRQ00_82378ZB ( Score_IRQ_First + 0 ) +#define SCORE603E_IRQ01_82378ZB ( Score_IRQ_First + 1 ) +#define SCORE603E_IRQ02_82378ZB ( Score_IRQ_First + 2 ) +#define SCORE603E_IRQ03_82378ZB ( Score_IRQ_First + 3 ) +#define SCORE603E_IRQ04_82378ZB ( Score_IRQ_First + 4 ) +#define SCORE603E_IRQ05_82378ZB ( Score_IRQ_First + 5 ) +#define SCORE603E_IRQ06_82378ZB ( Score_IRQ_First + 6 ) +#define SCORE603E_IRQ07_82378ZB ( Score_IRQ_First + 7 ) +#define SCORE603E_IRQ08_82378ZB ( Score_IRQ_First + 8 ) +#define SCORE603E_IRQ09_82378ZB ( Score_IRQ_First + 9 ) +#define SCORE603E_IRQ10_82378ZB ( Score_IRQ_First + 10 ) +#define SCORE603E_IRQ11_82378ZB ( Score_IRQ_First + 11 ) +#define SCORE603E_IRQ12_82378ZB ( Score_IRQ_First + 12 ) +#define SCORE603E_IRQ13_82378ZB ( Score_IRQ_First + 13 ) +#define SCORE603E_IRQ14_82378ZB ( Score_IRQ_First + 14 ) +#define SCORE603E_IRQ15_82378ZB ( Score_IRQ_First + 15 ) + +#define MAX_BOARD_IRQS SCORE603E_IRQ15_82378ZB + +#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03_82378ZB +#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04_82378ZB +#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ12_82378ZB + + +#define Write_82378ZB( _offset, _data ) { \ + volatile rtems_unsigned8 *addr; \ + addr = (volatile rtems_unsigned8 *)(SCORE603E_ISA_PCI_IO_BASE + _offset);\ + *addr = _data; } + +#define Read_82378ZB( _offset, _data ) { \ + volatile rtems_unsigned8 *addr; \ + addr = (volatile rtems_unsigned8 *)(SCORE603E_ISA_PCI_IO_BASE + _offset);\ + _data = *addr; } + + +/* + * BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer + * driver. + */ + +#define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */ + /* to start/stop the timer. */ +#define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */ + +/* + * Convert decrement value to tenths of microsecnds (used by + * shared timer driver). + * + * + CPU has a 66.67 Mhz bus, + * + There are 4 bus cycles per click + * + We return value in 1/10 microsecond units. + * Modified following equation to integer equation to remove + * floating point math. + * (int) ((float)(_value) / ((66.67 * 0.1) / 4.0)) + */ + +#define BSP_Convert_decrementer( _value ) \ + (int) (((_value) * 4000) / 6667) + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/gen2.h b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h new file mode 100644 index 0000000000..a157109d24 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h @@ -0,0 +1,276 @@ +/* Gen2.h + * + * This include file contains all Generation 2 board addreses + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __SCORE_GENERATION_2_h +#define __SCORE_GENERATION_2_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems.h> + +/* + * ISA/PCI I/O space. + */ +#define SCORE603E_VME_JUMPER_ADDR 0x00e20000 +#define SCORE603E_FLASH_BASE_ADDR 0x04000000 +#define SCORE603E_ISA_PCI_IO_BASE 0x80000000 +#define SCORE603E_TIMER_PORT_C 0xfd000000 +#define SCORE603E_TIMER_INT_ACK 0xfd000000 +#define SCORE603E_TIMER_PORT_B 0xfd000008 +#define SCORE603E_TIMER_PORT_A 0xfd000004 + +#define SCORE603E_BOARD_CTRL_REG ((volatile rtems_unsigned8 *)0xfd00002c) +#define SCORE603E_BRD_FLASH_DISABLE_MASK 0x40 + +#define SCORE603E_85C30_CTRL_0 ((volatile rtems_unsigned8 *)0xfe200020) +#define SCORE603E_85C30_DATA_0 ((volatile rtems_unsigned8 *)0xfe200024) +#define SCORE603E_85C30_CTRL_1 ((volatile rtems_unsigned8 *)0xfe200028) +#define SCORE603E_85C30_DATA_1 ((volatile rtems_unsigned8 *)0xfe20002c) +#define SCORE603E_85C30_CTRL_2 ((volatile rtems_unsigned8 *)0xfe200000) +#define SCORE603E_85C30_DATA_2 ((volatile rtems_unsigned8 *)0xfe200004) +#define SCORE603E_85C30_CTRL_3 ((volatile rtems_unsigned8 *)0xfe200008) +#define SCORE603E_85C30_DATA_3 ((volatile rtems_unsigned8 *)0xfe20000c) + +/* + * PSC8 - PMC Card + */ +#define SCORE603E_PCI_CONFIGURATION_BASE 0x80800000 +#define SCORE603E_PMC_BASE SCORE603E_PCI_CONFIGURATION_BASE +#define SCORE603E_PCI_PMC_DEVICE_BASE 0x80808000 + +#define SCORE603E_PCI_REGISTER_BASE 0xfc000000 + +#define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \ + ((volatile rtems_unsigned32 *)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset )) + + +#define SCORE603E_PMC_SERIAL_ADDRESS( _offset ) \ + ((volatile rtems_unsigned8 *)(SCORE603E_PCI_REGISTER_BASE + _offset)) + +/* + * PMC serial channels - (4-7: 232 and 8-11: 422) + */ +#define SCORE603E_85C30_CTRL_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200020) +#define SCORE603E_85C30_DATA_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200024) +#define SCORE603E_85C30_CTRL_5 SCORE603E_PMC_SERIAL_ADDRESS(0x200028) +#define SCORE603E_85C30_DATA_5 SCORE603E_PMC_SERIAL_ADDRESS(0x20002c) +#define SCORE603E_85C30_CTRL_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200030) +#define SCORE603E_85C30_DATA_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200034) +#define SCORE603E_85C30_CTRL_7 SCORE603E_PMC_SERIAL_ADDRESS(0x200038) +#define SCORE603E_85C30_DATA_7 SCORE603E_PMC_SERIAL_ADDRESS(0x20003c) +#define SCORE603E_85C30_CTRL_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200000) +#define SCORE603E_85C30_DATA_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200004) +#define SCORE603E_85C30_CTRL_9 SCORE603E_PMC_SERIAL_ADDRESS(0x200008) +#define SCORE603E_85C30_DATA_9 SCORE603E_PMC_SERIAL_ADDRESS(0x20000c) +#define SCORE603E_85C30_CTRL_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200010) +#define SCORE603E_85C30_DATA_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200014) +#define SCORE603E_85C30_CTRL_11 SCORE603E_PMC_SERIAL_ADDRESS(0x200018) +#define SCORE603E_85C30_DATA_11 SCORE603E_PMC_SERIAL_ADDRESS(0x20001c) + +#define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8 +#define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc + +#define SCORE603E_UNIVERSE_BASE 0x80030000 +#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000 +#define SCORE603E_PCI_MEM_BASE 0xc0000000 +#define SCORE603E_NVRAM_BASE 0xfd100000 +#define SCORE603E_RTC_ADDRESS ((volatile unsigned char *)0xfd180000) +#define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000 +#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000 + + +#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) +#define SCORE603E_VME_A16_OFFSET 0x04000000 +#elif (SCORE603E_USE_DINK) +#define SCORE603E_VME_A16_OFFSET 0x11000000 +#define SCORE603E_VME_A24_OFFSET 0x10000000 +#define SCORE603E_VME_A24_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET) +#else +#error "SCORE603E gen2.h -- what ROM monitor are you using" +#endif + +#define SCORE603E_VME_A16_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET) + +/* + * Definations for the ICM 1770 RTC chip + */ + /* + * These values are programed into a register and must not be changed. + */ +#define ICM1770_CRYSTAL_FREQ_32K 0x00 +#define ICM1770_CRYSTAL_FREQ_1M 0x01 +#define ICM1770_CRYSTAL_FREQ_2M 0x02 +#define ICM1770_CRYSTAL_FREQ_4M 0x03 + +#define SCORE_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K + +/* + * Z85C30 Definations for the 423 interface. + */ +#define SCORE603E_85C30_0_CLOCK 14745600 /* 10,000,000 ?10->14.5 */ +#define SCORE603E_85C30_0_CLOCK_X 16 + +/* + * Z85C30 Definations for the 422 interface. + */ +#define SCORE603E_85C30_1_CLOCK 16000000 /* 10,000,000 ?10->14.5 */ +#define SCORE603E_85C30_1_CLOCK_X 16 + +/* + * Z85C30 Definations for the PMC serial chips + */ +#define SCORE603E_85C30_PMC_CLOCK 16000000 /* 10,000,000 ?10->14.5 */ +#define SCORE603E_85C30_PMC_CLOCK_X 16 + +#define SCORE603E_85C30_2_CLOCK SCORE603E_85C30_PMC_CLOCK +#define SCORE603E_85C30_3_CLOCK SCORE603E_85C30_PMC_CLOCK +#define SCORE603E_85C30_4_CLOCK SCORE603E_85C30_PMC_CLOCK +#define SCORE603E_85C30_5_CLOCK SCORE603E_85C30_PMC_CLOCK +#define SCORE603E_85C30_2_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X +#define SCORE603E_85C30_3_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X +#define SCORE603E_85C30_4_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X +#define SCORE603E_85C30_5_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X + + +#define SCORE603E_UNIVERSE_CHIP_ID 0x000010E3 + +/* + * FPGA Interupt Address Definations. + */ +#define SCORE603E_FPGA_VECT_DATA ((volatile rtems_unsigned16 *)0xfd000040) +#define SCORE603E_FPGA_BIT1_15_0 ((volatile rtems_unsigned16 *)0xfd000044) +#define SCORE603E_FPGA_MASK_DATA ((volatile rtems_unsigned16 *)0xfd000048) +#define SCORE603E_FPGA_IRQ_INPUT ((volatile rtems_unsigned16 *)0xfd00004c) + +/* + * The PMC status word is at the PMC base address + */ +#define SCORE603E_PMC_STATUS_ADDRESS (SCORE603E_PMC_SERIAL_ADDRESS (0)) +#define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80) /* SCC 422-1 */ +#define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40) /* SCC 232-1 */ +#define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20) /* SCC 422-2 */ +#define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08) /* SCC 232-2 */ + +#define SCORE603E_PMC_CONTROL_ADDRESS SCORE603E_PMC_SERIAL_ADDRESS(0x100000) +#define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20) + +#define PMC_SET_232_LOOPBACK(_word) (_word | 0x02) +#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd) +#define PMC_SET_422_LOOPBACK(_word) (_word | 0x01) +#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe) + + +/* + * Score603e Interupt Definations. + */ + +/* + * First Score Unique IRQ + */ +#define Score_IRQ_First ( PPC_IRQ_LAST + 1 ) + +/* + * The Following Are part of a Score603e FPGA. + */ +#define SCORE603E_IRQ00 ( Score_IRQ_First + 0 ) +#define SCORE603E_IRQ01 ( Score_IRQ_First + 1 ) +#define SCORE603E_IRQ02 ( Score_IRQ_First + 2 ) +#define SCORE603E_IRQ03 ( Score_IRQ_First + 3 ) +#define SCORE603E_IRQ04 ( Score_IRQ_First + 4 ) +#define SCORE603E_IRQ05 ( Score_IRQ_First + 5 ) +#define SCORE603E_IRQ06 ( Score_IRQ_First + 6 ) +#define SCORE603E_IRQ07 ( Score_IRQ_First + 7 ) +#define SCORE603E_IRQ08 ( Score_IRQ_First + 8 ) +#define SCORE603E_IRQ09 ( Score_IRQ_First + 9 ) +#define SCORE603E_IRQ10 ( Score_IRQ_First + 10 ) +#define SCORE603E_IRQ11 ( Score_IRQ_First + 11 ) +#define SCORE603E_IRQ12 ( Score_IRQ_First + 12 ) +#define SCORE603E_IRQ13 ( Score_IRQ_First + 13 ) +#define SCORE603E_IRQ14 ( Score_IRQ_First + 14 ) +#define SCORE603E_IRQ15 ( Score_IRQ_First + 15 ) + +#define SCORE603E_TIMER1_IRQ SCORE603E_IRQ00 +#define SCORE603E_TIMER2_IRQ SCORE603E_IRQ01 +#define SCORE603E_TIMER3_IRQ SCORE603E_IRQ02 +#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03 +#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04 +#define SCORE603E_RTC_IRQ SCORE603E_IRQ05 +#define SCORE603E_PCI_IRQ_0 SCORE603E_IRQ06 +#define SCORE603E_PCI_IRQ_1 SCORE603E_IRQ07 +#define SCORE603E_PCI_IRQ_2 SCORE603E_IRQ08 +#define SCORE603E_PCI_IRQ_3 SCORE603E_IRQ09 +#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ10 +#define SCORE603E_1553_IRQ SCORE603E_IRQ11 +#define SCORE603E_MAIL_BOX_IRQ_0 SCORE603E_IRQ12 +#define SCORE603E_MAIL_BOX_IRQ_1 SCORE603E_IRQ13 +#define SCORE603E_MAIL_BOX_IRQ_2 SCORE603E_IRQ14 +#define SCORE603E_MAIL_BOX_IRQ_3 SCORE603E_IRQ15 + +/* + * The Score FPGA maps all interrupts comming from the PMC card to + * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be + * read to indicate which interrupt was chained to the FPGA. + */ +#define SCORE603E_IRQ16 ( Score_IRQ_First + 16 ) +#define SCORE603E_IRQ17 ( Score_IRQ_First + 17 ) +#define SCORE603E_IRQ18 ( Score_IRQ_First + 18 ) +#define SCORE603E_IRQ19 ( Score_IRQ_First + 19 ) + +/* + * IRQ'a read from the PMC card + */ +#define SCORE603E_85C30_4_IRQ SCORE603E_IRQ16 /* SCC 422-1 */ +#define SCORE603E_85C30_2_IRQ SCORE603E_IRQ17 /* SCC 232-1 */ +#define SCORE603E_85C30_5_IRQ SCORE603E_IRQ18 /* SCC 422-2 */ +#define SCORE603E_85C30_3_IRQ SCORE603E_IRQ19 /* SCC 232-2 */ + +#define MAX_BOARD_IRQS SCORE603E_IRQ19 + + +/* + * BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer + * driver. + */ + +#define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */ + /* to start/stop the timer. */ +#define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */ + +/* + * Convert decrement value to tenths of microsecnds (used by + * shared timer driver). + * + * + CPU has a 66.67 Mhz bus, + * + There are 4 bus cycles per click + * + We return value in 1/10 microsecond units. + * Modified following equation to integer equation to remove + * floating point math. + * (int) ((float)(_value) / ((66.67 * 0.1) / 4.0)) + */ + +#define BSP_Convert_decrementer( _value ) \ + (int) (((_value) * 4000) / 6667) + +#endif + +#ifdef __cplusplus +} +#endif + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/tod.h b/c/src/lib/libbsp/powerpc/score603e/include/tod.h new file mode 100644 index 0000000000..d51ceb23b9 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/tod.h @@ -0,0 +1,38 @@ +/* + * Real Time Clock (MK48T08) for RTEMS on Score603e + * + * Based on MVME162 TOD by: + * COPYRIGHT (C) 1997 + * by Katsutoshi Shibuya - BU Denken Co.,Ltd. - Sapporo - JAPAN + * ALL RIGHTS RESERVED + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + + +#ifndef TOD_H +#define TOD_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern void setRealTimeToRTEMS(); +/* Read real time from RTC and set it to RTEMS' clock manager */ + +extern void setRealTimeFromRTEMS(); +/* Read time from RTEMS' clock manager and set it to RTC */ + +extern int checkRealTime(); +/* Return the difference between RTC and RTEMS' clock manager time in minutes. + If the difference is greater than 1 day, this returns 9999. */ + +#ifdef __cplusplus +} +#endif + +#endif |