diff options
Diffstat (limited to 'c')
44 files changed, 6467 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/score603e/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/Makefile.in new file mode 100644 index 0000000000..80d87c2ad1 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/Makefile.in @@ -0,0 +1,22 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/directory.cfg + +SRCS=README + +all: $(SRCS) + +# wrapup is the one that actually builds and installs the library +# from the individual .rel files built in other directories +SUB_DIRS=include clock console startup start timer tod PCI_bus vectors wrapup diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/Makefile.in new file mode 100644 index 0000000000..fc893346d6 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/Makefile.in @@ -0,0 +1,56 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +PGM=${ARCH}/PCI_bus.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=universe PCI flash +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +SRCS=$(C_FILES) $(H_FILES) +OBJS=$(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c new file mode 100644 index 0000000000..ac96d23f6c --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c @@ -0,0 +1,110 @@ +/* + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $ld: + */ + +#include <rtems.h> +#include <assert.h> +#include <stdio.h> + +#include <bsp.h> + +/* + * Forced delay to get around timing problems with the UNIVERSE chip. The + * two nops are used so that the delay works for varying clock frequencies, + * up to 66 Mhz, with margin. Each nop averages about 1 1/2 clock ticks, + * and since there are 2 nops, this routine takes about 3 clock ticks, + * which on a worst case 66 Mhz board, is 45 nanosecond. This time period + * is sufficient to guarantee a work-around to the UNIVERSE chip timing + * problem. The problem is that when there are two successive accesses to + * an UNIVERSE register, without sufficient delay, the second access will + * not work correctly. + */ +void PCI_bus_delay () +{ + asm(" nop"); + asm(" nop"); +} + + + +/* + * PCI_bus_write + */ +void PCI_bus_write( + volatile rtems_unsigned32 * _addr, /* IN */ + rtems_unsigned32 _data /* IN */ +) +{ + _data = Convert_Endian_32( _data ); + *_addr = _data; +} + +rtems_unsigned32 PCI_bus_read( + volatile rtems_unsigned32 * _addr /* IN */ +) +{ + rtems_unsigned32 data; + + data = *_addr; + data = Convert_Endian_32( data ); + return data; +} +/* + * PCI Configuration Cycle Read/Write Access which is used to access all of + * devices registers on the PCI bus. i.e.: Universe, Ethernet & PMC. + */ + +rtems_unsigned32 Read_pci_device_register( + rtems_unsigned32 address +) +{ + rtems_unsigned32 data; + + /* + * Write the PCI configuration address + */ + PCI_bus_write( (volatile rtems_unsigned32 *)SCORE603E_PCI_IO_CFG_ADDR, address ); + + /* + * Delay needed when running out of DRAM + */ + PCI_bus_delay (); + + /* + * read data + */ + data = PCI_bus_read( (volatile rtems_unsigned32 *)SCORE603E_PCI_IO_CFG_DATA ); + + return data; +} + +void Write_pci_device_register( + rtems_unsigned32 address, + rtems_unsigned32 data +) +{ + /* + * Write the PCI configuration address + */ + PCI_bus_write( (volatile rtems_unsigned32 *)SCORE603E_PCI_IO_CFG_ADDR, address ); + + /* + * Delay needed when running out of DRAM + */ + PCI_bus_delay (); + + /* + * write data + */ + PCI_bus_write( (volatile rtems_unsigned32 *)SCORE603E_PCI_IO_CFG_DATA, data ); +} + diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h new file mode 100644 index 0000000000..dfcb059bbb --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h @@ -0,0 +1,42 @@ +/* PCI.h + * + * This include file contains prototypes for chips attached to the + * PCI bus. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ +#ifndef __PCI_h +#define __PCI_h + +/* + * PCI.c + */ + +void PCI_bus_write( + volatile rtems_unsigned32 * _addr, + rtems_unsigned32 _data +); + +rtems_unsigned32 PCI_bus_read( + volatile rtems_unsigned32 * _addr +); + +rtems_unsigned32 Read_pci_device_register( + rtems_unsigned32 address +); + +void Write_pci_device_register( + rtems_unsigned32 address, + rtems_unsigned32 data +); + +#endif + diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c new file mode 100644 index 0000000000..5798aef90e --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c @@ -0,0 +1,115 @@ +/* + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $ld: + */ + +#include <rtems.h> +#include <assert.h> +#include <stdio.h> + +#include <bsp.h> +#include "PCI.h" +/*PAGE + * + * SCORE603e_FLASH_Disable + */ + +unsigned int SCORE603e_FLASH_Disable( + rtems_unsigned32 area /* IN */ +) +{ + rtems_unsigned8 value; + + value = *SCORE603E_BOARD_CTRL_REG; + value = value | (~SCORE603E_BRD_FLASH_DISABLE_MASK); + *SCORE603E_BOARD_CTRL_REG = value; + + return RTEMS_SUCCESSFUL; +} + +unsigned int SCORE603e_FLASH_verify_enable() +{ + volatile rtems_unsigned8 *Ctrl_Status_Register = + (void *)SCORE603E_BOARD_CTRL_REG; + rtems_unsigned8 ctrl_value; + rtems_unsigned32 pci_value; + + ctrl_value = *Ctrl_Status_Register; + if ( ctrl_value & SCORE603E_BRD_FLASH_DISABLE_MASK ) { + printf ("Flash Writes Disabled by board control register %x\n", + ctrl_value ); + assert( 0x0 ); + } + + pci_value = Read_pci_device_register( 0x800000A8 ); + if (( pci_value & 0x00001000 ) == 0) { + printf("Error PCI A8 \n"); + assert( 0x0 ); + } + + pci_value = Read_pci_device_register( 0x800000AC ); + if ( pci_value & 0x02000000) { + printf("Error PCI AC \n"); + assert( 0x0 ); + } + return RTEMS_SUCCESSFUL; +} + +unsigned int SCORE603e_FLASH_pci_reset_reg( + rtems_unsigned8 reg, + rtems_unsigned32 cmask, + rtems_unsigned32 mask +) +{ + rtems_unsigned32 pci_value; + rtems_unsigned32 value; + + pci_value = Read_pci_device_register( reg ); + pci_value &= cmask; + pci_value |= mask; + Write_pci_device_register( reg, pci_value ); + value = Read_pci_device_register( reg ); + if (value != pci_value) { + printf("Error PCI %x wrote %x read %x\n", reg, pci_value, value); + } + return RTEMS_SUCCESSFUL; +} + +/*PAGE + * + * SCORE603e_FLASH_Enable_writes + */ +unsigned int SCORE603e_FLASH_Enable_writes( + rtems_unsigned32 area /* IN */ +) +{ + rtems_unsigned8 ctrl_value; + rtems_unsigned32 pci_value; + + ctrl_value = *SCORE603E_BOARD_CTRL_REG; + ctrl_value = ctrl_value & 0xbf; + *SCORE603E_BOARD_CTRL_REG = ctrl_value; + + pci_value = Read_pci_device_register( 0x800000A8 ); + pci_value |= 0x00001000; + Write_pci_device_register( 0x800000A8, pci_value ); + + pci_value = Read_pci_device_register( 0x800000AC ); + pci_value &= (~0x02000000); + Write_pci_device_register( 0x000000AC, pci_value ); + + return RTEMS_SUCCESSFUL; +} + + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c new file mode 100644 index 0000000000..379dc3751c --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c @@ -0,0 +1,330 @@ +/* + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $ld: + */ + +#include <rtems.h> +#include <assert.h> +#include <stdio.h> + +#include <bsp.h> +#include "PCI.h" + +/******************************************************************** + ******************************************************************** + ********* ********* + ********* Prototypes ********* + ********* ********* + ******************************************************************** + ********************************************************************/ + + +/******************************************************************** + ******************************************************************** + ********* ********* + ********* ********* + ********* ********* + ******************************************************************** + ********************************************************************/ + +typedef struct { + rtems_unsigned32 PCI_ID; /* 0x80030000 */ + rtems_unsigned32 PCI_CSR; /* 0x80030004 */ + rtems_unsigned32 PCI_CLASS; /* 0x80030008 */ + rtems_unsigned32 PCI_MISC0; /* 0x8003000C */ + rtems_unsigned32 PCI_BS; /* 0x80030010 */ + rtems_unsigned32 Buf_0x80030014[ 0x0A ]; /* 0x80030014 */ + rtems_unsigned32 PCI_MISC1; /* 0x8003003C */ + rtems_unsigned32 Buf_0x80030040[ 0x30 ]; /* 0x80030040 */ + rtems_unsigned32 LSI0_CTL; /* 0x80030100 */ + rtems_unsigned32 LSI0_BS; /* 0x80030104 */ + rtems_unsigned32 LSI0_BD; /* 0x80030108 */ + rtems_unsigned32 LSI0_TO; /* 0x8003010C */ + rtems_unsigned32 Buf_0x80030110; /* 0x80030110 */ + rtems_unsigned32 LSI1_CTL; /* 0x80030114 */ + rtems_unsigned32 LSI1_BS; /* 0x80030118 */ + rtems_unsigned32 LSI1_BD; /* 0x8003011C */ + rtems_unsigned32 LSI1_TO; /* 0x80030120 */ + rtems_unsigned32 Buf_0x80030124; /* 0x80030124 */ + rtems_unsigned32 LSI2_CTL; /* 0x80030128 */ + rtems_unsigned32 LSI2_BS; /* 0x8003012C */ + rtems_unsigned32 LSI2_BD; /* 0x80030130 */ + rtems_unsigned32 LSI2_TO; /* 0x80030134 */ + rtems_unsigned32 Buf_0x80030138; /* 0x80030138 */ + rtems_unsigned32 LSI3_CTL; /* 0x8003013C */ + rtems_unsigned32 LSI3_BS; /* 0x80030140 */ + rtems_unsigned32 LSI3_BD; /* 0x80030144 */ + rtems_unsigned32 LSI3_TO; /* 0x80030148 */ + rtems_unsigned32 Buf_0x8003014C[ 0x09 ]; /* 0x8003014C */ + rtems_unsigned32 SCYC_CTL; /* 0x80030170 */ + rtems_unsigned32 SCYC_ADDR; /* 0x80030174 */ + rtems_unsigned32 SCYC_EN; /* 0x80030178 */ + rtems_unsigned32 SCYC_CMP; /* 0x8003017C */ + rtems_unsigned32 SCYC_SWP; /* 0x80030180 */ + rtems_unsigned32 LMISC; /* 0x80030184 */ + rtems_unsigned32 SLSI; /* 0x80030188 */ + rtems_unsigned32 L_CMDERR; /* 0x8003018C */ + rtems_unsigned32 LAERR; /* 0x80030190 */ + rtems_unsigned32 Buf_0x80030194[ 0x1B ]; /* 0x80030194 */ + rtems_unsigned32 DCTL; /* 0x80030200 */ + rtems_unsigned32 DTBC; /* 0x80030204 */ + rtems_unsigned32 DLA; /* 0x80030208 */ + rtems_unsigned32 Buf_0x8003020C; /* 0x8003020C */ + rtems_unsigned32 DVA; /* 0x80030210 */ + rtems_unsigned32 Buf_0x80030214; /* 0x80030214 */ + rtems_unsigned32 DCPP; /* 0x80030218 */ + rtems_unsigned32 Buf_0x8003021C; /* 0x8003021C */ + rtems_unsigned32 DGCS; /* 0x80030220 */ + rtems_unsigned32 D_LLUE; /* 0x80030224 */ + rtems_unsigned32 Buf_0x80030228[ 0x36 ]; /* 0x80030228 */ + rtems_unsigned32 LINT_EN; /* 0x80030300 */ + rtems_unsigned32 LINT_STAT; /* 0x80030304 */ + rtems_unsigned32 LINT_MAP0; /* 0x80030308 */ + rtems_unsigned32 LINT_MAP1; /* 0x8003030C */ + rtems_unsigned32 VINT_EN; /* 0x80030310 */ + rtems_unsigned32 VINT_STAT; /* 0x80030314 */ + rtems_unsigned32 VINT_MAP0; /* 0x80030318 */ + rtems_unsigned32 VINT_MAP1; /* 0x8003031C */ + rtems_unsigned32 STATID; /* 0x80030320 */ + rtems_unsigned32 V1_STATID; /* 0x80030324 */ + rtems_unsigned32 V2_STATID; /* 0x80030328 */ + rtems_unsigned32 V3_STATID; /* 0x8003032C */ + rtems_unsigned32 V4_STATID; /* 0x80030330 */ + rtems_unsigned32 V5_STATID; /* 0x80030334 */ + rtems_unsigned32 V6_STATID; /* 0x80030338 */ + rtems_unsigned32 V7_STATID; /* 0x8003033C */ + rtems_unsigned32 Buf_0x80030340[ 0x30 ]; /* 0x80030340 */ + rtems_unsigned32 MAST_CTL; /* 0x80030400 */ + rtems_unsigned32 MISC_CTL; /* 0x80030404 */ + rtems_unsigned32 MISC_STAT; /* 0x80030408 */ + rtems_unsigned32 USER_AM; /* 0x8003040C */ + rtems_unsigned32 Buf_0x80030410[ 0x2bc ];/* 0x80030410 */ + rtems_unsigned32 VSI0_CTL; /* 0x80030F00 */ + rtems_unsigned32 VSI0_BS; /* 0x80030F04 */ + rtems_unsigned32 VSI0_BD; /* 0x80030F08 */ + rtems_unsigned32 VSI0_TO; /* 0x80030F0C */ + rtems_unsigned32 Buf_0x80030f10; /* 0x80030F10 */ + rtems_unsigned32 VSI1_CTL; /* 0x80030F14 */ + rtems_unsigned32 VSI1_BS; /* 0x80030F18 */ + rtems_unsigned32 VSI1_BD; /* 0x80030F1C */ + rtems_unsigned32 VSI1_TO; /* 0x80030F20 */ + rtems_unsigned32 Buf_0x80030F24; /* 0x80030F24 */ + rtems_unsigned32 VSI2_CTL; /* 0x80030F28 */ + rtems_unsigned32 VSI2_BS; /* 0x80030F2C */ + rtems_unsigned32 VSI2_BD; /* 0x80030F30 */ + rtems_unsigned32 VSI2_TO; /* 0x80030F34 */ + rtems_unsigned32 Buf_0x80030F38; /* 0x80030F38 */ + rtems_unsigned32 VSI3_CTL; /* 0x80030F3C */ + rtems_unsigned32 VSI3_BS; /* 0x80030F40 */ + rtems_unsigned32 VSI3_BD; /* 0x80030F44 */ + rtems_unsigned32 VSI3_TO; /* 0x80030F48 */ + rtems_unsigned32 Buf_0x80030F4C[ 0x9 ]; /* 0x80030F4C */ + rtems_unsigned32 VRAI_CTL; /* 0x80030F70 */ + rtems_unsigned32 VRAI_BS; /* 0x80030F74 */ + rtems_unsigned32 Buf_0x80030F78[ 0x2 ]; /* 0x80030F78 */ + rtems_unsigned32 VCSR_CTL; /* 0x80030F80 */ + rtems_unsigned32 VCSR_TO; /* 0x80030F84 */ + rtems_unsigned32 V_AMERR; /* 0x80030F88 */ + rtems_unsigned32 VAERR; /* 0x80030F8C */ + rtems_unsigned32 Buf_0x80030F90[ 0x19 ]; /* 0x80030F90 */ + rtems_unsigned32 VCSR_CLR; /* 0x80030FF4 */ + rtems_unsigned32 VCSR_SET; /* 0x80030FF8 */ + rtems_unsigned32 VCSR_BS; /* 0x80030FFC */ +} Universe_Memory; + +volatile Universe_Memory *UNIVERSE = + (volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE; + + +/******************************************************************** + ******************************************************************** + ********* ********* + ********* ********* + ********* ********* + ******************************************************************** + ********************************************************************/ + +/* + * Initializes the UNIVERSE chip. This routine is called automatically + * by the boot code. This routine should be called by user code only if + * a complete SCORE603e VME initialization is required. + */ + +void initialize_universe() +{ + rtems_unsigned32 jumper_selection; + rtems_unsigned32 pci_id; + volatile rtems_unsigned32 universe_temp_value; + + /* + * Read the VME jumper location to determine the VME base address + */ + jumper_selection = PCI_bus_read( + (volatile rtems_unsigned32 *)SCORE603E_VME_JUMPER_ADDR ); + jumper_selection = (jumper_selection >> 3) & 0x1f; + + /* + * Verify the UNIVERSE CHIP ID + */ + pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE ); + + /* + * compare to known ID + */ + if (pci_id != SCORE603E_UNIVERSE_CHIP_ID ){ + DEBUG_puts ("Invalid SCORE603E_UNIVERSE_CHIP_ID: "); + rtems_fatal_error_occurred( 0x603e0bad ); + } + +#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) + + /* + * Set the UNIVERSE PCI Configuration Base Address Register with 0x30001 + * to specifies the 64 Kbyte aligned base address of the UNIVERSE register + * space on PCI to be 0x30000 + 0x80000000 (IO_BASE) + */ + Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x10,0x30001 ); + + /* + * Set the UNIVERSE PCI Configuration Space Control and Status Register to + * medium speed device, Target Back to Back Capable, Master Enable, Target + * Memory Enable and Target IO Enable + */ + Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 ); + + /* + * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register + */ + PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 ); + + /* + * Set the VMEbus Master Control register with retry forever, 256 bytes + * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes + * aligned burst size and PCI bus number to be zero + */ + PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 ); + + /* + * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data + * width, A32 VMEbus Address Space, AM code to be data, none-privilleged, + * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable + PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 ); + */ + + PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 ); + PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 ); + PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 ); + PCI_bus_write( &UNIVERSE->LSI0_TO, 0x7C000000 ); + + /* + * Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of + * BI-Mode VMEbus accesses can be made. + */ + + universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL ); + + if (universe_temp_value & 0x100000) + PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF)); + +#elif (SCORE603E_USE_DINK) + /* + * Do not modify the DINK setup of the universe chip. + */ + +#else +#error "SCORE603E BSPSTART.C -- what ROM monitor are you using" +#endif + +} + + +/* + * Set the slave VME base address to the specified base address. + * Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus + * Slave Image 0 registers. + */ +void set_vme_base_address ( + rtems_unsigned32 base_address +) +{ + volatile rtems_unsigned32 temp; + + /* + * Calculate the current size of the Slave VME image 0 + */ + temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) - + ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000); + + /* + * Set the VMEbus Slave Image 0 Base Address to be + * the specifed base address on VSI0_BS register. + */ + PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) ); + + /* + * Update the VMEbus Slave Image 0 Bound Address. + */ + PCI_bus_write( &UNIVERSE->VSI0_BD, temp ); + + /* + * Update the VMEbus Slave Image 0 Translation Offset + */ + temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000; + PCI_bus_write( &UNIVERSE->VSI0_TO, temp ); +} + +/* + * Gets the VME base address + */ +rtems_unsigned32 get_vme_base_address () +{ + volatile rtems_unsigned32 temp; + + temp = PCI_bus_read( &UNIVERSE->VSI0_BS ); + temp &= 0xFFFFF000; + return (temp); +} + +rtems_unsigned32 get_vme_slave_size() +{ + volatile rtems_unsigned32 temp; + temp = PCI_bus_read( &UNIVERSE->VSI0_BD); + temp &= 0xFFFFF000; + temp = temp - get_vme_base_address (); + return temp; +} + +/* + * Set the size of the VME slave image + * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF) + */ +void set_vme_slave_size (rtems_unsigned32 size) +{ + volatile rtems_unsigned32 temp; + + if (size<0) + size = 0; + + if (size > 0x17FFFFF) + size = 0x17FFFFF; + + /* + * Read the VME slave image base address + */ + temp = get_vme_base_address (); + + /* + * Update the VMEbus Slave Image 0 Bound Address. + */ + temp = temp + (size & 0xFFFFF000); + PCI_bus_write( &UNIVERSE->VSI0_BD, temp ); +} + diff --git a/c/src/lib/libbsp/powerpc/score603e/README b/c/src/lib/libbsp/powerpc/score603e/README new file mode 100644 index 0000000000..f1b51821a0 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/README @@ -0,0 +1,55 @@ +# +# $Id$ +# + +BSP NAME: score603e +BOARD: VISTA SCORE 603e Generation I and II +BUS: N/A +CPU FAMILY: ppc +CPU: PowerPC 603e +COPROCESSORS: N/A +MODE: 32 bit mode + +DEBUG MONITOR: see note. + +PERIPHERALS +=========== +TIMERS: PPC internal Timebase register + RESOLUTION: +SERIAL PORTS: 2 Z85C30s +REAL-TIME CLOCK: Generation I: SGSM48T18 + Generation II: ICM7170AIBG +DMA: none +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: PPC internal +IOSUPP DRIVER: N/A +SHMSUPP: N/A +TIMER DRIVER: PPC internal +TTY DRIVER: PPC internal + +STDIO +===== +PORT: Console port 0 +ELECTRICAL: na +BAUD: 9600 +BITS PER CHARACTER: 8 +PARITY: n +STOP BITS: 1 + +Notes +===== + +This BSP has been tested using any Rom monitor. There have +been three rom chips loaded on the boards. One with the SDS +debug monitor, one with the firmworks monitor, and one with +the OAR Boot chip. The OAR Boot chip contains the basic +initialization from the SDS debugger and a jump to flash +location 0x04001200. + +The compiler option SCORE603E_GENERATION is set to 1 or 2, +for the generation to be produced. diff --git a/c/src/lib/libbsp/powerpc/score603e/bsp_specs b/c/src/lib/libbsp/powerpc/score603e/bsp_specs new file mode 100644 index 0000000000..3630230224 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/bsp_specs @@ -0,0 +1,18 @@ +%rename cpp old_cpp +%rename lib old_lib +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*cpp: +%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded) + +*lib: +%{!qrtems: %(old_lib)} %{qrtems: ecrti%O%s ecrtn%O%s --start-group -lrtemsall -lc -lgcc --end-group %{!qnolinkcmds: -T linkcmds%s}} + +*startfile: +%{!qrtems: %(old_startfile)} %{qrtems: start.o%s} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -Qy -dp -Bstatic -e _start -u __vectors} + diff --git a/c/src/lib/libbsp/powerpc/score603e/clock/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/clock/Makefile.in new file mode 100644 index 0000000000..390e1be4b9 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/clock/Makefile.in @@ -0,0 +1,62 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +PGM=${ARCH}/clock.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=clock +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/score603e/clock/clock.c b/c/src/lib/libbsp/powerpc/score603e/clock/clock.c new file mode 100644 index 0000000000..76b328f217 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/clock/clock.c @@ -0,0 +1,241 @@ +/* + * Clock Tick Device Driver + * + * This routine utilizes the Decrementer Register common to the PPC family. + * + * The tick frequency is directly programmed to the configured number of + * microseconds per tick. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <stdlib.h> + +#include <bsp.h> +#include <rtems/libio.h> +#include <assert.h> + +/* + * The Real Time Clock Counter Timer uses this trap type. + */ + +#define CLOCK_VECTOR PPC_IRQ_DECREMENTER + +/* + * Clock ticks since initialization + */ + +volatile rtems_unsigned32 Clock_driver_ticks; + +/* + * This is the value programmed into the count down timer. + */ + +rtems_unsigned32 Clock_Decrementer_value; + +rtems_isr_entry Old_ticker; + +void Clock_exit( void ); + +/* + * These are set by clock driver during its init + */ + +rtems_device_major_number rtems_clock_major = ~0; +rtems_device_minor_number rtems_clock_minor; + +#define PPC_Set_decrementer( _clicks ) \ + do { \ + asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + + +/* + * Clock_isr + * + * This is the clock tick interrupt handler. + * + * Input parameters: + * vector - vector number + * + * Output parameters: NONE + * + * Return values: NONE + * + */ +rtems_isr Clock_isr( + rtems_vector_number vector, + CPU_Interrupt_frame *frame +) +{ + /* + * Set the decrementer. + */ + + PPC_Set_decrementer( Clock_Decrementer_value ); + + /* + * The driver has seen another tick. + */ + + Clock_driver_ticks += 1; + + /* + * Real Time Clock counter/timer is set to automatically reload. + */ + + rtems_clock_tick(); +} + +/* + * Install_clock + * + * This routine actually performs the hardware initialization for the clock. + * + * Input parameters: + * clock_isr - clock interrupt service routine entry point + * + * Output parameters: NONE + * + * Return values: NONE + * + */ + +extern int CLOCK_SPEED; + +void Install_clock( + rtems_isr_entry clock_isr +) +{ + Clock_driver_ticks = 0; + + if ( BSP_Configuration.ticks_per_timeslice ) { + Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); + + PPC_Set_decrementer( Clock_Decrementer_value ); + + atexit( Clock_exit ); + } +} + +/* + * Clock_exit + * + * This routine allows the clock driver to exit by masking the interrupt and + * disabling the clock's counter. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: NONE + * + */ + +void Clock_exit( void ) +{ + if ( BSP_Configuration.ticks_per_timeslice ) { + + /* nothing to do */; + + /* do not restore old vector */ + } +} + +/* + * Clock_initialize + * + * This routine initializes the clock driver. + * + * Input parameters: + * major - clock device major number + * minor - clock device minor number + * parg - pointer to optional device driver arguments + * + * Output parameters: NONE + * + * Return values: + * rtems_device_driver status code + */ + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + Clock_Decrementer_value = (int) &CPU_PPC_CLICKS_PER_MS * + (BSP_Configuration.microseconds_per_tick / 1000); + + Install_clock( Clock_isr ); + + /* + * make major/minor avail to others such as shared memory driver + */ + + rtems_clock_major = major; + rtems_clock_minor = minor; + + return RTEMS_SUCCESSFUL; +} + +/* + * Clock_control + * + * This routine is the clock device driver control entry point. + * + * Input parameters: + * major - clock device major number + * minor - clock device minor number + * parg - pointer to optional device driver arguments + * + * Output parameters: NONE + * + * Return values: + * rtems_device_driver status code + */ + +rtems_device_driver Clock_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_unsigned32 isrlevel; + rtems_libio_ioctl_args_t *args = pargp; + + if (args == 0) + goto done; + + /* + * This is hokey, but until we get a defined interface + * to do this, it will just be this simple... + */ + + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) + { + Clock_isr( CLOCK_VECTOR, pargp ); + } + else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) + { + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); + } + +done: + return RTEMS_SUCCESSFUL; +} + + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/console/85c30.c b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c new file mode 100644 index 0000000000..d95246c074 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c @@ -0,0 +1,434 @@ +/* + * This file contains the console driver chip level routines for the + * z85c30 chip. + * + * Currently only polled mode is supported. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#include <rtems.h> +#include <bsp.h> +#include <rtems/libio.h> +#include <assert.h> + +#include "85c30.h" +#include "consolebsp.h" + +#define STATUS_REGISTER 0x00 +#define DATA_REGISTER 0x08 + + +#define Z8530_Status_Is_RX_character_available( _status ) \ + ( (_status) & 0x01 ) + +#define Z8530_Status_Is_TX_buffer_empty( _status ) \ + ( (_status) & 0x04 ) + +#define Z8530_Status_Is_break_abort( _status ) \ + ( (_status) & 0x80 ) + +typedef struct { + unsigned char read_setup; + unsigned char write_setup; + unsigned char mask_value; +} char_size_info; + +static const char_size_info Char_size_85c30[] = { + { Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF }, + { Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F }, + { Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F }, + { Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F } +}; + +static const unsigned char Clock_speed_85c30[] = { + Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK, Z8530_x64_CLOCK }; + +static const unsigned char Stop_bit_85c30[] = { + Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 }; + +static const unsigned char Parity_85c30[] = { + Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN }; + + +/* PAGE + * + * Read_85c30_register + * + * Read a Z85c30 register + */ +static unsigned char Read_85c30_register( + volatile unsigned char *csr, /* IN */ + unsigned char register_number /* IN */ +) +{ + unsigned char Data; + + *csr = register_number; + + delay_in_bus_cycles( 40 ); + + Data = *csr; + + delay_in_bus_cycles( 40 ); + + return Data; +} + +/* + * Write_85c30_register + * + * Write a Z85c30 register + */ +static void Write_85c30_register( + volatile unsigned char *csr, /* IN */ + unsigned char register_number, /* IN */ + unsigned char data /* IN */ +) +{ + *csr = register_number; + + delay_in_bus_cycles( 40 ); + + *csr = data; + + delay_in_bus_cycles( 40 ); +} + + +/* PAGE + * + * Reset_85c30_chip + * + * Reset a 85c30 chip. The pointers for the control registers for both + * ports on the chip are used as input. + */ +void Reset_85c30_chip( + volatile unsigned char *ctrl_0, /* IN */ + volatile unsigned char *ctrl_1 /* IN */ +) +{ + Write_85c30_register( ctrl_0, 0x09, 0x80 ); + Write_85c30_register( ctrl_1, 0x09, 0x40 ); +} + + +/* PAGE + * + * initialize_85c30_port + * + * initialize a z85c30 Port + */ +void initialize_85c30_port( + const Port_85C30_info *Port +) +{ + rtems_unsigned16 value; + volatile unsigned char *ctrl; + Console_Protocol *Setup; + rtems_unsigned16 baud_constant; + + Setup = Port->Protocol; + ctrl = Port->ctrl; + + baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency, + Port->Chip->clock_x, Setup->baud_rate ); + + /* + * Using register 4 + * Set up the clock rate. + */ + value = Clock_speed_85c30[ Port->Chip->clock_speed ] | + Stop_bit_85c30[ Setup->stop_bits ] | + Parity_85c30[ Setup->parity ]; + Write_85c30_register( ctrl, 0x04, value ); + + /* + * Set Write Register 1 to disable all interrupts + */ + Write_85c30_register( ctrl, 1, 0 ); + +#if CONSOLE_USE_INTERRUPTS + /* + * Set Write Register 2 to contain the interrupt vector + */ + Write_85c30_register( ctrl, 2, Port->Chip->vector ); +#endif + + /* + * Set Write Register 3 to disable the Receiver + */ + Write_85c30_register( ctrl, 0x03, 0x00 ); + + /* + * Set Write Register 5 to disable the Transmitter + */ + Write_85c30_register( ctrl, 5, 0x00 ); + + /* WR 6 -- unneeded in asynchronous mode */ + + /* WR 7 -- unneeded in asynchronous mode */ + + /* + * Set Write Register 9 to disable all interrupt sources + */ + Write_85c30_register( ctrl, 9, 0x00 ); + + /* + * Set Write Register 10 for simple Asynchronous operation + */ + Write_85c30_register( ctrl, 0x0a, 0x00 ); + + /* + * Setup the source of the receive and xmit + * clock as BRG output and the transmit clock + * as the output source for TRxC pin via register 11 + */ + Write_85c30_register( ctrl, 0x0b, 0x56 ); + + value = baud_constant; + + /* + * Setup the lower 8 bits time constants = 1E. + * If the time constans = 1E, then the desire + * baud rate will be equilvalent to 9600, via register 12. + */ + Write_85c30_register( ctrl, 0x0c, value & 0xff ); + + /* + * using register 13 + * Setup the upper 8 bits time constants = 0 + */ + Write_85c30_register( ctrl, 0x0d, value>>8 ); + + /* + * Set the DTR/REQ pin goes low when transmit + * buffer becomes empty and enable the baud + * rate generator enable with clock from the + * SCC's PCLK input via register 14. + */ + Write_85c30_register( ctrl, 0x0e, 0x07 ); + + /* + * Set Write Register 3 : Base Value is xx00_000x + * D6 - D7 : Receive Character Length (configured) + * D5 : Auto Enable (forced value) + * D4 : Enter Hunt Phase (forced value) + * D3 : Receive CRC Enable (forced value) + * D2 : Address Search Mode (0 if not SDLC) (forced value) + * D1 : Sync Character Load Inhibit (forced value) + * D0 : Receiver Enable (configured) + */ + value = 0x01; + value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup; + + Write_85c30_register( ctrl, 0x03, value ); + + /* + * Set Write Register 5 : Base Value is 0xx0_x000 + * D7 : Data Terminal Ready (DTR) (forced value) + * D5 - D6 : Transmit Character Length (configured) + * D4 : Send Break (forced value) + * D3 : Transmitter Enable (configured) + * D2 : CRC Select (forced value) + * D1 : Request to Send (forced value) + * D0 : Transmit CRC Enable (forced value) + */ + value = 0x8a; + value = value | Char_size_85c30[ Setup->write_char_bits ].write_setup; + Write_85c30_register( ctrl, 0x05, value ); + + /* + * Reset Tx UNDERRUN/EOM LATCH and ERROR + * via register 0 + */ + Write_85c30_register( ctrl, 0x00, 0xf0 ); + +#if CONSOLE_USE_INTERRUPTS + /* + * Set Write Register 1 to interrupt on Rx characters or special condition. + */ + Write_85c30_register( ctrl, 1, 0x10 ); +#endif + + /* + * Set Write Register 15 to disable extended functions. + */ + + Write_85c30_register( ctrl, 15, 0x00 ); + + /* + * Set the Command Register to Reset Ext/STATUS. + */ + Write_85c30_register( ctrl, 0x00, 0x10 ); + +#if CONSOLE_USE_INTERRUPTS + + /* + * Set Write Register 1 : Base Value is 0001_0110 + * Enables Rx interrupt on all characters and special conditions. + * Enables parity as a special condition. + * Enables Tx interrupt. + */ + Write_85c30_register( ctrl, 1, 0x16 ); + + /* + * Set Write Register 9 to enable all interrupt sources + * Changed from 0 to a + */ + Write_85c30_register( ctrl, 9, 0x0A ); + + + /* XXX */ + + /* + * Issue reset highest Interrupt Under Service (IUS) command. + */ + Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 ); + +#endif + +} + +/* PAGE + * + * outbyte_polled_85c30 + * + * This routine transmits a character using polling. + */ + +void outbyte_polled_85c30( + volatile unsigned char *csr, /* IN */ + char ch /* IN */ +) +{ + unsigned char z8530_status; + rtems_unsigned32 isrlevel; + + rtems_interrupt_disable( isrlevel ); + + /* + * Wait for the Transmit buffer to indicate that it is empty. + */ + do { + z8530_status = Read_85c30_register( csr, STATUS_REGISTER ); + } while ( !Z8530_Status_Is_TX_buffer_empty( z8530_status ) ); + + /* + * Write the character. + */ + Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch ); + + rtems_interrupt_enable( isrlevel ); +} + +/* PAGE + * + * inbyte_nonblocking_85c30 + * + * This routine polls for a character. + */ + +int inbyte_nonblocking_85c30( + const Port_85C30_info *Port +) +{ + volatile unsigned char *csr; + unsigned char z8530_status; + rtems_unsigned8 data; + + csr = Port->ctrl; + + /* + * return -1 if a character is not available. + */ + z8530_status = Read_85c30_register( csr, STATUS_REGISTER ); + if ( !Z8530_Status_Is_RX_character_available( z8530_status ) ) + return -1; + + /* + * Return the character read. + */ + data = Read_85c30_register( csr, DATA_REGISTER ); + data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value; + + return data; +} + + +/* + * Interrupt driven console IO + */ + +#if CONSOLE_USE_INTERRUPTS + +/*PAGE + * + * Z8530_Async_Channel_ISR + * + */ +/* RR0 */ + +rtems_isr ISR_85c30_Async( + const Port_85C30_info *Port +) +{ + rtems_unsigned16 status; + volatile Console_Protocol *Protocol; + unsigned char data; + rtems_boolean did_something = FALSE; + + Protocol = Port->Protocol; + + status = Read_85c30_register( Port->ctrl, 0x00 ); + + /* + * Was this a RX interrupt? If so, then process it. + */ + + if ( Z8530_Status_Is_RX_character_available( status ) ) { + data = Read_85c30_register( Port->ctrl, DATA_REGISTER ); + data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value; + + rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data, + &data, 1 ); + did_something = TRUE; + } + + /* + * Was this a TX empty interrupt? If so, then process it. + */ + + if (Z8530_Status_Is_TX_buffer_empty( status ) ) { + if ( !Ring_buffer_Is_empty( &Protocol->TX_Buffer ) ) { + Ring_buffer_Remove_character( &Protocol->TX_Buffer, data ); + Write_85c30_register( Port->ctrl, DATA_REGISTER, data ); + + } else { + Protocol->Is_TX_active = FALSE; + Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x28 ); + } + + did_something = TRUE; + } + + /* + * Issue reset highest Interrupt Under Service (IUS) command. + */ + + /* + if ( did_something ) + */ + Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 ); +} + +#endif + diff --git a/c/src/lib/libbsp/powerpc/score603e/console/85c30.h b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h new file mode 100644 index 0000000000..cacdfd0bb9 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h @@ -0,0 +1,56 @@ +/* 85c30.h + * + * This include file contains z85c30 chip information. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __85c30_H +#define __85c30_H + +/* + * Clock Speed Definations + */ + +#define Z8530_x1_CLOCK 0x00 +#define Z8530_x16_CLOCK 0x40 +#define Z8530_x32_CLOCK 0x80 +#define Z8530_x64_CLOCK 0xC0 + +/* + * Number of Stop Bits. + */ +#define Z8530_STOP_BITS_1 0x04 +#define Z8530_STOP_BITS_1_AND_A_HALF 0x08 +#define Z8530_STOP_BITS_2 0x0C + +/* + * PARITY + */ +#define Z8530_PARITY_NONE 0x00 +#define Z8530_PARITY_ODD 0x01 +#define Z8530_PARITY_EVEN 0x03 + +/* + * Character Bits + */ +#define Z8530_READ_CHARACTER_BITS_8 0xC0 +#define Z8530_READ_CHARACTER_BITS_7 0x40 +#define Z8530_READ_CHARACTER_BITS_6 0x80 +#define Z8530_READ_CHARACTER_BITS_5 0x00 + +#define Z8530_WRITE_CHARACTER_BITS_8 0x60 +#define Z8530_WRITE_CHARACTER_BITS_7 0x20 +#define Z8530_WRITE_CHARACTER_BITS_6 0x40 +#define Z8530_WRITE_CHARACTER_BITS_5 0x00 + +#endif + diff --git a/c/src/lib/libbsp/powerpc/score603e/console/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/console/Makefile.in new file mode 100644 index 0000000000..f0a1233ce6 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/console/Makefile.in @@ -0,0 +1,56 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +PGM=${ARCH}/console.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=85c30 console tbl85c30 +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +SRCS=$(C_FILES) $(H_FILES) +OBJS=$(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/score603e/console/console.c b/c/src/lib/libbsp/powerpc/score603e/console/console.c new file mode 100644 index 0000000000..a3836bd6a8 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/console/console.c @@ -0,0 +1,497 @@ +/* + * This file contains the TTY driver for the serial ports on the SCORE603e. + * + * This driver uses the termios pseudo driver. + * + * Currently only polled mode is supported. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <bsp.h> +#include <rtems/libio.h> +#include <stdlib.h> +#include <assert.h> + +#include "consolebsp.h" + +#if (1) +/* + * The Port Used for the Console interface is based upon which + * debugger is being used. The SDS debugger uses a binary + * interface on port 0 as part of the debugger. Thus port 0 can + * not be used as the console port for the SDS debugger. + */ + +#if (SCORE603E_USE_SDS) +#define USE_FOR_CONSOLE_DEF 1 + +#elif (SCORE603E_USE_OPEN_FIRMWARE) +#define USE_FOR_CONSOLE_DEF 0 + +#elif (SCORE603E_USE_NONE) +#define USE_FOR_CONSOLE_DEF 0 + +#elif (SCORE603E_USE_DINK) +#define USE_FOR_CONSOLE_DEF 0 + +#else +#error "SCORE603E CONSOLE.C -- what ROM monitor are you using" +#endif + +#endif + +#if (0) +extern int USE_FOR_CONSOLE; +#endif + +int USE_FOR_CONSOLE = USE_FOR_CONSOLE_DEF; + +/* + * + * Console Device Driver Entry Points + */ + +/* PAGE + * + * DEBUG_puts + * + * This should be safe in the event of an error. It attempts to insure + * that no TX empty interrupts occur while it is doing polled IO. Then + * it restores the state of that external interrupt. + * + * Input parameters: + * string - pointer to debug output string + * + * Output parameters: NONE + * + * Return values: NONE + */ + +void DEBUG_puts( + char *string +) +{ + char *s; + int console; + volatile rtems_unsigned8 *csr; + + console = USE_FOR_CONSOLE; + + csr = Ports_85C30[ console ].ctrl; + + /* should disable interrupts here */ + + for ( s = string ; *s ; s++ ) + outbyte_polled_85c30( csr, *s ); + + outbyte_polled_85c30( csr, '\r' ); + outbyte_polled_85c30( csr, '\n' ); + + /* should enable interrupts here */ +} + +/* PAGE + * + * console_inbyte_nonblocking + * + * Console Termios polling input entry point. + */ + +int console_inbyte_nonblocking( + int minor +) +{ + int port = minor; + + /* + * verify port Number + */ + assert ( port < NUM_Z85C30_PORTS ); + + /* + * return a character from the 85c30 port. + */ + return inbyte_nonblocking_85c30( &Ports_85C30[ port ] ); +} + + +void console_reserve_resources( + rtems_configuration_table *configuration +) +{ + rtems_termios_reserve_resources( configuration, NUM_Z85C30_PORTS ); +} + + +rtems_device_driver console_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return rtems_termios_close (arg); +} + +rtems_device_driver console_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return rtems_termios_read (arg); +} + +rtems_device_driver console_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return rtems_termios_write (arg); +} + +rtems_device_driver console_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return rtems_termios_ioctl (arg); +} + + + +/* + * Interrupt driven console IO + */ + +#if CONSOLE_USE_INTERRUPTS + +rtems_isr console_isr( + rtems_vector_number vector +) +{ + int i; + + for (i=0; i < NUM_Z85C30_PORTS; i++){ + ISR_85c30_Async( &Ports_85C30[i] ); + +#if (0) /* XXX - TO TEST LOOP BACKS comment this out. */ + if ( Ports_85C30[i].Chip->vector == vector ) { + ISR_85c30_Async( &Ports_85C30[i] ); + } +#endif + } +} + +void console_exit() +{ + int i; + volatile Ring_buffer_t *buffer; + rtems_unsigned32 ch; + + for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) { + + buffer = &( Ports_85C30[i].Protocol->TX_Buffer); + + while ( !Ring_buffer_Is_empty( buffer ) ) { + Ring_buffer_Remove_character( buffer, ch ); + outbyte_polled_85c30( Ports_85C30[i].ctrl, ch ); + } + } +} + +void console_initialize_interrupts( void ) +{ + volatile Ring_buffer_t *buffer; + Console_Protocol *protocol; + int i; + + for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) { + protocol = Ports_85C30[i].Protocol; + + /* + * Initialize the ring buffer and set to not transmitting. + */ + buffer = &protocol->TX_Buffer; + Ring_buffer_Initialize( buffer ); + protocol->Is_TX_active = FALSE; + } + + /* + * Connect each vector to the interupt service routine. + */ + for (i=0; i < NUM_Z85C30_CHIPS; i++) + set_vector( console_isr, Chips_85C30[i].vector, 1 ); + + + atexit( console_exit ); + +} +void console_outbyte_interrupts( + const Port_85C30_info *Port, + char ch +); + +/* XXXXXX */ +#endif + + +/* PAGE + * + * console_initialize + * + * Routine called to initialize the console device driver. + */ +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code status; + rtems_device_minor_number console; + int port, chip, p0,p1; + + /* + * initialize the termio interface. + */ + rtems_termios_initialize(); + + /* + * Register Device Names + */ + console = USE_FOR_CONSOLE; + status = rtems_io_register_name( "/dev/console", major, console ); + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred(status); + + /* + * Initialize Hardware + */ + + +/* + * INITIALIZE_COM_PORTS is defined in the linker script. If it is + * true all serial chips on the board are to be reset at startup + * otherwise the reset is assumed to occur elsewhere (ie. in the + * debugger...) + */ +#if ( INITIALIZE_COM_PORTS ) + + /* + * Force to perform a hardware reset w/o + * Master interrupt enable via register 9 + */ + + for (port=0; port<NUM_Z85C30_PORTS; port++){ + p0 = port; + port++; + p1 = port; + Reset_85c30_chip( Ports_85C30[p0].ctrl, Ports_85C30[p1].ctrl ); + } +#else + /* TEMP - To see if this makes a diff with the new ports. + * Never reset chip 1 when using the chip as a monitor + */ + for (port=2; port<NUM_Z85C30_PORTS; port++){ + p0 = port; + port++; + p1 = port; + Reset_85c30_chip( Ports_85C30[p0].ctrl, Ports_85C30[p1].ctrl ); + } +#endif + + /* + * Initialize each port. + * Note: the ports are numbered such that 0,1 are on the first chip + * 2,3 are on the second .... + */ + + for (port=0; port<NUM_Z85C30_PORTS; port++) { + chip = port >> 1; + initialize_85c30_port( &Ports_85C30[port] ); + } + +#if CONSOLE_USE_INTERRUPTS + console_initialize_interrupts(); +#endif + + return RTEMS_SUCCESSFUL; +} + +/* PAGE + * + * console_write_support + * + * Console Termios output entry point. + * + */ +int console_write_support( + int minor, + const char *buf, + int len) +{ + int nwrite = 0; + volatile rtems_unsigned8 *csr; + int port = minor; + + /* + * verify port Number + */ + assert ( port < NUM_Z85C30_PORTS ); + + /* + * Set the csr based upon the port number. + */ + csr = Ports_85C30[ port ].ctrl; + + /* + * poll each byte in the string out of the port. + */ + while (nwrite < len) { +#if (CONSOLE_USE_INTERRUPTS) + console_outbyte_interrupts( &Ports_85C30[ port ], *buf++ ); +#else + outbyte_polled_85c30( csr, *buf++ ); +#endif + nwrite++; + } + + /* + * return the number of bytes written. + */ + return nwrite; +} + +/* PAGE + * + * console_open + * + * open a port as a termios console. + * + */ +rtems_device_driver console_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + rtems_status_code sc; + int port = minor; +#if (CONSOLE_USE_INTERRUPTS) + rtems_libio_open_close_args_t *args = arg; + static const rtems_termios_callbacks intrCallbacks = { + NULL, /* firstOpen */ + NULL, /* lastClose */ + NULL, /* pollRead */ + console_write_support, /* write */ + NULL, /* setAttributes */ + NULL, /* stopRemoteTx */ + NULL, /* startRemoteTx */ + 1 /* outputUsesInterrupts */ + }; +#else + static const rtems_termios_callbacks pollCallbacks = { + NULL, /* firstOpen */ + NULL, /* lastClose */ + console_inbyte_nonblocking, /* pollRead */ + console_write_support, /* write */ + NULL, /* setAttributes */ + NULL, /* stopRemoteTx */ + NULL, /* startRemoteTx */ + 0 /* outputUsesInterrupts */ + }; +#endif + + + /* + * Verify the minor number is valid. + */ + if (minor < 0) + return RTEMS_INVALID_NUMBER; + + if ( port > NUM_Z85C30_PORTS ) + return RTEMS_INVALID_NUMBER; + + /* + * open the port as a termios console driver. + */ + +#if (CONSOLE_USE_INTERRUPTS) + sc = rtems_termios_open( major, minor, arg, &intrCallbacks ); + + Ports_85C30[ minor ].Protocol->console_termios_data = args->iop->data1; +#else + sc = rtems_termios_open( major, minor, arg, &pollCallbacks ); +#endif + + return sc; +} + + +#if (CONSOLE_USE_INTERRUPTS) + +/* + * console_outbyte_interrupts + * + * This routine transmits a character out. + * + * Input parameters: + * port - port to transmit character to + * ch - character to be transmitted + * + * Output parameters: NONE + * + * Return values: NONE + */ +void console_outbyte_interrupts( + const Port_85C30_info *Port, + char ch +) +{ + Console_Protocol *protocol; + rtems_unsigned32 isrlevel; + + protocol = Port->Protocol; + + /* + * If this is the first character then we need to prime the pump + */ + + if ( protocol->Is_TX_active == FALSE ) { + + rtems_interrupt_disable( isrlevel ); + protocol->Is_TX_active = TRUE; + outbyte_polled_85c30( Port->ctrl, ch ); + rtems_interrupt_enable( isrlevel ); + + return; + } + + while ( Ring_buffer_Is_full( &protocol->TX_Buffer ) ); + + Ring_buffer_Add_character( &protocol->TX_Buffer, ch ); +} + +#endif + + + + + + + + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h new file mode 100644 index 0000000000..2c5016890c --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h @@ -0,0 +1,152 @@ +/* consolebsp.h + * + * This include file contains all console driver definations + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __CONSOLEBSP_H +#define __CONSOLEBSP_H + +#include <rtems.h> +#include <ringbuf.h> + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * + * Note: The Ports are numbered 0..NUM_Z85C30_CHIPS with port 0 and 1 + * being on the first chip, and ports 2 and 3 being on the + * second chip... + */ + + +/* + * Z85c30 configuration informaiton. + */ + +#if (HAS_PMC_PSC8) +#define NUM_Z85C30_CHIPS_ON_MEZZANINE 4 +#else +#define NUM_Z85C30_CHIPS_ON_MEZZANINE 0 +#endif + +#define NUM_Z85C30_CHIPS (2 + NUM_Z85C30_CHIPS_ON_MEZZANINE) +#define NUM_Z85C30_PORTS (NUM_Z85C30_CHIPS * 2) + +typedef enum { + CONSOLE_x1_CLOCK, + CONSOLE_x16_CLOCK, + CONSOLE_x32_CLOCK, + CONSOLE_x64_CLOCK, +} CONSOLE_Clock_speed; + +typedef enum { + CONSOLE_STOP_BITS_1, + CONSOLE_STOP_BITS_1_AND_A_HALF, + CONSOLE_STOP_BITS_2, +} CONSOLE_Stop_bits; + +typedef enum { + CONSOLE_PARITY_NONE, + CONSOLE_PARITY_ODD, + CONSOLE_PARITY_EVEN, +} CONSOLE_Parity; + +typedef enum { + CONSOLE_CHARACTER_BITS_8, + CONSOLE_CHARACTER_BITS_7, + CONSOLE_CHARACTER_BITS_6, + CONSOLE_CHARACTER_BITS_5, +} CONSOLE_Character_bits; + +typedef struct { + rtems_unsigned32 baud_rate; /* baud rate value */ + CONSOLE_Stop_bits stop_bits; + CONSOLE_Parity parity; + CONSOLE_Character_bits read_char_bits; + CONSOLE_Character_bits write_char_bits; + +#if CONSOLE_USE_INTERRUPTS + volatile Ring_buffer_t TX_Buffer; /* Transmit Buffer */ + volatile rtems_boolean Is_TX_active; /* Transmitting */ + void *console_termios_data; +#endif + +} Console_Protocol; + + +/* + * Structure used for chip level information. + */ +typedef struct { + rtems_unsigned32 vector; + rtems_unsigned32 clock_frequency; + rtems_unsigned16 clock_x; + CONSOLE_Clock_speed clock_speed; +} Chip_85C30_info; + +/* + * Structure used for port level informaiton. + */ +typedef struct { + + volatile unsigned char *ctrl; /* Port Ctrl byte */ + volatile unsigned char *data; /* Port data byte */ + + unsigned char port; /* Port-id / minor # */ + + Console_Protocol *Protocol; + Chip_85C30_info *Chip; /* Chip specific info */ + +} Port_85C30_info; + +/* + * Console port chip configuration tables. + */ +extern Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ]; +extern const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ]; + + +/* + * 85c30.c prototypes. + */ +void initialize_85c30_port( + const Port_85C30_info *Port +); + +void outbyte_polled_85c30( + volatile unsigned char *csr, /* IN */ + char ch +); + +int inbyte_nonblocking_85c30( + const Port_85C30_info *Port +); + +void Reset_85c30_chip( + volatile unsigned char *ctrl_0, + volatile unsigned char *ctrl_1 +); + +#if CONSOLE_USE_INTERRUPTS +rtems_isr ISR_85c30_Async( + const Port_85C30_info *Port +); +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c new file mode 100644 index 0000000000..349f669fc8 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c @@ -0,0 +1,198 @@ + /* + * This file contains the table for the z85c30 port + * used by the console driver. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#include "consolebsp.h" +#include <bsp.h> + +#define CONSOLE_DEFAULT_BAUD_RATE 9600 +#define CONSOLE_DEFAULT_BAUD_CONSTANT Score603e_Z8530_Chip0_Baud(9600) + +#define CONSOLE_DEFAULT_STOP_BITS CONSOLE_STOP_BITS_1 +#define CONSOLE_DEFAULT_PARITY CONSOLE_PARITY_NONE +#define CONSOLE_DEFAULT_READ_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8 +#define CONSOLE_DEFAULT_WRITE_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8 +#define CONSOLE_DEFAULT_CONSOLE_CLOCK CONSOLE_x16_CLOCK + + +#define DEFAULT_PROTOCOL { CONSOLE_DEFAULT_BAUD_RATE, \ + CONSOLE_DEFAULT_STOP_BITS, \ + CONSOLE_DEFAULT_PARITY, \ + CONSOLE_DEFAULT_READ_CHARACTER_BITS, \ + CONSOLE_DEFAULT_WRITE_CHARACTER_BITS } + +/* + * Tables of information necessary to use the console 85c30 routines. + */ +Console_Protocol Protocols_85c30 [ NUM_Z85C30_PORTS ] = +{ + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + +#if (HAS_PMC_PSC8) + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, + DEFAULT_PROTOCOL, +#endif +}; + +/* + * Table of chip unique information for each chip. + * See consolebsp.h for the Chip_85C30_info structure defination. + */ +Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] = +{ + { + SCORE603E_85C30_0_IRQ, + SCORE603E_85C30_0_CLOCK, + SCORE603E_85C30_0_CLOCK_X, + CONSOLE_DEFAULT_CONSOLE_CLOCK + }, + { + SCORE603E_85C30_1_IRQ, + SCORE603E_85C30_1_CLOCK, + SCORE603E_85C30_1_CLOCK_X, + CONSOLE_DEFAULT_CONSOLE_CLOCK + }, + +#if (HAS_PMC_PSC8) + { + SCORE603E_85C30_2_IRQ, + SCORE603E_85C30_2_CLOCK, + SCORE603E_85C30_2_CLOCK_X, + CONSOLE_DEFAULT_CONSOLE_CLOCK + }, + { + SCORE603E_85C30_3_IRQ, + SCORE603E_85C30_3_CLOCK, + SCORE603E_85C30_3_CLOCK_X, + CONSOLE_DEFAULT_CONSOLE_CLOCK + }, + { + SCORE603E_85C30_4_IRQ, + SCORE603E_85C30_4_CLOCK, + SCORE603E_85C30_4_CLOCK_X, + CONSOLE_DEFAULT_CONSOLE_CLOCK + }, + { + SCORE603E_85C30_5_IRQ, + SCORE603E_85C30_5_CLOCK, + SCORE603E_85C30_5_CLOCK_X, + CONSOLE_DEFAULT_CONSOLE_CLOCK + }, +#endif + +}; + +/* + * Table of port unique information for each port. + * See consolebsp.h for the Port_85C30_info structure defination. + */ +const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ] = { + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_0, + (volatile unsigned char *) SCORE603E_85C30_DATA_0, + 0x00, + &Protocols_85c30[0], + &Chips_85C30[0], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_1, + (volatile unsigned char *) SCORE603E_85C30_DATA_1, + 0x01, + &Protocols_85c30[1], + &Chips_85C30[0], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_2, + (volatile unsigned char *) SCORE603E_85C30_DATA_2, + 0x02, + &Protocols_85c30[2], + &Chips_85C30[1], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_3, + (volatile unsigned char *) SCORE603E_85C30_DATA_3, + 0x03, + &Protocols_85c30[3], + &Chips_85C30[1], + }, + +#if defined(HAS_PMC_PSC8) + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_4, + (volatile unsigned char *) SCORE603E_85C30_DATA_4, + 0x04, + &Protocols_85c30[4], + &Chips_85C30[2], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_5, + (volatile unsigned char *) SCORE603E_85C30_DATA_5, + 0x05, + &Protocols_85c30[5], + &Chips_85C30[2], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_6, + (volatile unsigned char *) SCORE603E_85C30_DATA_6, + 0x06, + &Protocols_85c30[6], + &Chips_85C30[3], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_7, + (volatile unsigned char *) SCORE603E_85C30_DATA_7, + 0x07, + &Protocols_85c30[7], + &Chips_85C30[3], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_8, + (volatile unsigned char *) SCORE603E_85C30_DATA_8, + 0x08, + &Protocols_85c30[8], + &Chips_85C30[4], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_9, + (volatile unsigned char *) SCORE603E_85C30_DATA_9, + 0x09, + &Protocols_85c30[9], + &Chips_85C30[4], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_10, + (volatile unsigned char *) SCORE603E_85C30_DATA_10, + 0x0a, + &Protocols_85c30[10], + &Chips_85C30[5], + }, + { + (volatile unsigned char *) SCORE603E_85C30_CTRL_11, + (volatile unsigned char *) SCORE603E_85C30_DATA_11, + 0x0b, + &Protocols_85c30[11], + &Chips_85C30[5], + }, +#endif +}; + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/include/Makefile.in new file mode 100644 index 0000000000..d206d1d37b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/Makefile.in @@ -0,0 +1,38 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +H_FILES = $(srcdir)/bsp.h $(srcdir)/coverhd.h $(srcdir)/chain.h \ + $(srcdir)/gen1.h $(srcdir)/gen2.h $(srcdir)/tod.h + +# +# Equate files are for including from assembly preprocessed by +# gm4 or gasp. No examples are provided except for those for +# other CPUs. The best way to generate them would be to +# provide a program which generates the constants used based +# on the C equivalents. +# +# If you add equate files, don't forget to uncomment the install line +# below. +# + +EQ_FILES = + +SRCS=$(H_FILES) $(EQ_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: $(SRCS) + $(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE) diff --git a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h new file mode 100644 index 0000000000..2888a1dc9a --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h @@ -0,0 +1,261 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __BSP_h +#define __BSP_h + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include <rtems.h> +#include <console.h> +#include <clockdrv.h> +#include <iosupp.h> + + +#if (SCORE603E_GENERATION == 1) +#include <gen1.h> +#elif (SCORE603E_GENERATION == 2) +#include <gen2.h> +#else +#error "Unknown Generation of Score603e" +#endif + + +/* + * The following macro calculates the Baud constant. For the Z8530 chip. + * + * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 + * for the Score603e ((10,000,000 / 16) / (2 * Baud Rate)) - 2 + */ +#define _Score603e_Z8530_Baud( _frequency, _clock_by, _baud_rate ) \ + ( (_frequency /( _clock_by * 2 * _baud_rate)) - 2) + +#define Score603e_Z8530_Chip1_Baud( _value ) \ + _Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \ + SCORE603E_85C30_1_CLOCK_X, _value ) + +#define Score603e_Z8530_Chip0_Baud( _value ) \ + _Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \ + SCORE603E_85C30_0_CLOCK_X, _value ) + +#define Initialize_Board_ctrl_register() \ + *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \ + SCORE603E_BRD_FLASH_DISABLE_MASK) \ + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( _handler ) \ + set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 ) + +#define Cause_tm27_intr() \ + do { \ + unsigned32 _clicks = 8; \ + asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + + +#define Clear_tm27_intr() \ + do { \ + unsigned32 _clicks = 0xffffffff; \ + asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + unsigned32 _msr = 0; \ + _ISR_Set_level( 0 ); \ + asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + + +/* Constants */ + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + + +/* + * Information placed in the linkcmds file. + */ + +extern int RAM_START; +extern int RAM_END; +extern int RAM_SIZE; + +extern int PROM_START; +extern int PROM_END; +extern int PROM_SIZE; + +extern int CLOCK_SPEED; +extern int CPU_PPC_CLICKS_PER_MS; + +extern int end; /* last address in the program */ + +/* + * How many libio files we want + */ + +#define BSP_LIBIO_MAX_FDS 20 + +/* functions */ + +void bsp_start( void ); + +void bsp_cleanup( void ); + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +/* + * spurious.c + */ +rtems_isr bsp_stub_handler( + rtems_vector_number trap +); +rtems_isr bsp_spurious_handler( + rtems_vector_number trap +); +void bsp_spurious_initialize(); + +/* + * genvec.c + */ +rtems_isr_entry set_EE_vector( + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector /* vector number */ +); +void initialize_external_exception_vector (); + +/* + * console.c + */ +void DEBUG_puts( char *string ); + +void BSP_fatal_return( void ); + +/* + * Hwr_init.c + */ +void init_PCI(); +void instruction_cache_enable (); +void data_cache_enable (); + + +void initialize_PCI_bridge (); +rtems_unsigned16 read_and_clear_irq (); +void set_irq_mask( + rtems_unsigned16 value +); +rtems_unsigned16 get_irq_mask(); + +/* + * universe.c + */ +void initialize_universe(); + +void set_irq_mask( + rtems_unsigned16 value +); + +rtems_unsigned16 get_irq_mask(); + +void unmask_irq( + rtems_unsigned16 irq_idx +); + +void init_irq_data_register(); + +rtems_unsigned16 read_and_clear_PMC_irq( + rtems_unsigned16 irq +); + +rtems_boolean Is_PMC_IRQ( + rtems_unsigned32 pmc_irq, + rtems_unsigned16 status_word +); + +rtems_unsigned16 read_and_clear_irq(); + +/* + * FPGA.c + */ +void initialize_PCI_bridge (); + +/* flash.c */ + +unsigned int SCORE603e_FLASH_Disable( + rtems_unsigned32 unused +); +unsigned int SCORE603e_FLASH_verify_enable(); +unsigned int SCORE603e_FLASH_Enable_writes( + rtems_unsigned32 area /* Unused */ +); + +#define Convert_Endian_32( _data ) \ + ( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) | \ + ((_data&0x00ff0000)>>8) | ((_data&0xff000000)>>24) ) + +#define Convert_Endian_16( _data ) \ + ( ((_data&0x00ff)<<8) | ((_data&0xff00)>>8) ) + +extern rtems_configuration_table BSP_Configuration; /* owned by BSP */ +extern rtems_cpu_table Cpu_table; /* owned by BSP */ +extern rtems_unsigned32 bsp_isr_level; + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/chain.h b/c/src/lib/libbsp/powerpc/score603e/include/chain.h new file mode 100644 index 0000000000..98cf2b1a86 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/chain.h @@ -0,0 +1,362 @@ +/* chain.h + * + * This include file contains all the constants and structures associated + * with doubly linked chains. This file actually just provides an + * interface to the chain object in rtems. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $ld: + */ + +#ifndef __CHAIN_h +#define __CHAIN_h + +#include <rtems.h> + +/* + * Chain_Initialize + * + * This routine initializes the_chain structure to manage the + * contiguous array of number_nodes nodes which starts at + * starting_address. Each node is of node_size bytes. + * + * Chain_Control *the_chain, * IN * + * void *starting_address, * IN * + * rtems_unsigned32 number_nodes, * IN * + * rtems_unsigned32 node_size * IN * + */ + +#define Chain_Initialize( the_chain, starting_address, \ + number_nodes, node_size ) \ + _Chain_Initialize( the_chain, starting_address, \ + number_nodes, node_size ) \ + + +/* + * Chain_Initialize_empty + * + * This routine initializes the specified chain to contain zero nodes. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Initialize_empty( the_chain ) \ + _Chain_Initialize_empty( the_chain ) + + +/* + * Chain_Are_nodes_equal + * + * This function returns TRUE if LEFT and RIGHT are equal, + * and FALSE otherwise. + * + * Chain_Node *left, * IN * + * Chain_Node *right * IN * + */ + +#define Chain_Are_nodes_equal( left, right ) \ + _Chain_Are_nodes_equal( left, right ) + + +/* + * Chain_Extract_unprotected + * + * This routine extracts the_node from the chain on which it resides. + * It does NOT disable interrupts to insure the atomicity of the + * extract operation. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Extract_unprotected( the_node ) \ + _Chain_Extract_unprotected( the_node ) + + +/* + * Chain_Extract + * + * This routine extracts the_node from the chain on which it resides. + * It disables interrupts to insure the atomicity of the + * extract operation. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Extract( the_node ) \ + _Chain_Extract( the_node ) + + +/* + * Chain_Get_unprotected + * + * This function removes the first node from the_chain and returns + * a pointer to that node. If the_chain is empty, then NULL is returned. + * It does NOT disable interrupts to insure the atomicity of the + * get operation. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Get_unprotected( the_chain ) \ + _Chain_Get_unprotected( the_chain ) + + +/* + * Chain_Get + * + * This function removes the first node from the_chain and returns + * a pointer to that node. If the_chain is empty, then NULL is returned. + * It disables interrupts to insure the atomicity of the + * get operation. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Get( the_chain ) \ + _Chain_Get( the_chain ) + + +/* + * Chain_Get_first_unprotected + * + * This function removes the first node from the_chain and returns + * a pointer to that node. It does NOT disable interrupts to insure + * the atomicity of the get operation. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Get_first_unprotected( the_chain ) \ + _Chain_Get_first_unprotected( the_chain ) + + +/* + * Chain_Insert_unprotected + * + * This routine inserts the_node on a chain immediately following + * after_node. It does NOT disable interrupts to insure the atomicity + * of the extract operation. + * + * Chain_Node *after_node, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Insert_unprotected( after_node, the_node ) \ + _Chain_Insert_unprotected( after_node, the_node ) + + +/* + * Chain_Insert + * + * This routine inserts the_node on a chain immediately following + * after_node. It disables interrupts to insure the atomicity + * of the extract operation. + * + * Chain_Node *after_node, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Insert( after_node, the_node ) \ + _Chain_Insert( after_node, the_node ) + + +/* + * Chain_Append_unprotected + * + * This routine appends the_node onto the end of the_chain. + * It does NOT disable interrupts to insure the atomicity of the + * append operation. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Append_unprotected( the_chain, the_node ) \ + _Chain_Append_unprotected( the_chain, the_node ) + + +/* + * Chain_Append + * + * This routine appends the_node onto the end of the_chain. + * It disables interrupts to insure the atomicity of the + * append operation. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Append( the_chain, the_node ) \ + _Chain_Append( the_chain, the_node ) + + +/* + * Chain_Prepend_unprotected + * + * This routine prepends the_node onto the front of the_chain. + * It does NOT disable interrupts to insure the atomicity of the + * prepend operation. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Prepend_unprotected( the_chain, the_node ) \ + _Chain_Prepend_unprotected( the_chain, the_node ) + + +/* + * Chain_Prepend + * + * This routine prepends the_node onto the front of the_chain. + * It disables interrupts to insure the atomicity of the + * prepend operation. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Prepend( the_chain, the_node ) \ + _Chain_Prepend( the_chain, the_node ) + + +/* + * Chain_Head + * + * This function returns a pointer to the first node on the chain. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Head( the_chain ) \ + _Chain_Head( the_chain ) + + +/* + * Chain_Tail + * + * This function returns a pointer to the last node on the chain. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Tail( the_chain ) \ + _Chain_Tail( the_chain ) + + +/* + * Chain_Is_head + * + * This function returns TRUE if the_node is the head of the_chain and + * FALSE otherwise. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_head( the_chain, the_node ) \ + _Chain_Is_head( the_chain, the_node ) + + +/* + * Chain_Is_tail + * + * This function returns TRUE if the_node is the tail of the_chain and + * FALSE otherwise. + * + * Chain_Control *the_chain, * IN * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_tail( the_chain, the_node ) \ + _Chain_Is_tail( the_chain, the_node ) + + +/* + * Chain_Is_first + * + * This function returns TRUE if the_node is the first node on a chain and + * FALSE otherwise. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_first( the_node ) \ + _Chain_Is_first( the_node ) + + +/* + * Chain_Is_last + * + * This function returns TRUE if the_node is the last node on a chain and + * FALSE otherwise. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_last( the_node ) \ + _Chain_Is_last( the_node ) + + +/* + * Chain_Is_empty + * + * This function returns TRUE if there are no nodes on the_chain and + * FALSE otherwise. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Is_empty( the_chain ) \ + _Chain_Is_empty( the_chain ) + + +/* + * Chain_Has_only_one_node + * + * This function returns TRUE if there is only one node on the_chain and + * FALSE otherwise. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Has_only_one_node( the_chain ) \ + _Chain_Has_only_one_node( the_chain ) + + +/* + * Chain_Is_null + * + * This function returns TRUE if the_chain is NULL and FALSE otherwise. + * + * Chain_Control *the_chain * IN * + */ + +#define Chain_Is_null( the_chain ) \ + _Chain_Is_null( the_chain ) + + +/* + * Chain_Is_null_node + * + * This function returns TRUE if the_node is NULL and FALSE otherwise. + * + * Chain_Node *the_node * IN * + */ + +#define Chain_Is_null_node( the_node ) \ + _Chain_Is_null_node( the_node ) + + +#undef __RTEMS_APPLICATION__ +#include <rtems/score/chain.inl> +#define __RTEMS_APPLICATION__ +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h new file mode 100644 index 0000000000..69d300365c --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h @@ -0,0 +1,139 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include + * calling overhead including passing of arguments. + * + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +/* + * These are set to 0 for now. + * + * Units are 100ns. + * + * These numbers are of questionable use, as they are developed by calling + * the routine many times, thus getting its entry veneer into the (small) + * cache on the 403GA. This in general is not true of the RTEMS timing + * tests, which usually call a routine only once, thus having no cache loaded + * advantage. + * + * Whether the directive times are useful after deducting the function call + * overhead is also questionable. The user is more interested generally + * in the total cost of a directive, not the cost if the procedure call + * is inlined! (In general this is not true). + * + * Andrew Bray 18/08/1995 + * + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 +#define CALLING_OVERHEAD_TASK_CREATE 0 +#define CALLING_OVERHEAD_TASK_IDENT 0 +#define CALLING_OVERHEAD_TASK_START 0 +#define CALLING_OVERHEAD_TASK_RESTART 0 +#define CALLING_OVERHEAD_TASK_DELETE 0 +#define CALLING_OVERHEAD_TASK_SUSPEND 0 +#define CALLING_OVERHEAD_TASK_RESUME 0 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 +#define CALLING_OVERHEAD_TASK_MODE 0 +#define CALLING_OVERHEAD_TASK_GET_NOTE 0 +#define CALLING_OVERHEAD_TASK_SET_NOTE 0 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 +#define CALLING_OVERHEAD_CLOCK_GET 0 +#define CALLING_OVERHEAD_CLOCK_SET 0 +#define CALLING_OVERHEAD_CLOCK_TICK 0 + +#define CALLING_OVERHEAD_TIMER_CREATE 0 +#define CALLING_OVERHEAD_TIMER_IDENT 0 +#define CALLING_OVERHEAD_TIMER_DELETE 0 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 0 +#define CALLING_OVERHEAD_TIMER_RESET 0 +#define CALLING_OVERHEAD_TIMER_CANCEL 0 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 + +#define CALLING_OVERHEAD_EVENT_SEND 0 +#define CALLING_OVERHEAD_EVENT_RECEIVE 0 +#define CALLING_OVERHEAD_SIGNAL_CATCH 0 +#define CALLING_OVERHEAD_SIGNAL_SEND 0 +#define CALLING_OVERHEAD_PARTITION_CREATE 0 +#define CALLING_OVERHEAD_PARTITION_IDENT 0 +#define CALLING_OVERHEAD_PARTITION_DELETE 0 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 +#define CALLING_OVERHEAD_REGION_CREATE 0 +#define CALLING_OVERHEAD_REGION_IDENT 0 +#define CALLING_OVERHEAD_REGION_DELETE 0 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 +#define CALLING_OVERHEAD_PORT_CREATE 0 +#define CALLING_OVERHEAD_PORT_IDENT 0 +#define CALLING_OVERHEAD_PORT_DELETE 0 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 + +#define CALLING_OVERHEAD_IO_INITIALIZE 0 +#define CALLING_OVERHEAD_IO_OPEN 0 +#define CALLING_OVERHEAD_IO_CLOSE 0 +#define CALLING_OVERHEAD_IO_READ 0 +#define CALLING_OVERHEAD_IO_WRITE 0 +#define CALLING_OVERHEAD_IO_CONTROL 0 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/gen1.h b/c/src/lib/libbsp/powerpc/score603e/include/gen1.h new file mode 100644 index 0000000000..048c101382 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/gen1.h @@ -0,0 +1,155 @@ +/* Gen1.h + * + * This include file contains all Generation 1 board addreses + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __SCORE_GENERATION_1_h +#define __SCORE_GENERATION_1_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems.h> + +/* + * ISA/PCI I/O space. + */ +#define SCORE603E_VME_JUMPER_ADDR 0x00e20000 +#define SCORE603E_FLASH_BASE_ADDR 0x01000000 +#define SCORE603E_ISA_PCI_IO_BASE 0x80000000 +#define SCORE603E_TIMER_PORT_C 0x80000278 +#define SCORE603E_TIMER_INT_ACK 0x8000027a +#define SCORE603E_TIMER_PORT_B 0x8000027b +#define SCORE603E_TIMER_PORT_A 0x8000027c +#define SCORE603E_85C30_CTRL_1 ((volatile rtems_unsigned8 *)0x800002f8) +#define SCORE603E_85C30_INT_ACK ((volatile rtems_unsigned8 *)0x800002fa) +#define SCORE603E_85C30_CTRL_0 ((volatile rtems_unsigned8 *)0x800002fb) +#define SCORE603E_85C30_DATA_1 ((volatile rtems_unsigned8 *)0x800002fc) +#define SCORE603E_85C30_DATA_0 ((volatile rtems_unsigned8 *)0x800002ff) +#define SCORE603E_85C30_CTRL_3 ((volatile rtems_unsigned8 *)0x800003f8) +#define SCORE603E_85C30_CTRL_2 ((volatile rtems_unsigned8 *)0x800003fb) +#define SCORE603E_85C30_DATA_3 ((volatile rtems_unsigned8 *)0x800003fc) +#define SCORE603E_85C30_DATA_2 ((volatile rtems_unsigned8 *)0x800003ff) +#define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8 +#define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc + +#define SCORE603E_UNIVERSE_BASE 0x80030000 +#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000 +#define SCORE603E_PCI_MEM_BASE 0xc0000000 +#define SCORE603E_NVRAM_BASE 0xc00f0000 +#define SCORE603E_RTC_ADDRESS ((volatile unsigned char *)0xc00f1ff8) +#define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000 +#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000 + +#define SCORE603E_VME_A16_OFFSET 0x04000000 +#define SCORE603E_VME_A16_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET) + +#define SCORE603E_BOARD_CTRL_REG ((volatile rtems_unsigned32*)0x80000800) +#define SCORE603E_BRD_FLASH_DISABLE_MASK 0x02000000 + + /* + * Z85C30 Definations for the 232 interface. + */ +#define SCORE603E_85C30_0_CLOCK 10000000 /* 10,000,000 */ +#define SCORE603E_85C30_0_CLOCK_X 16 + +/* + * Z85C30 Definations for the 422 interface. + */ +#define SCORE603E_85C30_1_CLOCK 10000000 /* 10,000,000 */ +#define SCORE603E_85C30_1_CLOCK_X 16 + + +#define SCORE603E_UNIVERSE_CHIP_ID 0x000010E3 + +/* + * Score603e Interupt Definations. + */ + +/* + * First Score Unique IRQ + */ +#define Score_IRQ_First ( PPC_IRQ_LAST + 1 ) + +/* + * 82378ZB IRQ definations. + */ +#define SCORE603E_IRQ00_82378ZB ( Score_IRQ_First + 0 ) +#define SCORE603E_IRQ01_82378ZB ( Score_IRQ_First + 1 ) +#define SCORE603E_IRQ02_82378ZB ( Score_IRQ_First + 2 ) +#define SCORE603E_IRQ03_82378ZB ( Score_IRQ_First + 3 ) +#define SCORE603E_IRQ04_82378ZB ( Score_IRQ_First + 4 ) +#define SCORE603E_IRQ05_82378ZB ( Score_IRQ_First + 5 ) +#define SCORE603E_IRQ06_82378ZB ( Score_IRQ_First + 6 ) +#define SCORE603E_IRQ07_82378ZB ( Score_IRQ_First + 7 ) +#define SCORE603E_IRQ08_82378ZB ( Score_IRQ_First + 8 ) +#define SCORE603E_IRQ09_82378ZB ( Score_IRQ_First + 9 ) +#define SCORE603E_IRQ10_82378ZB ( Score_IRQ_First + 10 ) +#define SCORE603E_IRQ11_82378ZB ( Score_IRQ_First + 11 ) +#define SCORE603E_IRQ12_82378ZB ( Score_IRQ_First + 12 ) +#define SCORE603E_IRQ13_82378ZB ( Score_IRQ_First + 13 ) +#define SCORE603E_IRQ14_82378ZB ( Score_IRQ_First + 14 ) +#define SCORE603E_IRQ15_82378ZB ( Score_IRQ_First + 15 ) + +#define MAX_BOARD_IRQS SCORE603E_IRQ15_82378ZB + +#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03_82378ZB +#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04_82378ZB +#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ12_82378ZB + + +#define Write_82378ZB( _offset, _data ) { \ + volatile rtems_unsigned8 *addr; \ + addr = (volatile rtems_unsigned8 *)(SCORE603E_ISA_PCI_IO_BASE + _offset);\ + *addr = _data; } + +#define Read_82378ZB( _offset, _data ) { \ + volatile rtems_unsigned8 *addr; \ + addr = (volatile rtems_unsigned8 *)(SCORE603E_ISA_PCI_IO_BASE + _offset);\ + _data = *addr; } + + +/* + * BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer + * driver. + */ + +#define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */ + /* to start/stop the timer. */ +#define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */ + +/* + * Convert decrement value to tenths of microsecnds (used by + * shared timer driver). + * + * + CPU has a 66.67 Mhz bus, + * + There are 4 bus cycles per click + * + We return value in 1/10 microsecond units. + * Modified following equation to integer equation to remove + * floating point math. + * (int) ((float)(_value) / ((66.67 * 0.1) / 4.0)) + */ + +#define BSP_Convert_decrementer( _value ) \ + (int) (((_value) * 4000) / 6667) + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/gen2.h b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h new file mode 100644 index 0000000000..a157109d24 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h @@ -0,0 +1,276 @@ +/* Gen2.h + * + * This include file contains all Generation 2 board addreses + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __SCORE_GENERATION_2_h +#define __SCORE_GENERATION_2_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems.h> + +/* + * ISA/PCI I/O space. + */ +#define SCORE603E_VME_JUMPER_ADDR 0x00e20000 +#define SCORE603E_FLASH_BASE_ADDR 0x04000000 +#define SCORE603E_ISA_PCI_IO_BASE 0x80000000 +#define SCORE603E_TIMER_PORT_C 0xfd000000 +#define SCORE603E_TIMER_INT_ACK 0xfd000000 +#define SCORE603E_TIMER_PORT_B 0xfd000008 +#define SCORE603E_TIMER_PORT_A 0xfd000004 + +#define SCORE603E_BOARD_CTRL_REG ((volatile rtems_unsigned8 *)0xfd00002c) +#define SCORE603E_BRD_FLASH_DISABLE_MASK 0x40 + +#define SCORE603E_85C30_CTRL_0 ((volatile rtems_unsigned8 *)0xfe200020) +#define SCORE603E_85C30_DATA_0 ((volatile rtems_unsigned8 *)0xfe200024) +#define SCORE603E_85C30_CTRL_1 ((volatile rtems_unsigned8 *)0xfe200028) +#define SCORE603E_85C30_DATA_1 ((volatile rtems_unsigned8 *)0xfe20002c) +#define SCORE603E_85C30_CTRL_2 ((volatile rtems_unsigned8 *)0xfe200000) +#define SCORE603E_85C30_DATA_2 ((volatile rtems_unsigned8 *)0xfe200004) +#define SCORE603E_85C30_CTRL_3 ((volatile rtems_unsigned8 *)0xfe200008) +#define SCORE603E_85C30_DATA_3 ((volatile rtems_unsigned8 *)0xfe20000c) + +/* + * PSC8 - PMC Card + */ +#define SCORE603E_PCI_CONFIGURATION_BASE 0x80800000 +#define SCORE603E_PMC_BASE SCORE603E_PCI_CONFIGURATION_BASE +#define SCORE603E_PCI_PMC_DEVICE_BASE 0x80808000 + +#define SCORE603E_PCI_REGISTER_BASE 0xfc000000 + +#define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \ + ((volatile rtems_unsigned32 *)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset )) + + +#define SCORE603E_PMC_SERIAL_ADDRESS( _offset ) \ + ((volatile rtems_unsigned8 *)(SCORE603E_PCI_REGISTER_BASE + _offset)) + +/* + * PMC serial channels - (4-7: 232 and 8-11: 422) + */ +#define SCORE603E_85C30_CTRL_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200020) +#define SCORE603E_85C30_DATA_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200024) +#define SCORE603E_85C30_CTRL_5 SCORE603E_PMC_SERIAL_ADDRESS(0x200028) +#define SCORE603E_85C30_DATA_5 SCORE603E_PMC_SERIAL_ADDRESS(0x20002c) +#define SCORE603E_85C30_CTRL_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200030) +#define SCORE603E_85C30_DATA_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200034) +#define SCORE603E_85C30_CTRL_7 SCORE603E_PMC_SERIAL_ADDRESS(0x200038) +#define SCORE603E_85C30_DATA_7 SCORE603E_PMC_SERIAL_ADDRESS(0x20003c) +#define SCORE603E_85C30_CTRL_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200000) +#define SCORE603E_85C30_DATA_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200004) +#define SCORE603E_85C30_CTRL_9 SCORE603E_PMC_SERIAL_ADDRESS(0x200008) +#define SCORE603E_85C30_DATA_9 SCORE603E_PMC_SERIAL_ADDRESS(0x20000c) +#define SCORE603E_85C30_CTRL_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200010) +#define SCORE603E_85C30_DATA_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200014) +#define SCORE603E_85C30_CTRL_11 SCORE603E_PMC_SERIAL_ADDRESS(0x200018) +#define SCORE603E_85C30_DATA_11 SCORE603E_PMC_SERIAL_ADDRESS(0x20001c) + +#define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8 +#define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc + +#define SCORE603E_UNIVERSE_BASE 0x80030000 +#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000 +#define SCORE603E_PCI_MEM_BASE 0xc0000000 +#define SCORE603E_NVRAM_BASE 0xfd100000 +#define SCORE603E_RTC_ADDRESS ((volatile unsigned char *)0xfd180000) +#define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000 +#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000 + + +#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) +#define SCORE603E_VME_A16_OFFSET 0x04000000 +#elif (SCORE603E_USE_DINK) +#define SCORE603E_VME_A16_OFFSET 0x11000000 +#define SCORE603E_VME_A24_OFFSET 0x10000000 +#define SCORE603E_VME_A24_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET) +#else +#error "SCORE603E gen2.h -- what ROM monitor are you using" +#endif + +#define SCORE603E_VME_A16_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET) + +/* + * Definations for the ICM 1770 RTC chip + */ + /* + * These values are programed into a register and must not be changed. + */ +#define ICM1770_CRYSTAL_FREQ_32K 0x00 +#define ICM1770_CRYSTAL_FREQ_1M 0x01 +#define ICM1770_CRYSTAL_FREQ_2M 0x02 +#define ICM1770_CRYSTAL_FREQ_4M 0x03 + +#define SCORE_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K + +/* + * Z85C30 Definations for the 423 interface. + */ +#define SCORE603E_85C30_0_CLOCK 14745600 /* 10,000,000 ?10->14.5 */ +#define SCORE603E_85C30_0_CLOCK_X 16 + +/* + * Z85C30 Definations for the 422 interface. + */ +#define SCORE603E_85C30_1_CLOCK 16000000 /* 10,000,000 ?10->14.5 */ +#define SCORE603E_85C30_1_CLOCK_X 16 + +/* + * Z85C30 Definations for the PMC serial chips + */ +#define SCORE603E_85C30_PMC_CLOCK 16000000 /* 10,000,000 ?10->14.5 */ +#define SCORE603E_85C30_PMC_CLOCK_X 16 + +#define SCORE603E_85C30_2_CLOCK SCORE603E_85C30_PMC_CLOCK +#define SCORE603E_85C30_3_CLOCK SCORE603E_85C30_PMC_CLOCK +#define SCORE603E_85C30_4_CLOCK SCORE603E_85C30_PMC_CLOCK +#define SCORE603E_85C30_5_CLOCK SCORE603E_85C30_PMC_CLOCK +#define SCORE603E_85C30_2_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X +#define SCORE603E_85C30_3_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X +#define SCORE603E_85C30_4_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X +#define SCORE603E_85C30_5_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X + + +#define SCORE603E_UNIVERSE_CHIP_ID 0x000010E3 + +/* + * FPGA Interupt Address Definations. + */ +#define SCORE603E_FPGA_VECT_DATA ((volatile rtems_unsigned16 *)0xfd000040) +#define SCORE603E_FPGA_BIT1_15_0 ((volatile rtems_unsigned16 *)0xfd000044) +#define SCORE603E_FPGA_MASK_DATA ((volatile rtems_unsigned16 *)0xfd000048) +#define SCORE603E_FPGA_IRQ_INPUT ((volatile rtems_unsigned16 *)0xfd00004c) + +/* + * The PMC status word is at the PMC base address + */ +#define SCORE603E_PMC_STATUS_ADDRESS (SCORE603E_PMC_SERIAL_ADDRESS (0)) +#define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80) /* SCC 422-1 */ +#define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40) /* SCC 232-1 */ +#define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20) /* SCC 422-2 */ +#define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08) /* SCC 232-2 */ + +#define SCORE603E_PMC_CONTROL_ADDRESS SCORE603E_PMC_SERIAL_ADDRESS(0x100000) +#define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20) + +#define PMC_SET_232_LOOPBACK(_word) (_word | 0x02) +#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd) +#define PMC_SET_422_LOOPBACK(_word) (_word | 0x01) +#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe) + + +/* + * Score603e Interupt Definations. + */ + +/* + * First Score Unique IRQ + */ +#define Score_IRQ_First ( PPC_IRQ_LAST + 1 ) + +/* + * The Following Are part of a Score603e FPGA. + */ +#define SCORE603E_IRQ00 ( Score_IRQ_First + 0 ) +#define SCORE603E_IRQ01 ( Score_IRQ_First + 1 ) +#define SCORE603E_IRQ02 ( Score_IRQ_First + 2 ) +#define SCORE603E_IRQ03 ( Score_IRQ_First + 3 ) +#define SCORE603E_IRQ04 ( Score_IRQ_First + 4 ) +#define SCORE603E_IRQ05 ( Score_IRQ_First + 5 ) +#define SCORE603E_IRQ06 ( Score_IRQ_First + 6 ) +#define SCORE603E_IRQ07 ( Score_IRQ_First + 7 ) +#define SCORE603E_IRQ08 ( Score_IRQ_First + 8 ) +#define SCORE603E_IRQ09 ( Score_IRQ_First + 9 ) +#define SCORE603E_IRQ10 ( Score_IRQ_First + 10 ) +#define SCORE603E_IRQ11 ( Score_IRQ_First + 11 ) +#define SCORE603E_IRQ12 ( Score_IRQ_First + 12 ) +#define SCORE603E_IRQ13 ( Score_IRQ_First + 13 ) +#define SCORE603E_IRQ14 ( Score_IRQ_First + 14 ) +#define SCORE603E_IRQ15 ( Score_IRQ_First + 15 ) + +#define SCORE603E_TIMER1_IRQ SCORE603E_IRQ00 +#define SCORE603E_TIMER2_IRQ SCORE603E_IRQ01 +#define SCORE603E_TIMER3_IRQ SCORE603E_IRQ02 +#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03 +#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04 +#define SCORE603E_RTC_IRQ SCORE603E_IRQ05 +#define SCORE603E_PCI_IRQ_0 SCORE603E_IRQ06 +#define SCORE603E_PCI_IRQ_1 SCORE603E_IRQ07 +#define SCORE603E_PCI_IRQ_2 SCORE603E_IRQ08 +#define SCORE603E_PCI_IRQ_3 SCORE603E_IRQ09 +#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ10 +#define SCORE603E_1553_IRQ SCORE603E_IRQ11 +#define SCORE603E_MAIL_BOX_IRQ_0 SCORE603E_IRQ12 +#define SCORE603E_MAIL_BOX_IRQ_1 SCORE603E_IRQ13 +#define SCORE603E_MAIL_BOX_IRQ_2 SCORE603E_IRQ14 +#define SCORE603E_MAIL_BOX_IRQ_3 SCORE603E_IRQ15 + +/* + * The Score FPGA maps all interrupts comming from the PMC card to + * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be + * read to indicate which interrupt was chained to the FPGA. + */ +#define SCORE603E_IRQ16 ( Score_IRQ_First + 16 ) +#define SCORE603E_IRQ17 ( Score_IRQ_First + 17 ) +#define SCORE603E_IRQ18 ( Score_IRQ_First + 18 ) +#define SCORE603E_IRQ19 ( Score_IRQ_First + 19 ) + +/* + * IRQ'a read from the PMC card + */ +#define SCORE603E_85C30_4_IRQ SCORE603E_IRQ16 /* SCC 422-1 */ +#define SCORE603E_85C30_2_IRQ SCORE603E_IRQ17 /* SCC 232-1 */ +#define SCORE603E_85C30_5_IRQ SCORE603E_IRQ18 /* SCC 422-2 */ +#define SCORE603E_85C30_3_IRQ SCORE603E_IRQ19 /* SCC 232-2 */ + +#define MAX_BOARD_IRQS SCORE603E_IRQ19 + + +/* + * BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer + * driver. + */ + +#define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */ + /* to start/stop the timer. */ +#define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */ + +/* + * Convert decrement value to tenths of microsecnds (used by + * shared timer driver). + * + * + CPU has a 66.67 Mhz bus, + * + There are 4 bus cycles per click + * + We return value in 1/10 microsecond units. + * Modified following equation to integer equation to remove + * floating point math. + * (int) ((float)(_value) / ((66.67 * 0.1) / 4.0)) + */ + +#define BSP_Convert_decrementer( _value ) \ + (int) (((_value) * 4000) / 6667) + +#endif + +#ifdef __cplusplus +} +#endif + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/include/tod.h b/c/src/lib/libbsp/powerpc/score603e/include/tod.h new file mode 100644 index 0000000000..d51ceb23b9 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/include/tod.h @@ -0,0 +1,38 @@ +/* + * Real Time Clock (MK48T08) for RTEMS on Score603e + * + * Based on MVME162 TOD by: + * COPYRIGHT (C) 1997 + * by Katsutoshi Shibuya - BU Denken Co.,Ltd. - Sapporo - JAPAN + * ALL RIGHTS RESERVED + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + + +#ifndef TOD_H +#define TOD_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern void setRealTimeToRTEMS(); +/* Read real time from RTC and set it to RTEMS' clock manager */ + +extern void setRealTimeFromRTEMS(); +/* Read time from RTEMS' clock manager and set it to RTC */ + +extern int checkRealTime(); +/* Return the difference between RTC and RTEMS' clock manager time in minutes. + If the difference is greater than 1 day, this returns 9999. */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libbsp/powerpc/score603e/start/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/start/Makefile.in new file mode 100644 index 0000000000..972a64f5de --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/start/Makefile.in @@ -0,0 +1,56 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +PGMS=${ARCH}/start.o + +# C source names, if any, go here -- minus the .c +C_PIECES= +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .S +S_PIECES=start +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: ${ARCH} $(SRCS) $(OBJS) $(PGM) + $(INSTALL_VARIANT) -m 555 ${PGMS} ${PROJECT_RELEASE}/lib diff --git a/c/src/lib/libbsp/powerpc/score603e/start/start.S b/c/src/lib/libbsp/powerpc/score603e/start/start.S new file mode 100644 index 0000000000..9f4befee7d --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/start/start.S @@ -0,0 +1,155 @@ +/* + * This is based on the mvme-crt0.S file from libgloss/rs6000. + * crt0.S -- startup file for PowerPC systems. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + * $Id$ + */ +#include <rtems/score/targopts.h> +#include "ppc-asm.h" + + .file "start.s" + .section ".got2","aw" + .align 2 + +.LCTOC1 = .+32768 + + .extern FUNC_NAME(atexit) + .globl FUNC_NAME(__atexit) + .section ".sdata","aw" + .align 2 +FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ + .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ + + .section ".fixup","aw" + .align 2 + .long FUNC_NAME(__atexit) + + .section ".got2","aw" +.Ltable = .-.LCTOC1 + .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ + +.Lbss_start = .-.LCTOC1 + .long _edata /* includes sbss and bss */ + +.Lend = .-.LCTOC1 + .long _end + +.Lstack = .-.LCTOC1 /* stack address if set by user */ + .long __stack + + .text +.Lptr: + .long .LCTOC1-.Laddr + + .globl _start + .type _start,@function +_start: + b past_constants + /* Set MSR */ + .long _etext /* end of code space */ + .long _edata /* end of code and data space */ + +past_constants: + lis r5,0 + mr r4,r5 + ori r4,r4,0x0000 /* 0x2030 */ + mtmsr r4 + +#if (SCORE603E_GENERATION == 1) + lis r4,0 + mtspr 530,r4 /* Set IBAT1U */ + mtspr 531,r4 /* Set IBAT1L */ + mtspr 534,r4 /* Set IBAT3U */ + mtspr 535,r4 /* Set IBAT3L */ + mtspr 538,r4 /* Set DBAT1U */ + mtspr 539,r4 /* Set DBAT1L */ + lis r4,0 + ori r4,r4,0x1fff + mtspr 528,r4 /* Set IBAT0U */ + mtspr 536,r4 /* Set DBAT0U */ + lis r4,0 + ori r4,r4,0x0002 + mtspr 529,r4 /* Set IBAT0L */ + mtspr 537,r4 /* Set DBAT0L */ + lis r4,-4096 /* 0xf000 */ + ori r4,r4,8191 /* 0x1fff */ + mtspr 532,r4 /* Set IBAT2U */ + mtspr 540,r4 /* Set DBAT2U */ + lis r4,-4096 /* 0xf000 */ + ori r4,r4,1 + mtspr 533,r4 /* Set IBAT2L */ + mtspr 541,r4 /* Set DBAT2L */ + lis r4,-32768 /* 0x8000 */ + ori r4,r4,8191 /* 0x1fff */ + mtspr 542,r4 /* Set DBAT3U */ + lis r4,-32768 /* 0x8000 */ + ori r4,r4,0x003a + mtspr 543,r4 /* Set DBAT3L */ + +#elif (SCORE603E_GENERATION == 2) +/* XXX FILL THIS IN WHEN I GET HELLO TO COME UP. */ + +#else +#error "Unknown Generation of Score603e" +#endif + + bl .Laddr /* get current address */ +.Laddr: + mflr r4 /* real address of .Laddr */ + lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ + add r5,r5,r4 /* correct to real pointer */ + lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ + subf r4,r4,r5 /* calculate difference between where linked and current */ + + /* clear bss */ + lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ + lwz r7,.Lend(r5) /* calculate end of the BSS */ + add r6,r6,r4 /* adjust pointers */ + add r7,r7,r4 + + cmplw 1,r6,r7 + bc 4,4,.Ldone + + subf r8,r6,r7 /* number of bytes to zero */ + srwi r9,r8,2 /* number of words to zero */ + mtctr r9 + li r0,0 /* zero to clear memory */ + addi r6,r6,-4 /* adjust so we can use stwu */ +.Lloop: + stwu r0,4(r6) /* zero bss */ + bdnz .Lloop + +.Ldone: + + lwz r0,.Lstack(r5) /* stack address or 0 */ + cmplwi 1,r0,0 /* equal to 0? */ + bc 12,6,.Lnostack /* use default stack if == 0 */ + mr sp,r0 /* use user defined stack */ + +.Lnostack: + /* set up initial stack frame */ + addi sp,sp,-4 /* make sure we don't overwrite debug mem */ + lis r0,0 + stw r0,0(sp) /* clear back chain */ + stwu sp,-56(sp) /* push another stack frame */ + + /* Let her rip */ + bl FUNC_NAME(boot_card) + + /* return value from boot_card is argument to exit */ + bl FUNC_NAME(exit) + trap +.Lstart: + .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/82378zb.c b/c/src/lib/libbsp/powerpc/score603e/startup/82378zb.c new file mode 100644 index 0000000000..f3b1b314e2 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/82378zb.c @@ -0,0 +1,158 @@ +/* 82378zb.c + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ +#include <bsp.h> +#include <rtems/libio.h> + +#include <libcsupport.h> + +#include <string.h> +#include <fcntl.h> +#include <assert.h> +/* + * initialize 82378zb + */ +void initialize_PCI_bridge () +{ + + /* + * INT CNTRL-1 ICW1 + * LTIM and ICW4 + */ + Write_82378ZB( 0x20, 0x19); + + /* + * INT CNTRL-1 ICW 2 + * Sets 5 msbs of the base address in the interrupt vector table + * for the vector routines to 0100 0 ?? + */ + Write_82378ZB( 0x21, 0x40 ); + + /* + * INT CNTRL-1 ICW 3 + * Cascade CNTRL-2 INT output to IRQ[2] input of CNTRL-1 + */ + Write_82378ZB( 0x21, 0x04 ); + + /* + * INT CNTRL-1 ICW 4 + * Set Microprocessor mode for 80x86 system. + */ + Write_82378ZB( 0x21, 0x01 ); + + /* + * INT CNTRL-1 OCW 2 + * Set Non-specific EOI command + */ + Write_82378ZB( 0x20, 0x20 ); + + /* + * INT CNTRL-1 OCW 3 + * Interrupt controller in normal mask mode. + * Disable Poll mode command + * Read IRQ register. + */ + Write_82378ZB( 0x20, 0x2a ); + + /* + * INT CNTRL-1 OCW 1 + * Write Interrupt Request mask for IRQ[7:0]. An interrupt request for + * a masked IRQ will not set the interrupt request register (IRR) bit for + * that channel. + * + * XXXX - Was 0xfd Only allowing Timer interrupt through changed to + * 0xe1. + */ + Write_82378ZB( 0x21, 0xe1 ); + + /* + * INT CNTRL-2 ICW 1 + * LTIM and ICW4 + */ + Write_82378ZB( 0xa0, 0x19 ); + + /* + * INT CNTRL-2 ICW 2 + * Sets 5 msbs of the base address in the interrupt vector table + * for the vector routines to 0100 1 ?? + */ + Write_82378ZB( 0xa1, 0x48 ); + + /* + * INT CNTRL-1 ICW 3 + * Slave Identification Code (Must be intialized to 2). + */ + Write_82378ZB( 0xa1, 0x02 ); + + /* + * INT CNTRL-1 ICW 4 + * Set Microprocessor mode for 80x86 system. + */ + Write_82378ZB( 0xa1, 0x01 ); + + /* + * INT CNTRL-1 OCW 2 + * Set Non-specific EOI command + */ + Write_82378ZB( 0xa0, 0x20 ); + + /* + * INT CNTRL-1 OCW 3 + * Interrupt controller in normal mask mode. + * Disable Poll mode command + * Read IRQ register. + */ + Write_82378ZB( 0xa0, 0x2a ); + + /* + * INT CNTRL-1 OCW 1 + * Write Interrupt Request mask for IRQ[7:0]. An interrupt request for + * a masked IRQ will not set the interrupt request register (IRR) bit for + * that channel. + * + * XXXX - All interrupts masked. + */ + Write_82378ZB( 0xa1, 0xff ); +} + + +rtems_unsigned16 read_and_clear_irq () +{ + rtems_unsigned16 irq; + + /* + * XXX - Fix this for all interrupts later + */ + + Write_82378ZB( 0x20, 0x0c); + Read_82378ZB( 0x20, irq ); + irq &= 0x7; + Write_82378ZB( 0x20, 0x20 ); + + return irq; +} + +void init_irq_data_register() +{ + assert (0); +} +rtems_unsigned16 get_irq_mask() +{ + assert (0); + return 0; +} +void set_irq_mask( + rtems_unsigned16 value +) +{ + assert (0); +} diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c b/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c new file mode 100644 index 0000000000..0bc3d48429 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c @@ -0,0 +1,178 @@ +/* FPGA.c + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ +#include <bsp.h> +#include <rtems/libio.h> + +#include <libcsupport.h> + +#include <string.h> +#include <fcntl.h> +#include <assert.h> + +/* + * initialize FPGA + */ +void initialize_PCI_bridge () +{ +#if (!SCORE603E_USE_DINK) + rtems_unsigned16 mask, shift, data; + + shift = SCORE603E_85C30_0_IRQ - Score_IRQ_First; + mask = 1 << shift; + + shift = SCORE603E_85C30_1_IRQ - Score_IRQ_First; + mask = mask & (1 << shift); + + data = *SCORE603E_FPGA_MASK_DATA; + data = ~mask; + + *SCORE603E_FPGA_MASK_DATA = data; +#endif + +} + +void set_irq_mask( + rtems_unsigned16 value +) +{ + rtems_unsigned16 *loc; + + loc = (rtems_unsigned16 *)SCORE603E_FPGA_MASK_DATA; + + *loc = value; +} + +rtems_unsigned16 get_irq_mask() +{ + rtems_unsigned16 *loc; + rtems_unsigned16 value; + + loc = (rtems_unsigned16 *)SCORE603E_FPGA_MASK_DATA; + + value = *loc; + + return value; +} + +void unmask_irq( + rtems_unsigned16 irq_idx +) +{ + rtems_unsigned16 value; + rtems_unsigned32 mask_idx = irq_idx; + + value = get_irq_mask(); + +#if (HAS_PMC_PSC8) + switch (irq_idx + Score_IRQ_First ) { + case SCORE603E_85C30_4_IRQ: + case SCORE603E_85C30_2_IRQ: + case SCORE603E_85C30_5_IRQ: + case SCORE603E_85C30_3_IRQ: + mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First; + break; + default: + break; + } +#endif + + value &= (~(0x1 << mask_idx)); + set_irq_mask( value ); +} + + +void init_irq_data_register() +{ + rtems_unsigned32 index; + rtems_unsigned32 i; + +#if (SCORE603E_USE_DINK) + set_irq_mask( 0xffff ); +#endif + + /* + * Clear any existing interupts from the vector data register. + */ + for (i=0; i<20; i++) { + index = (*SCORE603E_FPGA_VECT_DATA); + if ( (index&0x10) != 0x10 ) + break; + } +} + +rtems_unsigned16 read_and_clear_PMC_irq( + rtems_unsigned16 irq +) +{ + rtems_unsigned16 status_word = irq; + + status_word = (*SCORE603E_PMC_STATUS_ADDRESS); + + return status_word; +} + +rtems_boolean Is_PMC_IRQ( + rtems_unsigned32 pmc_irq, + rtems_unsigned16 status_word +) +{ + rtems_boolean result= FALSE; + + switch(pmc_irq) { + case SCORE603E_85C30_4_IRQ: + result = Is_PMC_85C30_4_IRQ( status_word ); + break; + case SCORE603E_85C30_2_IRQ: + result = Is_PMC_85C30_2_IRQ( status_word ); + break; + case SCORE603E_85C30_5_IRQ: + result = Is_PMC_85C30_5_IRQ( status_word ); + break; + case SCORE603E_85C30_3_IRQ: + result = Is_PMC_85C30_3_IRQ( status_word ); + break; + default: + assert( 0 ); + break; + } + + return result; +} + +rtems_unsigned16 read_and_clear_irq() +{ + rtems_unsigned16 irq; + + irq = (*SCORE603E_FPGA_VECT_DATA); + + if ((irq & 0xffff0) != 0x10) { + DEBUG_puts( "ERROR:: no irq data\n"); + return (irq | 0x80); + } + + irq &=0xf; + + return irq; +} + + + + + + + + + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c new file mode 100644 index 0000000000..6281a31136 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c @@ -0,0 +1,213 @@ +/* Hwr_init.c + * + * $Id: + */ + +#include <bsp.h> + +#define PPC603e_SPR_HID0 1008 +#define PPC603e_SPR_HID1 1009 +#define PPC603e_SPR_IBAT0U 528 +#define PPC603e_SPR_IBAT0L 529 +#define PPC603e_SPR_DBAT0U 536 +#define PPC603e_SPR_DBAT0L 537 +#define PPC603e_SPR_IBAT1U 530 +#define PPC603e_SPR_IBAT1L 531 +#define PPC603e_SPR_DBAT1U 538 +#define PPC603e_SPR_DBAT1L 539 +#define PPC603e_SPR_IBAT2U 532 +#define PPC603e_SPR_IBAT2L 533 +#define PPC603e_SPR_DBAT2U 540 +#define PPC603e_SPR_DBAT2L 541 +#define PPC603e_SPR_IBAT3U 534 +#define PPC603e_SPR_IBAT3L 535 +#define PPC603e_SPR_DBAT3U 542 +#define PPC603e_SPR_DBAT3L 543 +#define PPC603e_SPR_DMISS 976 +#define PPC603e_SPR_DCMP 977 +#define PPC603e_SPR_HASH1 978 +#define PPC603e_SPR_HASH2 979 +#define PPC603e_SPR_IMISS 980 +#define PPC603e_SPR_ICMP 981 +#define PPC603e_SPR_RPA 982 +#define PPC603e_SPR_SDR1 25 +#define PPC603e_SPR_PVR 287 +#define PPC603e_SPR_DAR 19 +#define PPC603e_SPR_SPRG0 272 +#define PPC603e_SPR_SPRG1 273 +#define PPC603e_SPR_SPRG2 274 +#define PPC603e_SPR_SPRG3 275 +#define PPC603e_SPR_DSISR 18 +#define PPC603e_SPR_SRR0 26 +#define PPC603e_SPR_SRR1 27 +#define PPC603e_SPR_TBL_WRITE 284 +#define PPC603e_SPR_TBU_WRITE 285 +#define PPC603e_SPR_DEC 22 +#define PPC603e_SPR_IABR 1010 +#define PPC603e_SPR_EAR 282 + + + +#define PCI_MEM_CMD (SCORE603E_PCI_MEM_BASE >> 16) + + +typedef struct { + rtems_unsigned32 counter_1_100; + rtems_unsigned32 counter_hours; + rtems_unsigned32 counter_min; + rtems_unsigned32 counter_sec; + rtems_unsigned32 counter_month; + rtems_unsigned32 counter_date; + rtems_unsigned32 counter_year; + rtems_unsigned32 counter_day_of_week; + + rtems_unsigned32 RAM_1_100; + rtems_unsigned32 RAM_hours; + rtems_unsigned32 RAM_month; + rtems_unsigned32 RAM_date; + rtems_unsigned32 RAM_year; + rtems_unsigned32 RAM_day_of_week; + + rtems_unsigned32 interupt_status_mask; + rtems_unsigned32 command_register; +}Harris_RTC; + +void init_RTC() +{ + volatile Harris_RTC *the_RTC; + + the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS; + + the_RTC->command_register = 0x0; +} + +void init_PCI() +{ + rtems_unsigned32 value; + +#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) + /* + * NOTE: Accessing any memory location not mapped by the BAT + * registers will cause a TLB miss exception. + * Set the DBAT1 to be configured for 256M of PCI MEM + * at 0xC0000000 with Write-through and Guarded Attributed and + * read/write access allowed + */ + + /* load DBAT1U (spr538) - 256Mbytes, User, Super */ + value = SCORE603E_PCI_MEM_BASE | 0x1FFF; + asm volatile( + "isync;" + "mtspr 538, %0" + : "=r" (value) + : "0" (value) + ); + + /* load DBAT1L (spr539) - Write-through, Guarded and Read/Write */ + value = SCORE603E_PCI_MEM_BASE | 0x0002; + asm volatile ( + "mtspr 539, %0;" + "isync" + : "=r" (value) + : "0" (value) + ); + +#elif (SCORE603E_USE_DINK) + /* DINK Monitor setsup and uses all 4 BAT registers. */ + /* The fourth BAT register can be modified to access this area */ + +#if (0) + /* + * NOTE: Accessing any memory location not mapped by the BAT + * registers will cause a TLB miss exception. + * Set the DBAT3 to be configured for 256M of PCI MEM + * at 0xC0000000 with Write-through and Guarded Attributed and + * read/write access allowed + */ + + /* load DBAT3U (spr542) - 256Mbytes, User, Super */ + value = SCORE603E_PCI_MEM_BASE | 0x1FFF; + asm volatile( + "isync;" + "mtspr 542, %0" + : "=r" (value) + : "0" (value) + ); + + /* load DBAT3L (spr543) - Write-through, Guarded and Read/Write */ + value = SCORE603E_PCI_MEM_BASE | 0x0002; + asm volatile ( + "mtspr 543, %0;" + "isync" + : "=r" (value) + : "0" (value) + ); +#endif + +#else +#error "SCORE603E BSPSTART.C -- what ROM monitor are you using" +#endif +} + +#define PPC_Get_HID0( _value ) \ + do { \ + _value = 0; /* to avoid warnings */ \ + asm volatile( \ + "mfspr %0, 0x3f0;" /* get HID0 */ \ + "isync" \ + : "=r" (_value) \ + : "0" (_value) \ + ); \ + } while (0) + +#define PPC_Set_HID0( _value ) \ + do { \ + asm volatile( \ + "isync;" \ + "mtspr 0x3f0, %0;" /* load HID0 */ \ + "isync" \ + : "=r" (_value) \ + : "0" (_value) \ + ); \ + } while (0) + + +void instruction_cache_enable () +{ + rtems_unsigned32 value; + + /* + * Enable the instruction cache + */ + + PPC_Get_HID0( value ); + + value |= 0x00008000; /* Set ICE bit */ + + PPC_Set_HID0( value ); +} + +void data_cache_enable () +{ + rtems_unsigned32 value; + + /* + * enable data cache + */ + + PPC_Get_HID0( value ); + + value |= 0x00004000; /* set DCE bit */ + + PPC_Set_HID0( value ); +} + + + + + + + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/startup/Makefile.in new file mode 100644 index 0000000000..fcb757dc31 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/Makefile.in @@ -0,0 +1,71 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@:@srcdir@/../../../shared +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +PGM=${ARCH}/startup.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=bspclean bsplibc bsppost bspstart main sbrk setvec \ + Hwr_init spurious genpvec $(STARTUP_PIECES) +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=linkcmds $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# First and second generation use different Bridge chips :( +# C source names, if any, go here -- minus the .c +ifeq ($(SCORE603E_GENERATION),1) +STARTUP_PIECES=82378zb +else +ifeq ($(SCORE603E_GENERATION),2) +STARTUP_PIECES=FPGA +endif # generation 2 +endif # generation 1 + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(INSTALLED_O_FILES) $(PGM) + $(INSTALL) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib + $(INSTALL_VARIANT) $(INSTALLED_O_FILES) ${PROJECT_RELEASE}/lib diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/bspclean.c b/c/src/lib/libbsp/powerpc/score603e/startup/bspclean.c new file mode 100644 index 0000000000..fce38e7b3a --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/bspclean.c @@ -0,0 +1,17 @@ +/* + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +void bsp_cleanup( void ) +{ + asm volatile( "li 10,99" ); /* 0x63 */ + asm volatile( "sc" ); +} diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c new file mode 100644 index 0000000000..a914ded36b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c @@ -0,0 +1,299 @@ +/* bspstart.c + * + * This set of routines starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before any of these are invoked. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#include <bsp.h> +#include <rtems/libio.h> + +#include <libcsupport.h> + +#include <string.h> + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern rtems_configuration_table Configuration; +rtems_configuration_table BSP_Configuration; +rtems_cpu_table Cpu_table; +rtems_unsigned32 bsp_isr_level; + +/* + * Use the shared implementations of the following routines + */ + +void bsp_postdriver_hook(void); +void bsp_libc_init( void *, unsigned32, int ); + +/*PAGE + * + * bsp_pretasking_hook + * + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + */ + +void bsp_pretasking_hook(void) +{ + extern int end; + rtems_unsigned32 heap_start; + rtems_unsigned32 heap_size; + + heap_start = (rtems_unsigned32) &end; + if (heap_start & (CPU_ALIGNMENT-1)) + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + + heap_size = BSP_Configuration.work_space_start - (void *)&end; + heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */ + + bsp_libc_init((void *) heap_start, heap_size, 0); + +#ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); +#endif +} + +/*PAGE + * + * bsp_predriver_hook + * + * Before drivers are setup initialize interupt vectors. + */ + +void init_RTC(); +void initialize_PMC(); + +void bsp_predriver_hook(void) +{ + init_RTC(); + + init_PCI(); + initialize_universe(); + initialize_PCI_bridge (); + +#if (HAS_PMC_PSC8) + initialize_PMC(); +#endif + + /* + * Initialize Bsp General purpose vector table. + */ + initialize_external_exception_vector(); + +#if (0) + /* + * XXX - Modify this to write a 48000000 (loop to self) command + * to each interrupt location. This is better for debug. + */ + bsp_spurious_initialize(); +#endif + +} + +/*PAGE + * + * initialize_PMC + */ + +void initialize_PMC() { + volatile rtems_unsigned32 *PMC_addr; + rtems_unsigned8 data; + +#if (0) /* First Values sent */ + /* + * set PMC base address. + */ + PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 ); + *PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f; + + /* + * Clear status, enable SERR and memory space only. + */ + PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 ); + *PMC_addr = 0x0201ff37; + + /* + * Bit 0 and 1 HI cause Medium Loopback to occur. + */ + PMC_addr = SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 ); + data = *PMC_addr; + /* *PMC_addr = data | 0x3; */ + *PMC_addr = data & 0xfc; + +#endif + + +#if (1) + + /* + * Clear status, enable SERR and memory space only. + */ + PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 ); + *PMC_addr = 0x020080cc; + + /* + * set PMC base address. + */ + PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 ); + *PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f; + + PMC_addr = SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 ); + data = *PMC_addr; + *PMC_addr = data & 0xfc; + +#endif +} + + + +/*PAGE + * + * SCORE603e_bsp_postdriver_hook + * + * Standard post driver hook plus some BSP specific stuff. + */ + +void SCORE603e_bsp_postdriver_hook(void) +{ + + bsp_postdriver_hook(); + + Init_EE_mask_init(); +} + +void bsp_set_trap_vectors( void ); + +/*PAGE + * + * bsp_start + * + * This routine does the bulk of the system initialization. + */ + +void bsp_start( void ) +{ + unsigned char *work_space_start; + unsigned int msr_value = 0x0000; + volatile rtems_unsigned32 *ptr; + + delay( 1000 ); + + /* + * Zero out lots of memory + */ + + memset( + &end, + 0, + (unsigned char *)&RAM_END - (unsigned char *) &end + ); + + /* + * There are multiple ROM monitors available for this board. + */ +#if (SCORE603E_USE_SDS) + + /* + * Write instruction for Unconditional Branch to ROM vector. + */ + + Code = 0x4bf00002; + for (Address = 0x100; Address <= 0xe00; Address += 0x100) { + A_Vector = (unsigned32 *)Address; + Code = 0x4bf00002 + Address; + *A_Vector = Code; + } + + for (Address = 0x1000; Address <= 0x1400; Address += 0x100) { + A_Vector = (unsigned32 *)Address; + Code = 0x4bf00002 + Address; + *A_Vector = Code; + } + + Cpu_table.exceptions_in_RAM = TRUE; + msr_value = 0x2030; + +#elif (SCORE603E_USE_OPEN_FIRMWARE) + Cpu_table.exceptions_in_RAM = TRUE; + msr_value = 0x2030; + +#elif (SCORE603E_USE_NONE) + Cpu_table.exceptions_in_RAM = TRUE; + msr_value = 0x2030; + _CPU_MSR_SET( msr_value ); + bsp_set_trap_vectors(); + +#elif (SCORE603E_USE_DINK) + Cpu_table.exceptions_in_RAM = TRUE; + msr_value = 0x2030; + _CPU_MSR_SET( msr_value ); + + /* + * Override the DINK error on a Decrementor interrupt. + */ + /* org dec_vector - rfi */ + ptr = (rtems_unsigned32 *)0x900; + *ptr = 0x4c000064; + +#else +#error "SCORE603E BSPSTART.C -- what ROM monitor are you using" +#endif + + _CPU_MSR_SET( msr_value ); + + /* + * Need to "allocate" the memory for the RTEMS Workspace and + * tell the RTEMS configuration where it is. This memory is + * not malloc'ed. It is just "pulled from the air". + */ + + work_space_start = + (unsigned char *)&RAM_END - BSP_Configuration.work_space_size; + + if ( work_space_start <= (unsigned char *)&end ) { + DEBUG_puts( "bspstart: Not enough RAM!!!\n" ); + bsp_cleanup(); + } + + BSP_Configuration.work_space_start = work_space_start; + + /* + * Account for the console's resources + */ + + console_reserve_resources( &BSP_Configuration ); + + /* + * initialize the CPU table for this BSP + */ + + /* Cpu_table.exceptions_in_RAM was set above */ + Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ + Cpu_table.predriver_hook = bsp_predriver_hook; /* Init vectors */ + Cpu_table.postdriver_hook = SCORE603e_bsp_postdriver_hook; + Cpu_table.clicks_per_usec = 66 / 4; /* XXX get from linkcmds */ + Cpu_table.do_zero_of_workspace = TRUE; + Cpu_table.interrupt_stack_size = (12 * 1024); + Cpu_table.idle_task_stack_size = (3 * STACK_MINIMUM_SIZE); + +#if ( PPC_USE_DATA_CACHE ) + instruction_cache_enable (); + data_cache_enable (); +#endif +} + diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c b/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c new file mode 100644 index 0000000000..548772ff86 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c @@ -0,0 +1,202 @@ +/* genpvec.c + * + * These routines handle the external exception. Multiple ISRs occur off + * of this one interrupt. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#include <bsp.h> +#include "chain.h" +#include <assert.h> + + +/* + * Proto types for this file + */ + +rtems_isr external_exception_ISR ( + rtems_vector_number vector /* IN */ +); + +#define NUM_LIRQ_HANDLERS 20 +#define NUM_LIRQ ( MAX_BOARD_IRQS - PPC_IRQ_LAST ) + +/* + * Structure to for one of possible multiple interrupt handlers for + * a given interrupt. + */ +typedef struct +{ + Chain_Node Node; + rtems_isr_entry handler; /* isr routine */ + rtems_vector_number vector; /* vector number */ +} EE_ISR_Type; + + +/* Note: The following will not work if we add a method to remove + * handlers at a later time. + */ + EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS]; + rtems_unsigned16 Nodes_Used; + Chain_Control ISR_Array [NUM_LIRQ]; + +/* XXX */ +void init_irq_data_register(); + +void initialize_external_exception_vector () +{ + int i; + rtems_isr_entry previous_isr; + rtems_status_code status; + + Nodes_Used = 0; + + /* + * Mask out all interupts until they have a handler installed. + */ + + for (i=0; i <NUM_LIRQ; i++) + Chain_Initialize_empty( &ISR_Array[i] ); + + init_irq_data_register(); + + /* + * Install external_exception_ISR () as the handler for + * the General Purpose Interrupt. + */ + status = rtems_interrupt_catch( external_exception_ISR, + PPC_IRQ_EXTERNAL, (rtems_isr_entry *) &previous_isr ); +} + +void Init_EE_mask_init() { +; +} + +/* + * This routine installs one of multiple ISRs for the general purpose + * inerrupt. + */ +rtems_isr_entry set_EE_vector( + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector /* vector number */ +) +{ + rtems_unsigned16 vec_idx = vector - Score_IRQ_First; + rtems_unsigned32 index; + + assert (Nodes_Used < NUM_LIRQ_HANDLERS); + + /* + * If we have already installed this handler for this vector, then + * just reset it. + */ + + for ( index=0 ; index <= Nodes_Used ; index++ ) { + if ( ISR_Nodes[index].vector == vector && + ISR_Nodes[index].handler == handler ) + return NULL; + } + + /* + * Doing things in this order makes them more atomic + */ + + Nodes_Used++; + + index = Nodes_Used - 1; + + ISR_Nodes[index].handler = handler; + ISR_Nodes[index].vector = vector; + + /* printf( "Vector Index: %04x, Vector: %d (%x)\n", + vec_idx, vector, vector); */ + + Chain_Append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node ); + + /* + * Unmask the interrupt. + */ + unmask_irq( vec_idx ); + + return NULL; +} + +/* + * This interrupt service routine is called for an External Exception. + */ +rtems_isr external_exception_ISR ( + rtems_vector_number vector /* IN */ +) +{ + rtems_unsigned16 index; + EE_ISR_Type *node; + rtems_unsigned16 value; + char err_msg[100]; + rtems_unsigned16 PMC_irq; + rtems_unsigned16 check_irq; + rtems_unsigned16 status_word; + + index = read_and_clear_irq(); + if ( index >= NUM_LIRQ ) { + sprintf(err_msg,"ERROR:: Invalid interrupt number (%02x)\n", index); + DEBUG_puts( err_msg); + return; + } + +#if (HAS_PMC_PSC8) + PMC_irq = SCORE603E_PCI_IRQ_0 - SCORE603E_IRQ00; + + if (index == PMC_irq) { + status_word = read_and_clear_PMC_irq( index ); + + for (check_irq=SCORE603E_IRQ16; check_irq<=SCORE603E_IRQ19; check_irq++) { + if ( Is_PMC_IRQ( check_irq, status_word )) { + index = check_irq - SCORE603E_IRQ00; + node = (EE_ISR_Type *)(ISR_Array[ index ].first); + + if ( _Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) { + sprintf(err_msg,"ERROR:: check %d interrupt %02d has no isr\n", + check_irq, index); + DEBUG_puts( err_msg); + value = get_irq_mask(); + sprintf(err_msg," Mask = %02x\n", value); + DEBUG_puts( err_msg); + } + while ( !_Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) { + (*node->handler)( node->vector ); + node = (EE_ISR_Type *) node->Node.next; + } + } + } + } + else +#endif + { + node = (EE_ISR_Type *)(ISR_Array[ index ].first); + if ( _Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) { + sprintf(err_msg,"ERROR:: interrupt %02x has no isr\n", index); + DEBUG_puts( err_msg); + value = get_irq_mask(); + sprintf(err_msg," Mask = %02x\n", value); + DEBUG_puts( err_msg); + return; + } + while ( !_Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) { + (*node->handler)( node->vector ); + node = (EE_ISR_Type *) node->Node.next; + } + } + +} + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/linkcmds b/c/src/lib/libbsp/powerpc/score603e/startup/linkcmds new file mode 100644 index 0000000000..9b452bc0c0 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/linkcmds @@ -0,0 +1,181 @@ +OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", + "elf32-powerpc") + +OUTPUT_ARCH(powerpc) +ENTRY(_start) + +/* + * Number of Decrementer countdowns per millisecond + * + * Calculated by: (66 Mhz * 1000) / 4 cycles per click + */ + +PROVIDE(CPU_PPC_CLICKS_PER_MS = 16500); + +MEMORY + { + VECTORS : ORIGIN = 0, LENGTH = 64K + RAM : ORIGIN = 1M, LENGTH = 15M + EPROM : ORIGIN = 0xFFF00000, LENGTH = 0x80000 + } + +SECTIONS +{ + .vectors 0x00100 : + { + *(.vectors) + } + + /* Read-only sections, merged into text segment: */ + /* SDS ROM worked at 0x30000 */ + . = 0x100000; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rela.text : { *(.rela.text) } + .rela.data : { *(.rela.data) } + .rela.rodata : { *(.rela.rodata) } + .rela.got : { *(.rela.got) } + .rela.got1 : { *(.rela.got1) } + .rela.got2 : { *(.rela.got2) } + .rela.ctors : { *(.rela.ctors) } + .rela.dtors : { *(.rela.dtors) } + .rela.init : { *(.rela.init) } + .rela.fini : { *(.rela.fini) } + .rela.bss : { *(.rela.bss) } + .rela.plt : { *(.rela.plt) } + .rela.sdata : { *(.rela.sdata2) } + .rela.sbss : { *(.rela.sbss2) } + .rela.sdata2 : { *(.rela.sdata2) } + .rela.sbss2 : { *(.rela.sbss2) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.descriptors) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >RAM + .init : { *(.init) } >RAM + .fini : { *(.fini) } >RAM + .rodata : { *(.rodata) } >RAM + .rodata1 : { *(.rodata1) } >RAM + _etext = .; + PROVIDE (etext = .); + PROVIDE (__SDATA2_START__ = .); + .sdata2 : { *(.sdata2) } >RAM + .sbss2 : { *(.sbss2) } >RAM + PROVIDE (__SBSS2_END__ = .); + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. It would + be more correct to do this: + . = ALIGN(0x40000) + (ALIGN(8) & (0x40000 - 1)); + The current expression does not correctly handle the case of a + text segment ending precisely at the end of a page; it causes the + data segment to skip a page. The above expression does not have + this problem, but it will currently (2/95) cause BFD to allocate + a single segment, combining both text and data, for this case. + This will prevent the text segment from being shared among + multiple executions of the program; I think that is more + important than losing a page of the virtual address space (note + that no actual memory is lost; the page which is skipped can not + be referenced). */ + . = ALIGN(8) + 0x40000; + PROVIDE (sdata = .); + .data : + { + *(.data) + CONSTRUCTORS + } >RAM + PROVIDE (__EXCEPT_START__ = .); + .gcc_except_table : { *(.gcc_except_table) } >RAM + PROVIDE (__EXCEPT_END__ = .); + + .data1 : { *(.data1) } >RAM + .got1 : { *(.got1) } >RAM + .dynamic : { *(.dynamic) } >RAM + /* Put .ctors and .dtors next to the .got2 section, so that the pointers + get relocated with -mrelocatable. Also put in the .fixup pointers. + The current compiler no longer needs this, but keep it around for 2.7.2 */ + PROVIDE (_GOT2_START_ = .); + .got2 : { *(.got2) } >RAM + PROVIDE (__GOT2_END__ = .); + PROVIDE (__CTOR_LIST__ = .); + .ctors : { *(.ctors) } >RAM + PROVIDE (__CTOR_END__ = .); + PROVIDE (__DTOR_LIST__ = .); + .dtors : { *(.dtors) } >RAM + PROVIDE (__DTOR_END__ = .); + PROVIDE (_FIXUP_START_ = .); + .fixup : { *(.fixup) } >RAM + PROVIDE (_FIXUP_END_ = .); + PROVIDE (__FIXUP_END__ = .); + PROVIDE (_GOT2_END_ = .); + PROVIDE (_GOT_START_ = .); + s.got = .; + .got : { *(.got) } >RAM + .got.plt : { *(.got.plt) } >RAM + PROVIDE (_GOT_END_ = .); + PROVIDE (__GOT_END__ = .); + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + PROVIDE (__SDATA_START__ = .); + .sdata : { *(.sdata) } >RAM + _edata = .; + PROVIDE (edata = .); + PROVIDE (RAM_END = 10M); + . = ALIGN(8) + 0x1000; + PROVIDE (__SBSS_START__ = .); + .sbss : + { + PROVIDE (__sbss_start = .); + *(.sbss) + *(.scommon) + PROVIDE (__sbss_end = .); + } >RAM + PROVIDE (__SBSS_END__ = .); + .bss : + { + PROVIDE (__bss_start = .); + *(.dynbss) + *(.bss) + *(COMMON) + } >RAM + . = ALIGN(8) + 0x8000; + PROVIDE (__stack = .); + _end = . ; + PROVIDE (end = .); + + /* These are needed for ELF backends which have not yet been + converted to the new style linker. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* These must appear regardless of . */ +} diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c b/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c new file mode 100644 index 0000000000..83d9c45715 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c @@ -0,0 +1,73 @@ +/* set_vector + * + * This routine installs an interrupt vector on the target Board/CPU. + * This routine is allowed to be as board dependent as necessary. + * + * INPUT: + * handler - interrupt handler entry point + * vector - vector number + * type - 0 indicates raw hardware connect + * 1 indicates RTEMS interrupt connect + * + * RETURNS: + * address of previous interrupt handler + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/setvec.c: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#include <rtems.h> +#include <bsp.h> + + +/* + * This routine installs vector number vector. + * + */ +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +) +{ + rtems_isr_entry previous_isr; + rtems_status_code status; + + + /* + * vectors greater than PPC603e_IRQ_LAST are handled by the General purpose + * interupt handler. + */ + if ( vector > PPC_IRQ_LAST ) { + set_EE_vector( handler, vector ); + } + else { + status = rtems_interrupt_catch( + handler, vector, (rtems_isr_entry *) &previous_isr ); + } + return previous_isr; +} diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c b/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c new file mode 100644 index 0000000000..8bc11e41eb --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/spurious.c @@ -0,0 +1,259 @@ +/* + * Score603e Spurious Trap Handler + * + * This is just enough of a trap handler to let us know what + * the likely source of the trap was. + * + * Developed as part of the port of RTEMS to the ERC32 implementation + * of the SPARC by On-Line Applications Research Corporation (OAR) + * under contract to the European Space Agency (ESA). + * + * COPYRIGHT (c) 1995. European Space Agency. + * + * This terms of the RTEMS license apply to this file. + * + * $Id$ + */ + +#include <bsp.h> + +#include <string.h> + +static const char digits[16] = "0123456789abcdef"; + +rtems_isr bsp_stub_handler( + rtems_vector_number trap +) +{ +} + +/* + * bsp_spurious_handler + * + * Print a message on the debug console and then die + */ +rtems_isr bsp_spurious_handler( + rtems_vector_number trap +) +{ + + switch ( trap ) { + case PPC_IRQ_SYSTEM_RESET: + DEBUG_puts( "\nTrap: System reset" ); + break; + case PPC_IRQ_MCHECK: + DEBUG_puts( "\nTrap: Machine check" ); + break; + case PPC_IRQ_PROTECT: + DEBUG_puts( "\nTrap: DSI" ); + break; + case PPC_IRQ_ISI: + DEBUG_puts( "ISI" ); + break; + case PPC_IRQ_EXTERNAL: + DEBUG_puts( "\nTrap: External interupt" ); + break; + case PPC_IRQ_ALIGNMENT: + DEBUG_puts( "\nTrap: Alignment Exception" ); + break; + case PPC_IRQ_PROGRAM: + DEBUG_puts( "\nTrap: Program" ); + break; + case PPC_IRQ_NOFP: + DEBUG_puts( "\nTrap: Floating point unavailable" ); + break; + case PPC_IRQ_DECREMENTER: + DEBUG_puts( "\nTrap: Decrementer" ); + break; + case PPC_IRQ_RESERVED_A: + DEBUG_puts( "\nTrap: Reserved 0x00a00" ); + break; + case PPC_IRQ_RESERVED_B: + DEBUG_puts( "\nTrap: Reserved 0x00b00" ); + break; + case PPC_IRQ_SCALL: + DEBUG_puts( "\nTrap: System call" ); + break; + case PPC_IRQ_TRACE: + DEBUG_puts( "\nTrap: Trace" ); + break; + case PPC_IRQ_FP_ASST: + DEBUG_puts( "\nTrap: Floating point Assist" ); + break; + +#if defined(ppc403) +#error "Please fill in names. " + case PPC_IRQ_CRIT : + DEBUG_puts( "\nTrap: Critical Error "); + break; + case PPC_IRQ_PIT: + DEBUG_puts( "\nTrap: 0x01000" ); + break; + case PPC_IRQ_FIT: + DEBUG_puts( "\nTrap: 0x01010" ); + break; + case PPC_IRQ_WATCHDOG : + DEBUG_puts( "\nTrap: 0x01020" ); + break; + case PPC_IRQ_DEBUG : + DEBUG_puts( "\nTrap: 0x02000" ); + break; + +#elif defined(ppc601) +#error "Please fill in names. " + case PPC_IRQ_TRACE : + DEBUG_puts( "\nTrap: 0x02000" ); + break; + +#elif defined(ppc603) +#error "Please fill in names. " + case PPC_IRQ_TRANS_MISS : + DEBUG_puts( "\nTrap: 0x1000" ); + break; + case PPC_IRQ_DATA_LOAD: + DEBUG_puts( "\nTrap: 0x1100" ); + break; + case PPC_IRQ_DATA_STORE: + DEBUG_puts( "\nTrap: 0x1200" ); + break; + case PPC_IRQ_ADDR_BRK: + DEBUG_puts( "\nTrap: 0x1300" ); + break; + case PPC_IRQ_SYS_MGT: + DEBUG_puts( "\nTrap: 0x1400" ); + break; + +#elif defined(ppc603e) + case PPC_TLB_INST_MISS: + DEBUG_puts( "\nTrap: Instruction Translation Miss" ); + break; + case PPC_TLB_LOAD_MISS: + DEBUG_puts( "\nTrap: Data Load Translation Miss" ); + break; + case PPC_TLB_STORE_MISS : + DEBUG_puts( "\nTrap: Data store Translation Miss"); + break; + case PPC_IRQ_ADDRBRK: + DEBUG_puts( "\nTrap: Instruction address break point" ); + break; + case PPC_IRQ_SYS_MGT: + DEBUG_puts( "\nTrap: System management interrupt" ); + break; + +#elif defined(ppc604) +#error "Please fill in names. " + case PPC_IRQ_ADDR_BRK: + DEBUG_puts( "0x1300" ); + break; + case PPC_IRQ_SYS_MGT: + DEBUG_puts( "0x1400" ); + break; +#endif + + default: + DEBUG_puts( "\nTrap: Undefined exception " ); + break; + } + + /* + * What else can we do but stop ... + */ + /* + asm volatile( "" ); + */ + while (1); +} + +/* + * bsp_spurious_initialize + * + * Install the spurious handler for most traps. + */ + +void bsp_spurious_initialize() +{ + rtems_unsigned32 trap; + + for ( trap=0 ; trap < PPC_IRQ_LAST ; trap++ ) { + if (trap == PPC_IRQ_DECREMENTER) + ; + /* set_vector( bsp_stub_handler, trap, 1 ); */ + else + set_vector( bsp_spurious_handler, trap, 1 ); + } +} + +void bsp_set_trap_vectors( void ) +{ + volatile rtems_unsigned32 *ptr; + + /* reset_vector */ + ptr = (rtems_unsigned32 *)0x00100 ; + *ptr = 0x48000000; + + /* org mach_vector */ + ptr = (rtems_unsigned32 *)0x00200; + *ptr = 0x48000000; + + /* org prot_vector */ + ptr = (rtems_unsigned32 *)0x00300; + *ptr = 0x48000000; + + /* org isi_vector */ + ptr = (rtems_unsigned32 *)0x00400; + *ptr = 0x48000000; + + /* org ext_vector */ + ptr = (rtems_unsigned32 *)0x0500 ; + *ptr = 0x48000000; + + /* org align_vector */ + ptr = (rtems_unsigned32 *)0x00600 ; + *ptr = 0x48000000; + + /* org prog_vector */ + ptr = (rtems_unsigned32 *)0x00700 ; + *ptr = 0x48000000; + + /* org float_vector */ + ptr = (rtems_unsigned32 *)0x00800; + *ptr = 0x48000000; + + /* org dec_vector - rfi */ + ptr = (rtems_unsigned32 *)0x900; + *ptr = 0x4c000064; + + /* org sys_vector */ + ptr = (rtems_unsigned32 *)0x0c00 ; + *ptr = 0x48000000; + + /* org trace_vector */ + ptr = (rtems_unsigned32 *)0x0d00 ; + *ptr = 0x48000000; + + /* org itm_vector */ + ptr = (rtems_unsigned32 *)0x01000 ; + *ptr = 0x48000000; + + /* org dltm_vector */ + ptr = (rtems_unsigned32 *)0x01100 ; + *ptr = 0x48000000; + + /* org dstm_vector */ + ptr = (rtems_unsigned32 *)0x1200 ; + *ptr = 0x48000000; + + /* org addr_vector */ + ptr = (rtems_unsigned32 *)0x1300 ; + *ptr = 0x48000000; + + /* org sysmgmt_vector */ + ptr = (rtems_unsigned32 *)0x1400 ; + *ptr = 0x48000000; + +} + + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c new file mode 100644 index 0000000000..270d64672d --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c @@ -0,0 +1,70 @@ +/* vmeintr.c + * + * VMEbus support routines for the Generation I board. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#include <rtems.h> +#include <bsp.h> +#include <vmeintr.h> + +/*PAGE + * + * VME_interrupt_Disable + * + */ + +void VME_interrupt_Disable ( + VME_interrupt_Mask mask /* IN */ +) +{ + volatile rtems_unsigned8 *VME_interrupt_enable; + rtems_unsigned8 value; + +#if 0 + VME_interrupt_enable = ACC_VIE; +#else + VME_interrupt_enable = 0; +#endif + value = *VME_interrupt_enable; + + value &= ~mask; /* turn off interrupts for all levels in mask */ + + *VME_interrupt_enable = value; +} + +/*PAGE + * + * VME_interrupt_Enable + * + */ + +void VME_interrupt_Enable ( + VME_interrupt_Mask mask /* IN */ +) +{ + volatile rtems_unsigned8 *VME_interrupt_enable; + rtems_unsigned8 value; + +#if 0 + VME_interrupt_enable = ACC_VIE; +#else + VME_interrupt_enable = 0; +#endif + value = *VME_interrupt_enable; + + value |= mask; /* turn on interrupts for all levels in mask */ + + *VME_interrupt_enable = value; +} + + diff --git a/c/src/lib/libbsp/powerpc/score603e/timer/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/timer/Makefile.in new file mode 100644 index 0000000000..4c6affa027 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/timer/Makefile.in @@ -0,0 +1,61 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +PGM=${ARCH}/timer.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=timer +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/score603e/timer/timer.c b/c/src/lib/libbsp/powerpc/score603e/timer/timer.c new file mode 100644 index 0000000000..3623ac07d1 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/timer/timer.c @@ -0,0 +1,84 @@ +/* timer.c + * + * This file implements a benchmark timer using the General Purpose Timer. + * + * Notes: + * + * BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID are required to be + * provided in bsp.h + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <assert.h> + +#include <bsp.h> + +rtems_unsigned64 Timer_driver_Start_time; + +rtems_boolean Timer_driver_Find_average_overhead; + +/* + * Timer_initialize + */ + +void Timer_initialize() +{ + + /* + * Timer runs long and accurate enough not to require an interrupt. + */ + + Timer_driver_Start_time = PPC_Get_timebase_register(); +} + +/* + * Read_timer + */ + +int Read_timer() +{ + rtems_unsigned64 clicks; + rtems_unsigned64 total64; + rtems_unsigned32 total; + + /* approximately CLOCK_SPEED clicks per microsecond */ + + clicks = PPC_Get_timebase_register(); + + assert( clicks > Timer_driver_Start_time ); + + total64 = clicks - Timer_driver_Start_time; + + assert( total64 <= 0xffffffff ); /* fits into a unsigned32 */ + + total = (rtems_unsigned32) total64; + + if ( Timer_driver_Find_average_overhead == 1 ) + return total; /* in "clicks" of the decrementer units */ + + if ( total < BSP_TIMER_LEAST_VALID ) + return 0; /* below timer resolution */ + + return BSP_Convert_decrementer(total - BSP_TIMER_AVG_OVERHEAD); +} + +rtems_status_code Empty_function( void ) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead( + rtems_boolean find_flag +) +{ + Timer_driver_Find_average_overhead = find_flag; +} diff --git a/c/src/lib/libbsp/powerpc/score603e/tod/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/tod/Makefile.in new file mode 100644 index 0000000000..20b401dc25 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/tod/Makefile.in @@ -0,0 +1,65 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +PGM=${ARCH}/tod.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=$(TOD_PIECES) +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +SRCS=$(C_FILES) $(H_FILES) +OBJS=$(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# First and second generation use different RTC chips :( +ifeq ($(SCORE603E_GENERATION),1) +TOD_PIECES=tod_g1 +else +ifeq ($(SCORE603E_GENERATION),2) +TOD_PIECES=tod +endif # generation 2 +endif # generation 1 + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/score603e/tod/tod.c b/c/src/lib/libbsp/powerpc/score603e/tod/tod.c new file mode 100644 index 0000000000..e6333e8b6f --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/tod/tod.c @@ -0,0 +1,180 @@ +/* + * Real Time Clock (Harris ICM7170) for RTEMS + * + * This part is found on the second generation of this board. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <rtems.h> +#include <tod.h> +#include <bsp.h> + +/* + * These values are programed into a register and must not be changed. + */ + +#define ICM1770_CRYSTAL_FREQ_32K 0x00 +#define ICM1770_CRYSTAL_FREQ_1M 0x01 +#define ICM1770_CRYSTAL_FREQ_2M 0x02 +#define ICM1770_CRYSTAL_FREQ_4M 0x03 + +void ICM7170_GetTOD( + volatile unsigned char *imc1770_regs, + rtems_unsigned8 icm1770_freq, + rtems_time_of_day *rtc_tod +); +void ICM7170_SetTOD( + volatile unsigned char *imc1770_regs, + rtems_unsigned8 icm1770_freq, + rtems_time_of_day *rtc_tod +); + +/* + * This code is dependent on the Vista 603e's use of the ICM7170 RTC/NVRAM + * and should remain in this file. + */ + +void setRealTimeToRTEMS() +{ + rtems_time_of_day rtc_tod; + + ICM7170_GetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtc_tod ); + rtems_clock_set( &rtc_tod ); +} + +void setRealTimeFromRTEMS() +{ + rtems_time_of_day rtems_tod; + + rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod ); + ICM7170_SetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtems_tod ); +} + +int checkRealTime() +{ + rtems_time_of_day rtems_tod; + rtems_time_of_day rtc_tod; + + ICM7170_GetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtc_tod ); + rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod ); + + if( rtems_tod.year == rtc_tod.year && + rtems_tod.month == rtc_tod.month && + rtems_tod.day == rtc_tod.day ) { + return ((rtems_tod.hour - rtc_tod.hour) * 3600) + + ((rtems_tod.minute - rtc_tod.minute) * 60) + + (rtems_tod.second - rtc_tod.second); + } + return 9999; +} + +/* + * These routines are ICM7170 should be in + * a separate support library. + * XXX Make static + */ +static int ICM7170_GetField( + volatile unsigned char *imc1770_regs, + int reg +) +{ + unsigned char x; + + x = imc1770_regs[reg*4]; + + return x; +} + +static void ICM7170_SetField( + volatile unsigned char *imc1770_regs, + int reg, + unsigned char d +) +{ + imc1770_regs[reg*4] = d; +} + +void ICM7170_GetTOD( + volatile unsigned char *imc1770_regs, + rtems_unsigned8 icm1770_freq, + rtems_time_of_day *rtc_tod +) +{ + int year; + int usec; + static rtems_boolean init = TRUE; + + /* Initialize the clock at once prior to reading */ + if (init ) { + ICM7170_SetField( imc1770_regs, 0x11, (0x0c | icm1770_freq) ); + init = FALSE; + } + + /* Latch times */ + /* rtc_tod->ticks = */ + + usec = ICM7170_GetField( imc1770_regs, 0x00 ); + + year = ICM7170_GetField( imc1770_regs, 0x06 ); + if ( year >= 88 ) + year += 1900; + else + year += 2000; + + rtc_tod->year = year; + rtc_tod->month = ICM7170_GetField( imc1770_regs, 0x04 ); + rtc_tod->day = ICM7170_GetField( imc1770_regs, 0x05 ); + rtc_tod->hour = ICM7170_GetField( imc1770_regs, 0x01 ); + rtc_tod->minute = ICM7170_GetField( imc1770_regs, 0x02 ); + rtc_tod->second = ICM7170_GetField( imc1770_regs, 0x03 ); + rtc_tod->ticks = ICM7170_GetField( imc1770_regs, 0x00 ); +} + +void ICM7170_SetTOD( + volatile unsigned char *imc1770_regs, + rtems_unsigned8 icm1770_freq, + rtems_time_of_day *rtc_tod +) +{ + int ticks; + int year; + + year = rtc_tod->year; + if ( year >= 2088 ) /* plan ahead :) */ + rtems_fatal_error_occurred( 0xBAD0BAD0 ); + + if ( year >= 2000 ) + year -= 2000; + else + year -= 1900; + + ICM7170_SetField( imc1770_regs, 0x11, (0x04 |icm1770_freq ) ); + + ICM7170_SetField( imc1770_regs, 0x06, year ); + ICM7170_SetField( imc1770_regs, 0x04, rtc_tod->month ); + ICM7170_SetField( imc1770_regs, 0x05, rtc_tod->day ); + ICM7170_SetField( imc1770_regs, 0x01, rtc_tod->hour ); + ICM7170_SetField( imc1770_regs, 0x02, rtc_tod->minute ); + ICM7170_SetField( imc1770_regs, 0x03, rtc_tod->second ); + + /* + * I don't know which day of week is + * + */ + ICM7170_SetField( imc1770_regs, 0x07, 1 ); + + ICM7170_SetField( imc1770_regs, 0x11, (0x0c | icm1770_freq) ); +} + + + + + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/tod/tod_g1.c b/c/src/lib/libbsp/powerpc/score603e/tod/tod_g1.c new file mode 100644 index 0000000000..6366cf662a --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/tod/tod_g1.c @@ -0,0 +1,138 @@ +/* + * Real Time Clock (SGS-Thomson M48T08/M48T18) for RTEMS + * + * This part is only found on the first generation board. + * + * Based on MVME162 TOD Driver by: + * COPYRIGHT (C) 1997 + * by Katsutoshi Shibuya - BU Denken Co.,Ltd. - Sapporo - JAPAN + * ALL RIGHTS RESERVED + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <rtems.h> +#include <tod.h> +#include <bsp.h> + +/* + * These routines are M48T08 and M48T18 dependent and should be in + * a separate support library. + */ + +static int M48T08_GetField( + volatile unsigned char *mk48t08, + int n, + unsigned char mask +) +{ + unsigned char x; + + x = mk48t08[n] & mask; + return ((x >> 4) * 10) + (x & 0x0f); +} + +static void M48T08_SetField( + volatile unsigned char *mk48t08, + int n, + unsigned char d +) +{ + mk48t08[n] = ((d / 10) << 4) + (d % 10); +} + +static void M48T08_GetTOD( + volatile unsigned char *mk48t08, + rtems_time_of_day *rtc_tod +) +{ + int year; + + mk48t08[0] |= 0x40; /* Stop read register */ + + year = M48T08_GetField( mk48t08, 7, 0xff ); + if ( year >= 88 ) + year += 1900; + else + year += 2000; + + rtc_tod->year = year; + rtc_tod->month = M48T08_GetField( mk48t08, 6, 0x1f ); + rtc_tod->day = M48T08_GetField( mk48t08, 5, 0x3f ); + rtc_tod->hour = M48T08_GetField( mk48t08, 3, 0x3f ); + rtc_tod->minute = M48T08_GetField( mk48t08, 2, 0x7f ); + rtc_tod->second = M48T08_GetField( mk48t08, 1, 0x7f ); + rtc_tod->ticks = 0; + mk48t08[0] &= 0x3f; /* Release read register */ +} + +static void M48T08_SetTOD( + volatile unsigned char *mk48t08, + rtems_time_of_day *rtc_tod +) +{ + int year; + + year = rtc_tod->year; + + if ( year >= 2088 ) /* plan ahead :) */ + rtems_fatal_error_occurred( 0xBAD0BAD0 ); + + if ( year >= 2000 ) + year -= 2000; + else + year -= 1900; + + mk48t08[0] |= 0x80; /* Stop write register */ + M48T08_SetField( mk48t08, 7, year ); + M48T08_SetField( mk48t08, 6, rtc_tod->month ); + M48T08_SetField( mk48t08, 5, rtc_tod->day ); + M48T08_SetField( mk48t08, 4, 1 ); /* I don't know which day of week is */ + M48T08_SetField( mk48t08, 3, rtc_tod->hour ); + M48T08_SetField( mk48t08, 2, rtc_tod->minute ); + M48T08_SetField( mk48t08, 1, rtc_tod->second ); + mk48t08[0] &= 0x3f; /* Write these parameters */ +} + +/* + * This code is dependent on the Vista 603e's use of the M48T18 RTC/NVRAM + * and should remain in this file. + */ + +void setRealTimeToRTEMS() +{ + rtems_time_of_day rtc_tod; + + M48T08_GetTOD( SCORE603E_RTC_ADDRESS, &rtc_tod ); + rtems_clock_set( &rtc_tod ); +} + +void setRealTimeFromRTEMS() +{ + rtems_time_of_day rtems_tod; + + rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod ); + M48T08_SetTOD( SCORE603E_RTC_ADDRESS, &rtems_tod ); +} + +int checkRealTime() +{ + rtems_time_of_day rtems_tod; + rtems_time_of_day rtc_tod; + + M48T08_GetTOD( SCORE603E_RTC_ADDRESS, &rtc_tod ); + rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod ); + + if( rtems_tod.year == rtc_tod.year && + rtems_tod.month == rtc_tod.month && + rtems_tod.day == rtc_tod.day ) { + return ((rtems_tod.hour - rtc_tod.hour) * 3600) + + ((rtems_tod.minute - rtc_tod.minute) * 60) + + (rtems_tod.second - rtc_tod.second); + } + return 9999; +} diff --git a/c/src/lib/libbsp/powerpc/score603e/vectors/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/vectors/Makefile.in new file mode 100644 index 0000000000..b65178e44f --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/vectors/Makefile.in @@ -0,0 +1,61 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +PGM=${ARCH}/vectors.rel + +# C source names, if any, go here -- minus the .c +C_PIECES= +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .S +S_PIECES=vectors +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S b/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S new file mode 100644 index 0000000000..9a15dd1031 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/vectors/vectors.S @@ -0,0 +1,177 @@ +/* vectors.s 1.1 - 95/12/04 + * + * This file contains the assembly code for the PowerPC + * interrupt veneers for RTEMS. + * + */ + +/* + * The issue with this file is getting it loaded at the right place. + * The first vector MUST be at address 0x????0100. + * How this is achieved is dependant on the tool chain. + * + * However the basic mechanism for ELF assemblers is to create a + * section called ".vectors", which will be loaded to an address + * between 0x????0000 and 0x????0100 (inclusive) via a link script. + * + * The basic mechanism for XCOFF assemblers is to place it in the + * normal text section, and arrange for this file to be located + * at an appropriate position on the linker command line. + * + * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the + * offset from 0x????0000 to the first location in the file. This + * will usually be 0x0000 or 0x0100. + * + * $Id$ + */ + +#include "asm.h" + +#ifndef PPC_VECTOR_FILE_BASE +#error "PPC_VECTOR_FILE_BASE is not defined." +#endif + +#if (SCORE603E_USE_NONE) + + /* Where this file will be loaded */ + .set file_base, PPC_VECTOR_FILE_BASE + + /* Vector offsets */ + .set reset_vector,0x0100 + .set mach_vector,0x0200 + .set prot_vector,0x0300 + .set isi_vector,0x0400 + .set ext_vector,0x0500 + .set align_vector,0x0600 + .set prog_vector,0x0700 + .set float_vector,0x0800 + .set dec_vector,0x0900 + .set sys_vector,0x00C00 + .set trace_vector, 0x0d00 + .set itm_vector,0x01000 + .set dltm_vector,0x1100 + .set dstm_vector,0x1200 + .set addr_vector,0x1300 + .set sysmgmt_vector,0x1400 + +/* Go to the right section */ +#if PPC_ASM == PPC_ASM_ELF + .section .vectors,"awx",@progbits +#elif PPC_ASM == PPC_ASM_XCOFF + .csect .text[PR] +#endif + + PUBLIC_VAR (__vectors) +SYM (__vectors): + + /* Decrementer interrupt */ + .org reset_vector - file_base + ba 0x00100 + ba 0xfff00100 + ba 0xfff00100 + ba 0xfff00100 + + .org mach_vector - file_base + ba 0x00200 + ba 0xfff00200 + ba 0xfff00200 + ba 0xfff00200 + + .org prot_vector - file_base + ba 0x00300 + ba 0xfff00300 + ba 0xfff00300 + ba 0xfff00300 + + .org isi_vector - file_base + ba 0x00400 + ba 0xfff00400 + ba 0xfff00400 + ba 0xfff00400 + + .org ext_vector - file_base + ba 0x0500 + ba 0xfff00500 + ba 0xfff00500 + ba 0xfff00500 + + .org align_vector - file_base + ba 0x00600 + ba 0xfff00600 + ba 0xfff00600 + ba 0xfff00600 + + .org prog_vector - file_base + ba 0x00700 + ba 0xfff00700 + ba 0xfff00700 + ba 0xfff00700 + + .org float_vector - file_base + ba 0x00800 + ba 0xfff00800 + ba 0xfff00800 + ba 0xfff00800 + + .org dec_vector - file_base + rfi + ba 0xfff00900 + ba 0xfff00900 + ba 0xfff00900 + + .org sys_vector - file_base + ba 0x0c00 + ba 0xfff00C00 + ba 0xfff00C00 + ba 0xfff00C00 + + .org trace_vector - file_base + ba 0x0d00 + ba 0xfff00d00 + ba 0xfff00d00 + ba 0xfff00d00 + + .org itm_vector - file_base + ba 0x01000 + ba 0xfff01000 + ba 0xfff01000 + ba 0xfff01000 + + .org dltm_vector - file_base + ba 0x01100 + ba 0xfff01100 + ba 0xfff01100 + ba 0xfff01100 + + .org dstm_vector - file_base + ba 0x1200 + ba 0xfff01200 + ba 0xfff01200 + ba 0xfff01200 + + .org addr_vector - file_base + ba 0x1300 + ba 0xfff01300 + ba 0xfff01300 + ba 0xfff01300 + + .org sysmgmt_vector - file_base + ba 0x1400 + ba 0xfff01400 + ba 0xfff01400 + ba 0xfff01400 +#endif + + + + + + + + + + + + + + diff --git a/c/src/lib/libbsp/powerpc/score603e/wrapup/Makefile.in b/c/src/lib/libbsp/powerpc/score603e/wrapup/Makefile.in new file mode 100644 index 0000000000..38a2776074 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/score603e/wrapup/Makefile.in @@ -0,0 +1,56 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +INSTALL = @INSTALL@ + +BSP_PIECES=startup clock console timer tod vectors PCI_bus +# pieces to pick up out of libcpu/$(RTEMS_CPU) +CPU_PIECES= +GENERIC_PIECES= + +# bummer; have to use $foreach since % pattern subst rules only replace 1x +OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ + $(foreach piece, $(CPU_PIECES), \ + ../../../../libcpu/$(RTEMS_CPU)/$(piece)/$(ARCH)/$(piece).rel) \ + $(foreach piece, $(GENERIC_PIECES), \ + ../../../$(piece)/$(ARCH)/$(piece).rel) +LIB=$(ARCH)/libbsp.a + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +$(LIB): ${OBJS} + $(make-library) + +all: ${ARCH} $(SRCS) $(LIB) + $(INSTALL_VARIANT) -m 644 $(LIB) ${PROJECT_RELEASE}/lib + |