diff options
Diffstat (limited to 'c/src/lib/libbsp/m68k/mcf5206elite/startup/init5206e.c')
| -rw-r--r-- | c/src/lib/libbsp/m68k/mcf5206elite/startup/init5206e.c | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/startup/init5206e.c b/c/src/lib/libbsp/m68k/mcf5206elite/startup/init5206e.c index 8bf94caaad..64be2e5354 100644 --- a/c/src/lib/libbsp/m68k/mcf5206elite/startup/init5206e.c +++ b/c/src/lib/libbsp/m68k/mcf5206elite/startup/init5206e.c @@ -24,7 +24,7 @@ * found in the file LICENSE in this distribution or at * * http://www.rtems.com/license/LICENSE. - * + * * $Id$ */ @@ -82,19 +82,19 @@ void Init5206e(void) { extern void CopyDataClearBSSAndStart(unsigned long ramsize); - + /* Set Module Base Address register */ m68k_set_mbar((MBAR & MCF5206E_MBAR_BA) | MCF5206E_MBAR_V); - + /* Set System Protection Control Register (SYPCR): * Bus Monitor Enable, Bus Monitor Timing = 1024 clocks, * Software watchdog disabled */ *MCF5206E_SYPCR(MBAR) = MCF5206E_SYPCR_BME | MCF5206E_SYPCR_BMT_1024; - + /* Set Pin Assignment Register (PAR): - * Output Timer 0 (not DREQ) on *TOUT[0] / *DREQ[1] + * Output Timer 0 (not DREQ) on *TOUT[0] / *DREQ[1] * Input Timer 0 (not DREQ) on *TIN[0] / *DREQ[0] * IRQ, not IPL * UART2 RTS signal (not \RSTO) @@ -108,7 +108,7 @@ Init5206e(void) MCF5206E_PAR_PAR5_PST | MCF5206E_PAR_PAR4_DDATA | MCF5206E_PAR_WE0_WE1_WE2_WE3; - + /* Set SIM Configuration Register (SIMR): * Disable software watchdog timer and bus timeout monitor when * internal freeze signal is asserted. @@ -117,45 +117,45 @@ Init5206e(void) /* Set Interrupt Mask Register: Disable all interrupts */ *MCF5206E_IMR(MBAR) = 0xFFFF; - + /* Assign Interrupt Control Registers as it is defined in bsp.h */ - *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL1) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL1) = (BSP_INTLVL_AVEC1 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_AVEC1 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL2) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL2) = (BSP_INTLVL_AVEC2 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_AVEC2 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL3) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL3) = (BSP_INTLVL_AVEC3 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_AVEC3 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL4) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL4) = (BSP_INTLVL_AVEC4 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_AVEC4 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL5) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL5) = (BSP_INTLVL_AVEC5 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_AVEC5 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL6) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL6) = (BSP_INTLVL_AVEC6 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_AVEC6 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL7) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL7) = (BSP_INTLVL_AVEC7 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_AVEC7 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_1) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_1) = (BSP_INTLVL_TIMER1 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_TIMER1 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_2) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_2) = (BSP_INTLVL_TIMER2 << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_TIMER2 << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; - *MCF5206E_ICR(MBAR,MCF5206E_INTR_MBUS) = + *MCF5206E_ICR(MBAR,MCF5206E_INTR_MBUS) = (BSP_INTLVL_MBUS << MCF5206E_ICR_IL_S) | (BSP_INTPRIO_MBUS << MCF5206E_ICR_IP_S) | MCF5206E_ICR_AVEC; @@ -178,7 +178,7 @@ Init5206e(void) *MCF5206E_SWIVR(MBAR) = 0x0F; /* Uninitialized interrupt */ *MCF5206E_SWSR(MBAR) = MCF5206E_SWSR_KEY1; *MCF5206E_SWSR(MBAR) = MCF5206E_SWSR_KEY2; - + /* Configuring Chip Selects */ /* CS2: SRAM memory */ *MCF5206E_CSAR(MBAR,2) = BSP_MEM_ADDR_ESRAM >> 16; @@ -189,7 +189,7 @@ Init5206e(void) MCF5206E_CSCR_EMAA | MCF5206E_CSCR_WR | MCF5206E_CSCR_RD; - + /* CS3: GPIO on eLITE board */ *MCF5206E_CSAR(MBAR,3) = BSP_MEM_ADDR_GPIO >> 16; *MCF5206E_CSMR(MBAR,3) = BSP_MEM_MASK_GPIO; @@ -199,7 +199,7 @@ Init5206e(void) MCF5206E_CSCR_EMAA | MCF5206E_CSCR_WR | MCF5206E_CSCR_RD; - + { extern void INTERRUPT_VECTOR(); uint32_t *inttab = (uint32_t*)&INTERRUPT_VECTOR; @@ -211,9 +211,9 @@ Init5206e(void) } } m68k_set_vbr(BSP_MEM_ADDR_ESRAM); - + /* CS0: Flash EEPROM */ - *MCF5206E_CSAR(MBAR,0) = BSP_MEM_ADDR_FLASH >> 16; + *MCF5206E_CSAR(MBAR,0) = BSP_MEM_ADDR_FLASH >> 16; *MCF5206E_CSCR(MBAR,0) = MCF5206E_CSCR_WS3 | MCF5206E_CSCR_AA | MCF5206E_CSCR_PS_16 | @@ -221,7 +221,7 @@ Init5206e(void) MCF5206E_CSCR_WR | MCF5206E_CSCR_RD; *MCF5206E_CSMR(MBAR,0) = BSP_MEM_MASK_FLASH; - + /* * Invalidate the cache and disable it */ @@ -244,8 +244,8 @@ Init5206e(void) | MCF5206E_ACR_SM_ANY ); - mcf5206e_enable_cache(); - + mcf5206e_enable_cache(); + /* * Copy data, clear BSS, switch stacks and call boot_card() */ |