diff options
Diffstat (limited to 'c/src/lib/libbsp/i960')
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/clock/ckinit.c | 77 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/console/console.c | 147 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/include/bsp.h | 129 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/include/coverhd.h | 104 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/shmsupp/addrconv.c | 37 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/shmsupp/getcfg.c | 98 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/shmsupp/lock.c | 77 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/shmsupp/mpisr.c | 70 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/startup/bspclean.c | 32 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/startup/bspstart.c | 163 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/startup/exit.c | 38 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/startup/linkcmds | 48 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/startup/setvec.c | 145 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/timer/timer.c | 107 | ||||
| -rw-r--r-- | c/src/lib/libbsp/i960/cvme961/timer/timerisr.s | 59 |
15 files changed, 1331 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/i960/cvme961/clock/ckinit.c b/c/src/lib/libbsp/i960/cvme961/clock/ckinit.c new file mode 100644 index 0000000000..315e02cdbb --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/clock/ckinit.c @@ -0,0 +1,77 @@ +/* Clock_init() + * + * This routine initializes the timer on the VIC chip on the CVME961. + * The tick frequency is 1 millisecond. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <stdlib.h> + +#include <rtems.h> +#include <bsp.h> +#include <clockdrv.h> + +rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ +i960_isr Old_ticker; +volatile rtems_unsigned32 Clock_driver_ticks; + /* ticks since initialization */ + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp, + rtems_id id, + rtems_unsigned32 *rval ) +{ + Install_clock( Clock_isr ); + atexit( Clock_exit ); +} + +void ReInstall_clock( + rtems_isr_entry clock_isr +) +{ + (void) set_vector( clock_isr, 5, 1 ); +} + +void Install_clock( + rtems_isr_entry clock_isr +) +{ + volatile unsigned char *victimer; + + Clock_driver_ticks = 0; + Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; + + if ( BSP_Configuration.ticks_per_timeslice ) { + Old_ticker = set_vector( clock_isr, 5, 1 ); + victimer = (volatile unsigned char *) 0xa00000c3; + *victimer = 0x12; + *victimer = 0x92; /* 1000 HZ */ + } +} + +void Clock_exit() +{ + unsigned char *victimer; + + if ( BSP_Configuration.ticks_per_timeslice ) { + victimer = (unsigned char *) 0xa00000c3; + *victimer = 0x12; + i960_mask_intr( 5 ); + /* do not restore old vector */ + } +} diff --git a/c/src/lib/libbsp/i960/cvme961/console/console.c b/c/src/lib/libbsp/i960/cvme961/console/console.c new file mode 100644 index 0000000000..8ba0352304 --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/console/console.c @@ -0,0 +1,147 @@ +/* + * This file contains the MVME136 console IO package. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#define C961_INIT + +#include <rtems.h> +#include "console.h" +#include "bsp.h" + +/* console_initialize + * + * This routine initializes the console IO driver. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg, + rtems_id self, + rtems_unsigned32 *status +) +{ + *status = RTEMS_SUCCESSFUL; +} + +/* + * NINDY_IO( ... ) + * + * Interface to NINDY. + */ + +#define NINDY_INPUT 0 +#define NINDY_OUTPUT 1 + +void NINDY_IO(); + +void ___NINDY_IO_WRAPPER( void ) /* never called */ +{ + asm volatile ( " .text" ); + asm volatile ( " .align 4" ); + asm volatile ( " .globl _NINDY_IO" ); + asm volatile ( "_NINDY_IO:" ); + asm volatile ( " calls 0 /* call console routines */" ); + asm volatile ( " ret" ); +} + +/* inbyte + * + * This routine reads a character from the console using NINDY. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + * character read from UART + */ + +char inbyte( void ) +{ + char ch; + + NINDY_IO( NINDY_INPUT, &ch ); + return ch; +} + + +/* outbyte + * + * This routine transmits a character out the console using NINDY. + * + * Input parameters: + * ch - character to be transmitted + * + * Output parameters: NONE + */ + +void outbyte( + char ch +) +{ + NINDY_IO( NINDY_OUTPUT, ch ); +} + +/* + * __read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ + +int __read( + int fd, + char *buf, + int nbytes +) +{ + int i = 0; + + for (i = 0; i < nbytes; i++) { + *(buf + i) = inbyte(); + if ((*(buf + i) == '\n') || (*(buf + i) == '\r')) { + (*(buf + i++)) = '\n'; + (*(buf + i)) = 0; + break; + } + } + return (i); +} + +/* + * __write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ + +int __write( + int fd, + char *buf, + int nbytes +) +{ + int i; + + for (i = 0; i < nbytes; i++) { + if (*(buf + i) == '\n') { + outbyte ('\r'); + } + outbyte (*(buf + i)); + } + return (nbytes); +} diff --git a/c/src/lib/libbsp/i960/cvme961/include/bsp.h b/c/src/lib/libbsp/i960/cvme961/include/bsp.h new file mode 100644 index 0000000000..4dd907449f --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/include/bsp.h @@ -0,0 +1,129 @@ +/* bsp.h + * + * This include file contains some definitions specific to the + * Cyclone CVME960 and CVME961 boards. These boards are the + * same except the 960 uses SRAM and the 961 DRAM. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#ifndef __CVME961_h +#define __CVME961_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems.h> +#include <iosupp.h> + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Define the interrupt mechanism for Time Test 27 + * + * NOTE: Following are for i960CA and are board independent + * + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 6, 1 ) + +#define Cause_tm27_intr() i960_cause_intr( 0x62 ) + +#define Clear_tm27_intr() i960_clear_intr( 6 ) + +#define Lower_tm27_intr() + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define delay( microseconds ) \ + { register rtems_unsigned32 _delay=(microseconds); \ + register rtems_unsigned32 _tmp; \ + asm volatile( "0: \ + remo 3,31,%0 ; \ + cmpo 0,%0 ; \ + subo 1,%1,%1 ; \ + cmpobne.t 0,%1,0b " \ + : "=d" (_tmp), "=d" (_delay) \ + : "0" (_tmp), "1" (_delay) ); \ + } + +/* Constants */ + +#define RAM_START 0 +#define RAM_END 0x100000 + +/* NINDY console I/O requests: + * CO sends a single character to stdout, + * CI reads one. + */ + +#define NINDY_INPUT 0 +#define NINDY_OUTPUT 1 + +/* + * get_prcb + * + * Returns the PRCB pointer. + */ + +static inline i960ca_PRCB *get_prcb( void ) +{ + register i960ca_PRCB *_prcb = 0; + + asm volatile( "calls 5; \ + mov g0,%0" \ + : "=d" (_prcb) \ + : "0" (_prcb) ); + return ( _prcb ); +} + +#ifdef C961_INIT +#undef BSP_EXTERN +#define BSP_EXTERN +#else +#undef BSP_EXTERN +#define BSP_EXTERN extern +#endif + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +BSP_EXTERN i960ca_PRCB *Prcb; +BSP_EXTERN i960ca_control_table *Ctl_tbl; + +/* functions */ + +void bsp_cleanup( void ); + +i960_isr set_vector( rtems_isr_entry, unsigned int, unsigned int ); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/i960/cvme961/include/coverhd.h b/c/src/lib/libbsp/i960/cvme961/include/coverhd.h new file mode 100644 index 0000000000..9d6b26111a --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/include/coverhd.h @@ -0,0 +1,104 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C on this target. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 +#define CALLING_OVERHEAD_TASK_CREATE 0 +#define CALLING_OVERHEAD_TASK_IDENT 0 +#define CALLING_OVERHEAD_TASK_START 0 +#define CALLING_OVERHEAD_TASK_RESTART 0 +#define CALLING_OVERHEAD_TASK_DELETE 0 +#define CALLING_OVERHEAD_TASK_SUSPEND 0 +#define CALLING_OVERHEAD_TASK_RESUME 0 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 +#define CALLING_OVERHEAD_TASK_MODE 0 +#define CALLING_OVERHEAD_TASK_GET_NOTE 0 +#define CALLING_OVERHEAD_TASK_SET_NOTE 0 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 3 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 +#define CALLING_OVERHEAD_CLOCK_GET 3 +#define CALLING_OVERHEAD_CLOCK_SET 3 +#define CALLING_OVERHEAD_CLOCK_TICK 0 + +#define CALLING_OVERHEAD_TIMER_CREATE 0 +#define CALLING_OVERHEAD_TIMER_IDENT 0 +#define CALLING_OVERHEAD_TIMER_DELETE 0 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 6 +#define CALLING_OVERHEAD_TIMER_RESET 0 +#define CALLING_OVERHEAD_TIMER_CANCEL 0 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 + +#define CALLING_OVERHEAD_EVENT_SEND 0 +#define CALLING_OVERHEAD_EVENT_RECEIVE 0 +#define CALLING_OVERHEAD_SIGNAL_CATCH 0 +#define CALLING_OVERHEAD_SIGNAL_SEND 0 +#define CALLING_OVERHEAD_PARTITION_CREATE 0 +#define CALLING_OVERHEAD_PARTITION_IDENT 0 +#define CALLING_OVERHEAD_PARTITION_DELETE 0 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 +#define CALLING_OVERHEAD_REGION_CREATE 0 +#define CALLING_OVERHEAD_REGION_IDENT 0 +#define CALLING_OVERHEAD_REGION_DELETE 0 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 +#define CALLING_OVERHEAD_PORT_CREATE 0 +#define CALLING_OVERHEAD_PORT_IDENT 0 +#define CALLING_OVERHEAD_PORT_DELETE 0 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 + +#define CALLING_OVERHEAD_IO_INITIALIZE 0 +#define CALLING_OVERHEAD_IO_OPEN 0 +#define CALLING_OVERHEAD_IO_CLOSE 0 +#define CALLING_OVERHEAD_IO_READ 0 +#define CALLING_OVERHEAD_IO_WRITE 0 +#define CALLING_OVERHEAD_IO_CONTROL 0 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/i960/cvme961/shmsupp/addrconv.c b/c/src/lib/libbsp/i960/cvme961/shmsupp/addrconv.c new file mode 100644 index 0000000000..7702d22e67 --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/shmsupp/addrconv.c @@ -0,0 +1,37 @@ +/* Shm_Convert_address + * + * This routine takes into account the peculiar short VME address + * of the CVME961 board. The CVME961 maps short address space + * 0xffffxxxx to 0xb400xxxx. + * + * Input parameters: + * address - address to convert + * + * Output parameters: + * returns - converted address + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include "shm.h" + +void *Shm_Convert_address( + void *address +) +{ + rtems_unsigned32 workaddr = (rtems_unsigned32) address; + + if ( workaddr >= 0xffff0000 ) + workaddr = (workaddr & 0xffff) | 0xb4000000; + return ( (rtems_unsigned32 *)workaddr ); +} diff --git a/c/src/lib/libbsp/i960/cvme961/shmsupp/getcfg.c b/c/src/lib/libbsp/i960/cvme961/shmsupp/getcfg.c new file mode 100644 index 0000000000..f72e715b6f --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/shmsupp/getcfg.c @@ -0,0 +1,98 @@ +/* void Shm_Get_configuration( localnode, &shmcfg ) + * + * This routine initializes, if necessary, and returns a pointer + * to the Shared Memory Configuration Table for the Cyclone CVME961. + * + * INPUT PARAMETERS: + * localnode - local node number + * shmcfg - address of pointer to SHM Config Table + * + * OUTPUT PARAMETERS: + * *shmcfg - pointer to SHM Config Table + * + * NOTES: CVME961 target system has onboard dual-ported memory. This + * file uses the USE_ONBOARD_RAM macro to determine if this + * RAM is to be used as the SHM. If so (i.e. USE_ONBOARD_RAM + * is set to 1), it is assumed that the master node's dual + * ported memory will be used and that it is configured + * correctly. The node owning the memory CANNOT access it + * using a local address. The "if" insures that the MASTER + * node uses a local address to access the dual-ported memory. + * + * The interprocessor interrupt used on the CVME961 is generated + * by the VIC068. The ICMS capablities of the VIC068 are used + * to generate interprocessor interrupts for up to eight nodes. + * + * The following table illustrates the configuration limitations: + * + * BUS MAX + * MODE ENDIAN NODES + * ========= ====== ======= + * POLLED LITTLE 2+ + * INTERRUPT LITTLE 2-8 + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include "shm.h" + +#define USE_ONBOARD_RAM 0 /* use onboard (1) or VME RAM */ + /* for SHM communications */ + +#define INTERRUPT 1 /* CVME961 target supports both */ +#define POLLING 0 /* polling and interrupt modes */ + + +shm_config_table BSP_shm_cfgtbl; + +void Shm_Get_configuration( + rtems_unsigned32 localnode, + shm_config_table **shmcfg +) +{ +#if ( USE_ONBOARD_RAM == 1 ) + if ( Shm_RTEMS_MP_Configuration->node == MASTER ) + BSP_shm_cfgtbl.base = (rtems_unsigned32 *)0x00300000; + else + BSP_shm_cfgtbl.base = (rtems_unsigned32 *)0x10300000; +#else + BSP_shm_cfgtbl.base = (rtems_unsigned32 *)0x20000000; +#endif + + BSP_shm_cfgtbl.length = 1 * MEGABYTE; + BSP_shm_cfgtbl.format = SHM_LITTLE; + + BSP_shm_cfgtbl.cause_intr = Shm_Cause_interrupt; + +#ifdef NEUTRAL_BIG + BSP_shm_cfgtbl.convert = (void *)CPU_swap_u32; +#else + BSP_shm_cfgtbl.convert = NULL_CONVERT; +#endif + +#if (POLLING==1) + BSP_shm_cfgtbl.poll_intr = POLLED_MODE; + BSP_shm_cfgtbl.Intr.address = NO_INTERRUPT; + BSP_shm_cfgtbl.Intr.value = NO_INTERRUPT; + BSP_shm_cfgtbl.Intr.length = NO_INTERRUPT; +#else + BSP_shm_cfgtbl.poll_intr = INTR_MODE; + BSP_shm_cfgtbl.Intr.address = + (rtems_unsigned32 *) (0xffff0021|((localnode-1) << 12)); + /* use ICMS0 */ + BSP_shm_cfgtbl.Intr.value = 1; + BSP_shm_cfgtbl.Intr.length = BYTE; +#endif + + *shmcfg = &BSP_shm_cfgtbl; + +} diff --git a/c/src/lib/libbsp/i960/cvme961/shmsupp/lock.c b/c/src/lib/libbsp/i960/cvme961/shmsupp/lock.c new file mode 100644 index 0000000000..de62ec670d --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/shmsupp/lock.c @@ -0,0 +1,77 @@ +/* Shared Memory Lock Routines + * + * This shared memory locked queue support routine need to be + * able to lock the specified locked queue. Interrupts are + * disabled while the queue is locked to prevent preemption + * and deadlock when two tasks poll for the same lock. + * previous level. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include "cpu.h" +#include "bsp.h" +#include "shm.h" + +/* + * Shm_Initialize_lock + * + * Initialize the lock for the specified locked queue. + */ + +void Shm_Initialize_lock( + Shm_Locked_queue_Control *lq_cb +) +{ + lq_cb->lock = LQ_UNLOCKED; +} + +/* void _Shm_Lock( &lq_cb ) + * + * This shared memory locked queue support routine locks the + * specified locked queue. It disables interrupts to prevent + * a deadlock condition. + */ + +void Shm_Lock( + Shm_Locked_queue_Control *lq_cb +) +{ + rtems_unsigned32 isr_level, oldlock; + + rtems_interrupt_disable( isr_level ); + Shm_isrstat = isr_level; + while ( 1 ) { + atomic_modify( SHM_LOCK_VALUE, &lq_cb->lock, oldlock ); + if ( !(oldlock & SHM_LOCK_VALUE) ) + return; + delay( 28 ); /* delay 28 microseconds */ + } +} + +/* + * Shm_Unlock + * + * Unlock the lock for the specified locked queue. + */ + +void Shm_Unlock( + Shm_Locked_queue_Control *lq_cb +) +{ + rtems_unsigned32 isr_level; + + lq_cb->lock = SHM_UNLOCK_VALUE; + isr_level = Shm_isrstat; + rtems_interrupt_enable( isr_level ); +} + diff --git a/c/src/lib/libbsp/i960/cvme961/shmsupp/mpisr.c b/c/src/lib/libbsp/i960/cvme961/shmsupp/mpisr.c new file mode 100644 index 0000000000..827c5e4adb --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/shmsupp/mpisr.c @@ -0,0 +1,70 @@ +/* Shm_isr_cvme961() + * + * NOTE: This routine is not used when in polling mode. Either + * this routine OR Shm_clockisr is used in a particular system. + * + * There must be sufficient time after the IACK (read at + * 0xb600000x) for the VIC068 to clear the interrupt request + * before the interrupt request is cleared from IPND (sf0). + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include "shm.h" + +rtems_isr Shm_isr_cvme961( + rtems_vector_number vector +) +{ + rtems_unsigned32 vic_vector; + + /* enable_tracing(); */ + vic_vector = (*(volatile rtems_unsigned8 *)0xb6000007); + /* reset intr by reading */ + /* vector at IPL=3 */ + Shm_Interrupt_count += 1; + rtems_multiprocessing_announce(); + (*(volatile rtems_unsigned8 *)0xa000005f) = 0; /* clear ICMS0 */ + i960_clear_intr( 6 ); + +} + +/* void _Shm_setvec( ) + * + * This driver routine sets the SHM interrupt vector to point to the + * driver's SHM interrupt service routine. + * + * NOTE: See pp. 21-22, 36-39 of the CVME961 Manual for more info. + * + * Input parameters: NONE + * + * Output parameters: NONE + */ + +void Shm_setvec() +{ + rtems_unsigned32 isrlevel; + + rtems_interrupt_disable( isrlevel ); + /* set SQSIO4 CTL REG for */ + /* VME slave address */ + (*(rtems_unsigned8 *)0xc00000b0) = + (Shm_RTEMS_MP_Configuration->node - 1) | 0x10; + set_vector( Shm_isr_cvme961, 6, 1 ); + /* set ICMS Bector Base Register */ + (*(rtems_unsigned8 *)0xa0000053) = 0x60; /* XINT6 vector is 0x62 */ + /* set ICMS Intr Control Reg */ + (*(rtems_unsigned8 *)0xa0000047) = 0xeb; /* ICMS0 enabled, IPL=0 */ + (*(rtems_unsigned8 *)0xa000005f) = 0; /* clear ICMS0 */ + rtems_interrupt_enable( isrlevel ); +} diff --git a/c/src/lib/libbsp/i960/cvme961/startup/bspclean.c b/c/src/lib/libbsp/i960/cvme961/startup/bspclean.c new file mode 100644 index 0000000000..fb35e206be --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/startup/bspclean.c @@ -0,0 +1,32 @@ +/* + * This routine is used to return control to the NINDY monitor + * and is automatically invoked at shutdown. + * + * NOTES: DOES NOT RETURN!!! + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include "bsp.h" + +void bsp_cleanup( void ) +{ + asm volatile( "mov 0,g0; \ + fmark ; \ + syncf ; \ + .word 0xfeedface ; \ + bx start" : : ); + /* The constant 0xfeedface is a magic word for break which + * is defined by NINDY. The branch extended restarts the + * application if the user types "go". + */ +} diff --git a/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c b/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c new file mode 100644 index 0000000000..afb9b7e733 --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c @@ -0,0 +1,163 @@ +/* bsp_start() + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include "libcsupport.h" + + +#include "stackchk.h" + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern rtems_configuration_table Configuration; + +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +/* Initialize whatever libc we are using + * called from postdriver hook + */ + +void bsp_libc_init() +{ + extern int end; + rtems_unsigned32 heap_start; + + heap_start = (rtems_unsigned32) &end; + if (heap_start & (CPU_ALIGNMENT-1)) + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + + RTEMS_Malloc_Initialize((void *) heap_start, 64 * 1024, 0); + + /* + * Set up for the libc handling. + */ + + if (BSP_Configuration.ticks_per_timeslice > 0) + libc_init(1); /* reentrant if possible */ + else + libc_init(0); /* non-reentrant */ + /* + * Initialize the stack bounds checker + */ + +#ifdef STACK_CHECKER_ON + Stack_check_Initialize(); +#endif +} + +int bsp_start( + int argc, + char **argv, + char **environp +) +{ + /* set node number in SQSIO4 CTL REG */ + + *((rtems_unsigned32 *)0xc00000b0) = + (Configuration.User_multiprocessing_table) ? + Configuration.User_multiprocessing_table->node : 0; + + Prcb = get_prcb(); + Ctl_tbl = Prcb->control_tbl; + + /* following configures the data breakpoint (which must be set + * before this is executed) to break on writes only. + */ + + Ctl_tbl->bpcon &= ~0x00cc0000; + i960_reload_ctl_group( 6 ); + + /* bit 31 of the Register Cache Control can be set to + * enable an alternative caching algorithm. It does + * not appear to help RTEMS. + */ + + /* Configure Number of Register Caches */ + + Prcb->reg_cache_cfg = 8; + i960_soft_reset( Prcb ); + + /* + * we do not use the pretasking_hook. + */ + + Cpu_table.pretasking_hook = NULL; + + Cpu_table.predriver_hook = bsp_libc_init; /* RTEMS resources available */ + + Cpu_table.postdriver_hook = NULL; /* Call our main() for constructors */ + + Cpu_table.idle_task = NULL; /* do not override system IDLE task */ + + Cpu_table.do_zero_of_workspace = TRUE; + + Cpu_table.interrupt_stack_size = 4096; + + Cpu_table.extra_system_initialization_stack = 0; + + Cpu_table.Prcb = Prcb; + + /* + * Copy the table + */ + + BSP_Configuration = Configuration; + + /* + * Add 1 region for the RTEMS Malloc + */ + + BSP_Configuration.maximum_regions++; + + /* + * Add 1 extension for newlib libc + */ + +#ifdef RTEMS_NEWLIB + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Add another extension if using the stack checker + */ + +#ifdef STACK_CHECKER_ON + BSP_Configuration.maximum_extensions++; +#endif + + BSP_Configuration.work_space_start = (void *) + (RAM_END - BSP_Configuration.work_space_size); + + rtems_initialize_executive( &BSP_Configuration, &Cpu_table ); + /* does not return */ + + bsp_cleanup(); + + return 0; + +} diff --git a/c/src/lib/libbsp/i960/cvme961/startup/exit.c b/c/src/lib/libbsp/i960/cvme961/startup/exit.c new file mode 100644 index 0000000000..c412cad281 --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/startup/exit.c @@ -0,0 +1,38 @@ +/* exit + * + * This routine is used to return control to the NINDY monitor + * and is automatically invoked by the STDIO exit() routine. + * + * INPUT: + * status - exit status + * + * OUTPUT: NONE + * + * NOTES: DOES NOT RETURN!!! + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include "bsp.h" + +void _exit( ) +{ + asm volatile( "mov 0,g0; \ + fmark ; \ + syncf ; \ + .word 0xfeedface ; \ + bx start" : : ); + /* The constant 0xfeedface is a magic word for break which + * is defined by NINDY. The branch extended restarts the + * application if the user types "go". + */ +} diff --git a/c/src/lib/libbsp/i960/cvme961/startup/linkcmds b/c/src/lib/libbsp/i960/cvme961/startup/linkcmds new file mode 100644 index 0000000000..5acbf22283 --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/startup/linkcmds @@ -0,0 +1,48 @@ +/* + * This file contains directives for the GNU linker which are specific + * to the Cyclone CVME960/CVME961 boards. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +MEMORY + { + ram : org = 0x0, l = 1M + } + +SECTIONS +{ + .text 0x10000 : + { + text_start = . ; + _text_start = . ; + *(.text) + etext = ALIGN( 0x10 ) ; +/* _etext = .; */ + } + .data ADDR( .text ) + SIZEOF( .text ): + { + data_start = . ; + _data_start = .; + *(.data) + edata = ALIGN( 0x10 ) ; +/* _edata = .; */ + } + .bss ADDR( .data ) + SIZEOF( .data ): + { + bss_start = . ; +/* _bss_start = . ; */ + *(.bss) + *(COMMON) + end = . ; + _end = . ; + } +} diff --git a/c/src/lib/libbsp/i960/cvme961/startup/setvec.c b/c/src/lib/libbsp/i960/cvme961/startup/setvec.c new file mode 100644 index 0000000000..ea3706c3b3 --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/startup/setvec.c @@ -0,0 +1,145 @@ +/* set_vector + * + * This routine attempts to perform all "generic" interrupt initialization + * for the specified XINT line. It is specific to the Cyclone CVME961 in + * that it knows which interrupts are initialized by the monitor, the + * characteristics of XINT5 (VIC068 clock tick), and that it assumes the + * i960 is processing interrupts in dedicated mode. It attempts to map + * XINTs to interrupt vectors in a fairly straght forward way. + * + * XINT USE VECTOR INTR TBL INDEX TRIGGERED + * ==== ============= ====== ============== ========= + * 0 VMEbus ERROR 0x02 0x03 EDGE + * 1 DRAM PARITY 0x12 0x13 EDGE + * 2 Z8530 0x22 0x23 LEVEL + * 3 SQUALL 0 0x52 0x53 ---- + * 4 Z8536 (SQSIO4) 0x72 0x73 LEVEL + * 5 TICK 0x32 0x33 EDGE + * 6 VIC068 0x62 0x63 LEVEL + * 7 UNUSED 0x42 0x43 LEVEL + * + * The interrupt handler is installed in both the cached and memory + * resident interrupt tables. The appropriate IMAP register is updated to + * reflect the vector selected by this routine. Global interrupts are + * enabled. If XINT5 is being installed, places it in trigger mode. + * Finally, set_vector_support() is invoked to install the new IMAP and + * ICON, unmask the XINT in IMASK, and lower the i960's interrupt + * level to 0. + * + * INPUT: + * func - interrupt handler entry point + * xint - external interrupt line + * type - 0 indicates raw hardware connect + * 1 indicates RTEMS interrupt connect + * + * RETURNS: + * address of previous interrupt handler + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +#include <stdio.h> + +void print_prcb(); +void print_intr_info(); +void print_ipnd_imsk(); + +unsigned int Xint_2_Group_Map[8] = { 0, 1, 2, 5, 7, 3, 6, 4 }; + +i960_isr set_vector( /* returns old vector */ + rtems_isr_entry func, /* isr routine */ + unsigned int xint, /* XINT number */ + unsigned int type /* RTEMS or RAW */ +) +{ + i960_isr *intr_tbl, *cached_intr_tbl; + i960_isr saved_intr; + unsigned int vector, group, nibble; + unsigned int *imap; + + if ( xint > 7 ) + exit( 0x80 ); + + cached_intr_tbl = (i960_isr *) 0; + intr_tbl = (i960_isr *) Prcb->intr_tbl; + group = Xint_2_Group_Map[xint]; /* remap XINT to group */ + vector = (group << 4) + 2; /* direct vector num */ + + if ( type ) + rtems_interrupt_catch( func, vector, (rtems_isr_entry *) &saved_intr ); + else { + saved_intr = (i960_isr) intr_tbl[ vector ]; + /* return old vector */ + intr_tbl[ vector + 1 ] = /* normal vector table */ + cached_intr_tbl[ group ] = (i960_isr) func; /* cached vector */ + } + + if ( xint <= 3 ) imap = &Ctl_tbl->imap0; /* updating IMAP0 */ + else imap = &Ctl_tbl->imap1; /* updating IMAP1 */ + nibble = (xint % 4) * 4; + *imap &= ~(0xf << nibble); + *imap |= group << nibble; + + Ctl_tbl->icon &= ~0x00000400; /* enable global interrupts */ + Ctl_tbl->icon |= 0x00004000; /* fast sampling mode */ + switch ( xint ) { + case 0: Ctl_tbl->icon |= 0x00000004; break; + case 1: Ctl_tbl->icon |= 0x00000008; break; + case 2: Ctl_tbl->icon &= ~0x00000010; break; + case 4: Ctl_tbl->icon &= ~0x00000040; break; + case 5: Ctl_tbl->icon |= 0x00000080; break; + case 6: Ctl_tbl->icon &= ~0x00000100; break; + default: exit( 0x81 ); break; /* unsupported */ + } + + if ( xint == 4 ) { /* reprogram MCON for SQSIO4 */ + Ctl_tbl->mcon12 = 0x00002012; /* MCON12 - 0xCxxxxxxx */ + Ctl_tbl->mcon13 = 0x00000000; /* MCON13 - 0xDxxxxxxx */ + i960_reload_ctl_group( 5 ); /* update MCON12-MCON15 */ + } + + i960_unmask_intr( xint ); /* update IMSK */ + i960_reload_ctl_group( 1 ); /* update IMAP?/ICON */ + return( saved_intr ); /* return old vector */ +} + +void print_prcb() +{ + printf( "fault_table =0x%p\n", Prcb->fault_tbl ); + printf( "control_tbl =0x%p\n", Prcb->control_tbl ); + printf( "AC mask ov =0x%x\n", Prcb->initial_ac ); + printf( "fltconfig =0x%x\n", Prcb->fault_config ); + printf( "intr tbl =0x%p\n", Prcb->intr_tbl ); + printf( "systable =0x%p\n", Prcb->sys_proc_tbl ); + printf( "reserved =0x%x\n", Prcb->reserved ); + printf( "isr stk =0x%p\n", Prcb->intr_stack ); + printf( "ins cache =0x%x\n", Prcb->ins_cache_cfg ); + printf( "reg cache =0x%x\n", Prcb->reg_cache_cfg ); +} + +void print_intr_info() +{ + printf( "prcb =0x%p\n", Prcb ); + printf( "ctl_tbl =0x%p\n", Ctl_tbl ); + printf( "intr_tbl=0x%p\n", Prcb->intr_tbl ); + printf( "IMAP0 = 0x%x\n", Ctl_tbl->imap0 ); + printf( "IMAP1 = 0x%x\n", Ctl_tbl->imap1 ); + print_ipnd_imsk(); +} + +void print_ipnd_imsk() +{ + printf(" IPEND = 0x%x\n", i960_pend_intrs() ); + printf(" IMASK = 0x%x\n", i960_mask_intrs() ); +} diff --git a/c/src/lib/libbsp/i960/cvme961/timer/timer.c b/c/src/lib/libbsp/i960/cvme961/timer/timer.c new file mode 100644 index 0000000000..0a91d12a93 --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/timer/timer.c @@ -0,0 +1,107 @@ +/* Timer_init() + * + * This routine initializes the Z8536 timer on the SQSIO4 SQUALL + * board for the CVME961 board. The timer is setup to provide a + * tick every 1 millisecond. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * NOTE: This routine will not work if the optimizer is enabled + * for most compilers. The multiple writes to the Z8536 + * will be optimized away. + * + * It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + + +#include <rtems.h> +#include <bsp.h> +#include "z8536.h" + +#define TIMER 0xc00000a0 + +int Ttimer_val; +rtems_boolean Timer_driver_Find_average_overhead; + +void flush_reg(); +rtems_isr timerisr(); + +void Timer_initialize() +{ + set_vector( timerisr, 4, 0 ); /* install ISR */ + + i960_mask_intr( 5 ); /* disable VIC068 tick */ + flush_reg(); /* timed code starts clean */ + Ttimer_val = 0; /* clear timer ISR count */ + Z8x36_WRITE( TIMER, MASTER_INTR, 0x01 ); /* reset */ + Z8x36_WRITE( TIMER, MASTER_INTR, 0x00 ); /* clear reset */ + Z8x36_WRITE( TIMER, MASTER_CFG, 0x00 ); /* disable everything */ + Z8x36_WRITE( TIMER, CNT_TMR_VECTOR, 0x72 ); /* clear intr vector */ + Z8x36_WRITE( TIMER, MASTER_CFG, 0x20 ); /* clear intr info */ + Z8x36_WRITE( TIMER, MASTER_CFG, 0xe0 ); /* disable interrupts */ + Z8x36_WRITE( TIMER, MASTER_CFG, 0x20 ); /* clear intr info */ + Z8x36_WRITE( TIMER, MASTER_CFG, 0xe0 ); /* disable interrupts */ + Z8x36_WRITE( TIMER, MASTER_INTR, 0xe2 ); /* disable lower chain, */ + /* no vector, set right */ + /* justified addr and */ + /* master int enable */ + Z8x36_WRITE( TIMER, CT1_MODE_SPEC, 0x80 ); /* T1 continuous, and */ + /* cycle/pulse output */ + Z8x36_WRITE( TIMER, CT1_TIME_CONST_MSB, 0x00 ); + Z8x36_WRITE( TIMER, CT1_TIME_CONST_LSB, 0x00 ); + Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xc0 ); /* set INTR enable (IE) */ + Z8x36_WRITE( TIMER, MASTER_CFG, 0x40 ); /* enable timer1 */ + Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0x06 ); /* set trigger command */ + /* (TCB) and gate */ + /* command (GCB) bits */ +} + +#define AVG_OVERHEAD 11 /* It typically takes 5.5 microseconds */ + /* (11 countdowns) to start/stop the timer. */ +#define LEAST_VALID 15 /* Don't trust a value lower than this */ + +int Read_timer() +{ + rtems_unsigned8 msb, lsb; + rtems_unsigned32 remaining, total; + + Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xce ); /* read the counter value */ + Z8x36_READ( TIMER, CT1_CUR_CNT_MSB, msb ); + Z8x36_READ( TIMER, CT1_CUR_CNT_LSB, lsb ); + + remaining = 0xffff - ((msb << 8) + lsb); + total = (Ttimer_val * 0x10000) + remaining; + + if ( Timer_driver_Find_average_overhead == 1 ) + return total; /* in one-half microsecond units */ + else { + if ( total < LEAST_VALID ) + return 0; /* below timer resolution */ + return (total-AVG_OVERHEAD) >> 1; + } +} + +rtems_status_code Empty_function( void ) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead( + rtems_boolean find_flag +) +{ + Timer_driver_Find_average_overhead = find_flag; +} diff --git a/c/src/lib/libbsp/i960/cvme961/timer/timerisr.s b/c/src/lib/libbsp/i960/cvme961/timer/timerisr.s new file mode 100644 index 0000000000..02dc23cd5c --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/timer/timerisr.s @@ -0,0 +1,59 @@ +/* timer_isr() + * + * This routine initializes the Z8536 timer on the SQSIO4 SQUALL + * board for the CVME961 board. The timer is setup to provide a + * tick every 0x10000 / 2 milliseconds. This is used to time + * executing code. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include "asm.h" + +.set PORT_A, 0xc00000a8 # port A +.set PORT_B, 0xc00000a4 # port B +.set PORT_C, 0xc00000a0 # port C +.set CTL_PORT, 0xc00000ac # control port + +.set T1CSR, 0x0a # T1 command/status reg +.set RELOAD, 0x24 # clr IP & IUS,allow countdown + + PUBLIC(_timerisr) +SYM (_timerisr): + #ldconst 1,r4 + #modpc 0,r4,r4 # enable tracing + + ld _Ttimer_val,r6 # r6 = test timer + + ldconst T1CSR,r4 # r4 = T1 control status reg + stob r4,CTL_PORT # select T1CSR + ldconst RELOAD,r5 # r5 = reset value + stob r5,CTL_PORT # reset countdown + addo 1,r6,r6 + st r6,_Ttimer_val # increment test timer +loop_til_cleared: + clrbit 4,sf0,sf0 + bbs 4,sf0,loop_til_cleared +leaf: ret + + .leafproc _flush_reg, flush_reg.lf + .globl _flush_reg, flush_reg.lf +_flush_reg: + lda leaf,g14 # g14 = exit address +flush_reg.lf: + flushreg + mov g14,g0 # g0 = exit address + ldconst 0,g14 # set g14 for non-leaf + bx (g0) |