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Diffstat (limited to 'c/src/lib/libbsp/arm/stm32f4/include')
-rw-r--r--c/src/lib/libbsp/arm/stm32f4/include/bsp.h40
-rw-r--r--c/src/lib/libbsp/arm/stm32f4/include/irq.h126
-rw-r--r--c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h167
-rw-r--r--c/src/lib/libbsp/arm/stm32f4/include/usart.h30
4 files changed, 363 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/bsp.h b/c/src/lib/libbsp/arm/stm32f4/include/bsp.h
new file mode 100644
index 0000000000..e2c1ae4236
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/bsp.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_BSP_H
+#define LIBBSP_ARM_STM32F4_BSP_H
+
+#include <bspopts.h>
+
+#include <rtems.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4)
+
+#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4)
+
+#define BSP_ARMV7M_SYSTICK_FREQUENCY STM32F4_HCLK
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_STM32F4_BSP_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/irq.h b/c/src/lib/libbsp/arm/stm32f4/include/irq.h
new file mode 100644
index 0000000000..099c9417d7
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/irq.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_IRQ_H
+#define LIBBSP_ARM_STM32F4_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#define STM32F4_IRQ_WWDG 0
+#define STM32F4_IRQ_PVD 1
+#define STM32F4_IRQ_TAMP_STAMP 2
+#define STM32F4_IRQ_RTC_WKUP 3
+#define STM32F4_IRQ_FLASH 4
+#define STM32F4_IRQ_RCC 5
+#define STM32F4_IRQ_EXTI0 6
+#define STM32F4_IRQ_EXTI1 7
+#define STM32F4_IRQ_EXTI2 8
+#define STM32F4_IRQ_EXTI3 9
+#define STM32F4_IRQ_EXTI4 10
+#define STM32F4_IRQ_DMA1_STREAM0 11
+#define STM32F4_IRQ_DMA1_STREAM1 12
+#define STM32F4_IRQ_DMA1_STREAM2 13
+#define STM32F4_IRQ_DMA1_STREAM3 14
+#define STM32F4_IRQ_DMA1_STREAM4 15
+#define STM32F4_IRQ_DMA1_STREAM5 16
+#define STM32F4_IRQ_DMA1_STREAM6 17
+#define STM32F4_IRQ_ADC 18
+#define STM32F4_IRQ_CAN1_TX 19
+#define STM32F4_IRQ_CAN1_RX0 20
+#define STM32F4_IRQ_CAN1_RX1 21
+#define STM32F4_IRQ_CAN1_SCE 22
+#define STM32F4_IRQ_EXTI9_5 23
+#define STM32F4_IRQ_TIM1_BRK_TIM9 24
+#define STM32F4_IRQ_TIM1_UP_TIM10 25
+#define STM32F4_IRQ_TIM1_TRG_COM_TIM11 26
+#define STM32F4_IRQ_TIM1_CC 27
+#define STM32F4_IRQ_TIM2 28
+#define STM32F4_IRQ_TIM3 29
+#define STM32F4_IRQ_TIM4 30
+#define STM32F4_IRQ_I2C1_EV 31
+#define STM32F4_IRQ_I2C1_ER 32
+#define STM32F4_IRQ_I2C2_EV 33
+#define STM32F4_IRQ_I2C2_ER 34
+#define STM32F4_IRQ_SPI1 35
+#define STM32F4_IRQ_SPI2 36
+#define STM32F4_IRQ_USART1 37
+#define STM32F4_IRQ_USART2 38
+#define STM32F4_IRQ_USART3 39
+#define STM32F4_IRQ_EXTI15_10 40
+#define STM32F4_IRQ_RTC_ALARM 41
+#define STM32F4_IRQ_OTG_FS_WKUP 42
+#define STM32F4_IRQ_TIM8_BRK_TIM12 43
+#define STM32F4_IRQ_TIM8_UP_TIM13 44
+#define STM32F4_IRQ_TIM8_TRG_COM_TIM14 45
+#define STM32F4_IRQ_TIM8_CC 46
+#define STM32F4_IRQ_DMA1_STREAM7 47
+#define STM32F4_IRQ_FSMC 48
+#define STM32F4_IRQ_SDIO 49
+#define STM32F4_IRQ_TIM5 50
+#define STM32F4_IRQ_SPI3 51
+#define STM32F4_IRQ_UART4 52
+#define STM32F4_IRQ_UART5 53
+#define STM32F4_IRQ_TIM6_DAC 54
+#define STM32F4_IRQ_TIM7 55
+#define STM32F4_IRQ_DMA2_STREAM0 56
+#define STM32F4_IRQ_DMA2_STREAM1 57
+#define STM32F4_IRQ_DMA2_STREAM2 58
+#define STM32F4_IRQ_DMA2_STREAM3 59
+#define STM32F4_IRQ_DMA2_STREAM4 60
+#define STM32F4_IRQ_ETH 61
+#define STM32F4_IRQ_ETH_WKUP 62
+#define STM32F4_IRQ_CAN2_TX 63
+#define STM32F4_IRQ_CAN2_RX0 64
+#define STM32F4_IRQ_CAN2_RX1 65
+#define STM32F4_IRQ_CAN2_SCE 66
+#define STM32F4_IRQ_OTG_FS 67
+#define STM32F4_IRQ_DMA2_STREAM5 68
+#define STM32F4_IRQ_DMA2_STREAM6 69
+#define STM32F4_IRQ_DMA2_STREAM7 70
+#define STM32F4_IRQ_USART6 71
+#define STM32F4_IRQ_I2C3_EV 72
+#define STM32F4_IRQ_I2C3_ER 73
+#define STM32F4_IRQ_OTG_HS_EP1_OUT 74
+#define STM32F4_IRQ_OTG_HS_EP1_IN 75
+#define STM32F4_IRQ_OTG_HS_WKUP 76
+#define STM32F4_IRQ_OTG_HS 77
+#define STM32F4_IRQ_DCMI 78
+#define STM32F4_IRQ_CRYP 79
+#define STM32F4_IRQ_HASH_RNG 80
+#define STM32F4_IRQ_FPU 81
+
+#define STM32F4_IRQ_PRIORITY_VALUE_MIN 0
+#define STM32F4_IRQ_PRIORITY_VALUE_MAX 15
+#define STM32F4_IRQ_PRIORITY_COUNT (STM32F4_IRQ_PRIORITY_VALUE_MAX + 1)
+#define STM32F4_IRQ_PRIORITY_HIGHEST STM32F4_IRQ_PRIORITY_VALUE_MIN
+#define STM32F4_IRQ_PRIORITY_LOWEST STM32F4_IRQ_PRIORITY_VALUE_MAX
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+#define BSP_INTERRUPT_VECTOR_MAX 81
+
+#endif /* LIBBSP_ARM_STM32F4_IRQ_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
new file mode 100644
index 0000000000..683012b08a
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4_H
+#define LIBBSP_ARM_STM32F4_STM32F4_H
+
+#include <bsp/utility.h>
+
+#define STM32F4_BASE 0x00
+
+typedef struct {
+ uint32_t reserved_00 [16];
+ uint32_t apb1enr;
+#define STM32F4_RCC_APB1ENR_DAC_EN BSP_BIT32(29)
+#define STM32F4_RCC_APB1ENR_PWR_EN BSP_BIT32(28)
+#define STM32F4_RCC_APB1ENR_CAN2_EN BSP_BIT32(26)
+#define STM32F4_RCC_APB1ENR_CAN1_EN BSP_BIT32(25)
+#define STM32F4_RCC_APB1ENR_I2C3_EN BSP_BIT32(23)
+#define STM32F4_RCC_APB1ENR_I2C2_EN BSP_BIT32(22)
+#define STM32F4_RCC_APB1ENR_I2C1_EN BSP_BIT32(21)
+#define STM32F4_RCC_APB1ENR_UART5_EN BSP_BIT32(20)
+#define STM32F4_RCC_APB1ENR_UART4_EN BSP_BIT32(19)
+#define STM32F4_RCC_APB1ENR_USART3_EN BSP_BIT32(18)
+#define STM32F4_RCC_APB1ENR_USART2_EN BSP_BIT32(17)
+#define STM32F4_RCC_APB1ENR_SPI3_EN BSP_BIT32(15)
+#define STM32F4_RCC_APB1ENR_SPI2_EN BSP_BIT32(14)
+#define STM32F4_RCC_APB1ENR_WWDG_EN BSP_BIT32(11)
+#define STM32F4_RCC_APB1ENR_TIM14_EN BSP_BIT32(8)
+#define STM32F4_RCC_APB1ENR_TIM13_EN BSP_BIT32(7)
+#define STM32F4_RCC_APB1ENR_TIM12_EN BSP_BIT32(6)
+#define STM32F4_RCC_APB1ENR_TIM7_EN BSP_BIT32(5)
+#define STM32F4_RCC_APB1ENR_TIM6_EN BSP_BIT32(4)
+#define STM32F4_RCC_APB1ENR_TIM5_EN BSP_BIT32(3)
+#define STM32F4_RCC_APB1ENR_TIM4_EN BSP_BIT32(2)
+#define STM32F4_RCC_APB1ENR_TIM3_EN BSP_BIT32(1)
+#define STM32F4_RCC_APB1ENR_TIM2_EN BSP_BIT32(0)
+ uint32_t apb2enr;
+#define STM32F4_RCC_APB2ENR_TIM11 BSP_BIT32(18)
+#define STM32F4_RCC_APB2ENR_TIM10_EN BSP_BIT32(17)
+#define STM32F4_RCC_APB2ENR_TIM9_EN BSP_BIT32(16)
+#define STM32F4_RCC_APB2ENR_SYSCFG_EN BSP_BIT32(14)
+#define STM32F4_RCC_APB2ENR_SPI1_EN BSP_BIT32(12)
+#define STM32F4_RCC_APB2ENR_SDIO_EN BSP_BIT32(11)
+#define STM32F4_RCC_APB2ENR_ADC3_EN BSP_BIT32(10)
+#define STM32F4_RCC_APB2ENR_ADC2_EN BSP_BIT32(9)
+#define STM32F4_RCC_APB2ENR_ADC1_EN BSP_BIT32(8)
+#define STM32F4_RCC_APB2ENR_USART6_EN BSP_BIT32(5)
+#define STM32F4_RCC_APB2ENR_USART1_EN BSP_BIT32(4)
+#define STM32F4_RCC_APB2ENR_TIM8_EN BSP_BIT32(1)
+#define STM32F4_RCC_APB2ENR_TIM1_EN BSP_BIT32(0)
+} stm32f4_rcc;
+
+#define STM32F4_RCC (*(volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800))
+
+typedef struct {
+ uint32_t sr;
+#define STM32F4_USART_SR_CTS BSP_BIT32(9)
+#define STM32F4_USART_SR_LBD BSP_BIT32(8)
+#define STM32F4_USART_SR_TXE BSP_BIT32(7)
+#define STM32F4_USART_SR_TC BSP_BIT32(6)
+#define STM32F4_USART_SR_RXNE BSP_BIT32(5)
+#define STM32F4_USART_SR_IDLE BSP_BIT32(4)
+#define STM32F4_USART_SR_ORE BSP_BIT32(3)
+#define STM32F4_USART_SR_NF BSP_BIT32(2)
+#define STM32F4_USART_SR_FE BSP_BIT32(1)
+#define STM32F4_USART_SR_PE BSP_BIT32(0)
+ uint32_t dr;
+#define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7)
+#define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+ uint32_t bbr;
+#define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15)
+#define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15)
+#define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15)
+#define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3)
+#define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+ uint32_t cr1;
+#define STM32F4_USART_CR1_OVER8 BSP_BIT32(15)
+#define STM32F4_USART_CR1_UE BSP_BIT32(13)
+#define STM32F4_USART_CR1_M BSP_BIT32(12)
+#define STM32F4_USART_CR1_WAKE BSP_BIT32(11)
+#define STM32F4_USART_CR1_PCE BSP_BIT32(10)
+#define STM32F4_USART_CR1_PS BSP_BIT32(9)
+#define STM32F4_USART_CR1_PEIE BSP_BIT32(8)
+#define STM32F4_USART_CR1_TXEIE BSP_BIT32(7)
+#define STM32F4_USART_CR1_TCIE BSP_BIT32(6)
+#define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5)
+#define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4)
+#define STM32F4_USART_CR1_TE BSP_BIT32(3)
+#define STM32F4_USART_CR1_RE BSP_BIT32(2)
+#define STM32F4_USART_CR1_RWU BSP_BIT32(1)
+#define STM32F4_USART_CR1_SBK BSP_BIT32(0)
+ uint32_t cr2;
+#define STM32F4_USART_CR2_LINEN BSP_BIT32(14)
+#define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13)
+#define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13)
+#define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
+#define STM32F4_USART_CR2_CLKEN BSP_BIT32(11)
+#define STM32F4_USART_CR2_CPOL BSP_BIT32(10)
+#define STM32F4_USART_CR2_CPHA BSP_BIT32(9)
+#define STM32F4_USART_CR2_LBCL BSP_BIT32(8)
+#define STM32F4_USART_CR2_LBDIE BSP_BIT32(6)
+#define STM32F4_USART_CR2_LBDL BSP_BIT32(5)
+#define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3)
+#define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+ uint32_t cr3;
+#define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11)
+#define STM32F4_USART_CR3_CTSIE BSP_BIT32(10)
+#define STM32F4_USART_CR3_CTSE BSP_BIT32(9)
+#define STM32F4_USART_CR3_RTSE BSP_BIT32(8)
+#define STM32F4_USART_CR3_DMAT BSP_BIT32(7)
+#define STM32F4_USART_CR3_DMAR BSP_BIT32(6)
+#define STM32F4_USART_CR3_SCEN BSP_BIT32(5)
+#define STM32F4_USART_CR3_NACK BSP_BIT32(4)
+#define STM32F4_USART_CR3_HDSEL BSP_BIT32(3)
+#define STM32F4_USART_CR3_IRLP BSP_BIT32(2)
+#define STM32F4_USART_CR3_IREN BSP_BIT32(1)
+#define STM32F4_USART_CR3_EIE BSP_BIT32(0)
+ uint32_t gtpr;
+#define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15)
+#define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7)
+#define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+} stm32f4_usart;
+
+#define STM32F4_USART_1 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000))
+#define STM32F4_USART_2 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400))
+#define STM32F4_USART_3 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800))
+#define STM32F4_USART_4 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00))
+#define STM32F4_USART_5 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000))
+#define STM32F4_USART_6 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400))
+
+typedef struct {
+ uint32_t reserved_00 [268439808];
+ stm32f4_usart usart_2;
+ uint32_t reserved_4000441c [249];
+ stm32f4_usart usart_3;
+ uint32_t reserved_4000481c [249];
+ stm32f4_usart usart_4;
+ uint32_t reserved_40004c1c [249];
+ stm32f4_usart usart_5;
+ uint32_t reserved_4000501c [12281];
+ stm32f4_usart usart_1;
+ uint32_t reserved_4001101c [249];
+ stm32f4_usart usart_6;
+ uint32_t reserved_4001141c [18681];
+ stm32f4_rcc rcc;
+} stm32f4;
+
+#define STM32F4 (*(volatile stm32f4 *) (STM32F4_BASE))
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/usart.h b/c/src/lib/libbsp/arm/stm32f4/include/usart.h
new file mode 100644
index 0000000000..ee1e8bb39e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/usart.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_USART_H
+#define LIBBSP_ARM_STM32F4_USART_H
+
+#include <libchip/serial.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+extern console_fns stm32f4_usart_fns;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_STM32F4_USART_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-10 12:27:21 +0000